CN104572334A - Decoding method, memory storage device and memory control circuit unit - Google Patents

Decoding method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN104572334A
CN104572334A CN201310479133.7A CN201310479133A CN104572334A CN 104572334 A CN104572334 A CN 104572334A CN 201310479133 A CN201310479133 A CN 201310479133A CN 104572334 A CN104572334 A CN 104572334A
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voltage
those
decoding
reading
read
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CN104572334B (en
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林纬
严绍维
林玉祥
赖国欣
郑国义
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The decoding method comprises the following steps: reading a plurality of storage units according to first reading voltages to obtain a first verification bit; executing a decoding program containing a probability decoding algorithm according to the first verification bit to generate a plurality of first decoding bits, and judging whether decoding succeeds or not by utilizing the first decoding bits; if the decoding fails, reading the storage units according to second reading voltages to obtain a second verification bit; executing the decoding program according to the second verification bit to generate a plurality of second decoding bits, wherein the second reading voltages are different from the first reading voltages, and the number of the second reading voltages is equal to that of the first reading voltages. Thus, the error correcting capacity can be improved.

Description

Coding/decoding method, memory storage apparatus and memorizer control circuit unit
Technical field
The invention relates to a kind of coding/decoding method, and relate to a kind of coding/decoding method of reproducible nonvolatile memorizer module, memory storage apparatus and memorizer control circuit unit especially.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to storage medium is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be built in above-mentioned illustrated various portable multimedia devices in being applicable to very much.
In general, the data be stored in reproducible nonvolatile memorizer module can add some error correcting codes (error correcting code, abbreviation: ECC).The algebraic decoding algorithms of error correcting code many uses in the past, as (BCH code), and current probability decoding algorithm, as low-density parity check code, (lowdensity parity code, is called for short: LDPC), then ripe gradually.Low-density parity check code is that use sparse matrix (sparse matrix) carrys out encoding and decoding.The kernel (null space) of this sparse matrix just contains all effective code words (valid codeword).Distance between these effective code words is larger, then the number of bits can corrected is more.But the distance between these effective code words is not fixing, therefore, the number of bits that can correct neither be fixed.For example, in a code word (codeword), have 4 bits to there occurs mistake, and the low-density parity check code of correspondence can correct these mistakes; But in same code word, if there are other 3 bits to there occurs mistake, then corresponding low-density parity check code but possibly cannot correct these mistakes.In addition, use different sparse matrixes, the error correction capacity of low-density parity check code also can not be identical.
Fig. 1 is the error rate curves figure of low-density parity check code in prior art.
Please refer to Fig. 1, transverse axis be former wrong bitrate (raw bit error rate, is called for short: RBER), refer to the ratio that data before the decoding make a mistake; The longitudinal axis is that (uncorrectable bit error rate, is called for short: UBER) wrong bitrate that can not correct, and institute refers to the ratio that makes a mistake after decoding.What curve 180 represented is the first matrix, and curve 190 representative is the second matrix.First matrix has identical size with the second matrix, namely has identical code check (code rate) by the code word that these two matrixes produce.But the first matrix is not identical with the element in the second matrix.There is lower UBER at wrong ground district (errorfloor region) inner curve 180, but have lower UBER at waterfall district (waterfall region) inner curve 190.In other words, there is balance between curve 180 and curve 190.Therefore, how under the condition of same code rate, to promote the ability of righting the wrong, for this reason the subject under discussion be concerned about of those skilled in the art.
Summary of the invention
The invention provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit, the ability of righting the wrong can be promoted.
One embodiment of the invention provides a kind of coding/decoding method, and for reproducible nonvolatile memorizer module, it comprises multiple storage unit.This coding/decoding method comprises: read multiple first storage unit according at least one first reading voltage, to obtain at least one first checking bit of each the first storage unit; According to the first checking bit perform comprise a probability decoding algorithm the first decoding program to produce multiple first decoded bits, and utilize the first decoded bits to judge whether successfully decoded; And if decode unsuccessfully, read the first storage unit to obtain at least one second checking bit of each the first storage unit according at least one second reading voltage, perform the first decoding program to produce multiple second decoded bits according to the second checking bit.Wherein the second reading voltage is different from the first reading voltage, and the second number reading voltage is same as the number of the first reading voltage.
In an embodiment of the present invention, above-mentioned coding/decoding method also comprises: according to first read voltage one of them and one preset the difference read between voltage obtain an off-set value; Utilize off-set value adjustment to preset and read voltage to obtain the second reading voltage.
In an embodiment of the present invention, the first number reading voltage is 1, and the default voltage that reads reads voltage and second between first to read between voltage.
In an embodiment of the present invention, the above-mentioned step obtaining off-set value comprises: by first read voltage one of them and preset the difference read between voltage be multiplied by a multiplier to obtain off-set value.
In an embodiment of the present invention, above-mentioned coding/decoding method also comprises: utilize the second decoded bits to judge whether successfully decoded; If utilize the second decoded bits to judge to decode unsuccessfully, judge that whether the number of times again obtaining the second reading voltage is more than a preset times; If the number of times again obtaining the second reading voltage does not exceed preset times, again the second reading voltage is obtained, read voltage according to again obtain second and read the first storage unit again to obtain the second checking bit, the second checking bit according to again obtaining performs the first decoding program; And if the number of times again obtaining the second reading voltage exceedes preset times, stop again obtaining the second reading voltage.
In an embodiment of the present invention, the above-mentioned first number and second reading voltage reads the number of voltage is 1.Coding/decoding method also comprises: if the number of times again obtaining the second reading voltage exceedes preset times, according to multiple third reading power taking pressure reading first storage unit, to obtain multiple 3rd checking bits of each the first storage unit; One of them of setting third reading power taking pressure is that the first sign reads voltage; Read the 3rd of voltage and each the first storage unit according to the first sign and verify that bit obtains one of each the first storage unit and to decode initial value; Second decoding program is performed to obtain multiple 3rd decoded bits to decoding initial value; The 3rd decoded bits is utilized to judge whether successfully decoded; If utilize the 3rd decoded bits to judge to decode unsuccessfully, wherein another of setting third reading power taking pressure is that the second sign reads voltage, read voltage and the 3rd according to the second sign and verify that bit obtains decoding initial value again, and perform the second decoding program according to the decoding initial value again obtained.
In an embodiment of the present invention, it is the centre being positioned at third reading power taking pressure that the first above-mentioned sign reads voltage, and the second sign reading voltage is positioned at the side that the first sign reads voltage.Coding/decoding method also comprises: if the second decoding program utilizing the second sign to read performed by voltage does not have successfully decoded, setting third reading power taking pressure wherein more another is that the 3rd sign reads voltage, read voltage and the 3rd according to the 3rd sign and verify that bit obtains decoding initial value again, and perform the second decoding program according to the decoding initial value again obtained.Wherein the 3rd sign reads the opposite side that voltage is positioned at the first sign reading voltage.
In an embodiment of the present invention, above-mentioned coding/decoding method also comprises: read voltage for different signs, and the 3rd checking bit is inputed to different look-up tables, again to obtain decoding initial value.
In an embodiment of the present invention, above-mentioned probability decoding algorithm is low-density parity check code.
In an embodiment of the present invention, above-mentioned those first decoded bits that utilize judge whether that the step of successfully decoded comprises: produce multiple syndrome according to those first decoded bits; Judge whether the first decoded bits forms effective code word according to syndrome; If the first decoded bits forms effective code word, judge successfully decoded.
One embodiment of the invention provides a kind of memory storage apparatus, comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is electrically connected to a host computer system.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, in order to read multiple first storage unit according at least one first reading voltage, to obtain at least one first checking bit of each the first storage unit.Memorizer control circuit unit in order to perform according to the first checking bit comprise a probability decoding algorithm the first decoding program to produce multiple first decoded bits, and utilize the first decoded bits to judge whether successfully decoded.If decode unsuccessfully, memorizer control circuit unit in order to read the first storage unit according at least one second reading voltage to obtain at least one second checking bit of each the first storage unit, and performs the first decoding program to produce multiple second decoded bits according to the second checking bit.Wherein the second reading voltage is different from the first reading voltage, and the second number reading voltage is same as the number of the first reading voltage.
In an embodiment of the present invention, above-mentioned memorizer control circuit unit also in order to according to first read voltage one of them and one preset the difference read between voltage obtain an off-set value, and utilize off-set value adjust preset reading voltage to obtain the second reading voltage.
In an embodiment of the present invention, above-mentioned memorizer control circuit unit by first read voltage one of them and preset the difference read between voltage be multiplied by a multiplier to obtain off-set value.
In an embodiment of the present invention, above-mentioned memorizer control circuit unit is also in order to utilize the second decoded bits to judge whether successfully decoded.If utilize the second decoded bits to judge to decode unsuccessfully, memorizer control circuit unit is in order to judge that whether the number of times again obtaining the second reading voltage is more than a preset times.If the number of times again obtaining the second reading voltage does not exceed preset times, memorizer control circuit unit is in order to again to obtain the second reading voltage, read voltage according to again obtain second and read the first storage unit again to obtain the second checking bit, and perform the first decoding program according to the second checking bit again obtained.If the number of times again obtaining the second reading voltage exceedes preset times, memorizer control circuit unit is in order to stop again obtaining the second reading voltage.
In an embodiment of the present invention, the number that the first above-mentioned number and second reading voltage reads voltage is 1.If the number of times again obtaining the second reading voltage exceedes preset times, memorizer control circuit unit, in order to according to multiple third reading power taking pressure reading first storage unit, verifies bits with the obtain each the first storage unit the multiple 3rd.Memorizer control circuit unit is also that the first sign reads voltage in order to one of them setting third reading power taking pressure, and reads the 3rd of voltage and each storage unit according to the first sign and verify that bit obtains one of each the first storage unit and to decode initial value.Memorizer control circuit unit also in order to perform the second decoding program to obtain multiple 3rd decoded bits to decoding initial value, and utilizes the 3rd decoded bits to judge whether successfully decoded.If utilize the 3rd decoded bits to judge to decode unsuccessfully, memorizer control circuit unit is that the second sign reads voltage in order to set wherein another of third reading power taking pressure, read voltage and the 3rd according to the second sign and verify that bit obtains decoding initial value again, and perform the second decoding program according to the decoding initial value again obtained.
In an embodiment of the present invention, it is the centre being positioned at third reading power taking pressure that the first above-mentioned sign reads voltage, and the second sign reading voltage is positioned at the side that the first sign reads voltage.If the second decoding program utilizing the second sign to read performed by voltage does not have successfully decoded, memorizer control circuit unit in order to set third reading power taking pressure wherein more another be the 3rd sign read voltage, read voltage and the 3rd according to the 3rd sign and verify that bit obtains decoding initial value again, and perform the second decoding program according to the decoding initial value again obtained.Wherein the 3rd sign reads the opposite side that voltage is positioned at the first sign reading voltage.
In an embodiment of the present invention, the operation of memorizer control circuit unit judges whether successfully decoded comprises: memorizer control circuit unit produces multiple syndrome according to the first decoded bits and judges according to syndrome whether the first decoded bits forms effective code word.If the first decoded bits forms effective code word, memorizer control circuit unit judges successfully decoded.
One embodiment of the invention provides a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module.This memorizer control circuit unit comprises host interface, memory interface, bug check and correcting circuit and memory management circuitry.Host interface is electrically connected to a host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface, in order to according to multiple first storage unit at least one first reading voltage reading cells, to obtain at least one first checking bit of each the first storage unit.Memory management circuitry in order to according at least one first read voltage read multiple first storage unit, with obtain each the first storage unit at least one first checking bit.Bug check and correcting circuit to verify bit to perform that the first decoding program comprising a probability decoding algorithm is to produce multiple first decoded bits according to first, and utilize the first decoded bits to judge whether successfully decoded.If decode unsuccessfully, memory management circuitry is in order to read the first storage unit to obtain at least one second checking bit of each the first storage unit according at least one second reading voltage, and according to second, bug check and correcting circuit are in order to verify bit to perform that the first decoding program is to produce multiple second decoded bits.Wherein the second reading voltage is different from the first reading voltage, and the second number reading voltage is same as the number of the first reading voltage.
In an embodiment of the present invention, above-mentioned memory management circuitry also in order to according to first read voltage one of them and one preset the difference read between voltage obtain an off-set value, and utilize off-set value adjust preset reading voltage to obtain the second reading voltage.
In an embodiment of the present invention, above-mentioned memory management circuitry by first read voltage one of them and preset the difference read between voltage be multiplied by a multiplier to obtain off-set value.
In an embodiment of the present invention, above-mentioned memory management circuitry is also in order to utilize the second decoded bits to judge whether successfully decoded.If utilize the second decoded bits to judge to decode unsuccessfully, memory management circuitry is in order to judge that whether the number of times again obtaining the second reading voltage is more than a preset times.If the number of times again obtaining the second reading voltage does not exceed preset times, memory management circuitry in order to again to obtain the second reading voltage, and reads the first storage unit again to obtain the second checking bit according to the second reading voltage again obtained.According to again obtain second, bug check and correcting circuit are in order to verify that bit performs the first decoding program.If the number of times again obtaining the second reading voltage exceedes preset times, memory management circuitry is in order to stop again obtaining the second reading voltage.
In an embodiment of the present invention, the number that the first above-mentioned number and second reading voltage reads voltage is 1.If the number of times again obtaining the second reading voltage exceedes preset times, memory management circuitry, in order to according to multiple third reading power taking pressure reading first storage unit, verifies bits with the obtain each the first storage unit the multiple 3rd.Memory management circuitry is also that the first sign reads voltage in order to one of them setting third reading power taking pressure, and reads the 3rd of voltage and each storage unit according to the first sign and verify that bit obtains one of each the first storage unit and to decode initial value.Bug check and correcting circuit also in order to perform the second decoding program to initial value of decoding to obtain multiple 3rd decoded bits, and utilize the 3rd decoded bits to judge whether successfully decoded.If utilize the 3rd decoded bits to judge decode unsuccessfully, memory management circuitry is the second sign reading voltage in order to set wherein another of third reading power taking pressure, and verifies that bit obtains decoding initial value again according to the second sign reading voltage and the 3rd.Bug check and correcting circuit are in order to perform the second decoding program according to the decoding initial value again obtained.
In an embodiment of the present invention, it is the centre being positioned at third reading power taking pressure that the first above-mentioned sign reads voltage, and the second sign reading voltage is positioned at the side that the first sign reads voltage.If the second decoding program utilizing the second sign to read performed by voltage does not have successfully decoded, memory management circuitry in order to set third reading power taking pressure wherein more another be the 3rd sign read voltage, and according to the 3rd sign read voltage and the 3rd verify that bit obtains decoding initial value again.Bug check and correcting circuit are in order to perform the second decoding program according to the decoding initial value again obtained.3rd sign reads voltage and is positioned at the opposite side that the first sign reads voltage.
In an embodiment of the present invention, the 3rd checking bit, also in order to read voltage for different signs, is inputed to different look-up tables again to obtain decoding initial value by above-mentioned memory management circuitry.
In an embodiment of the present invention, bug check and correcting circuit judge whether that the operation of successfully decoded comprises: bug check and correcting circuit produce multiple syndrome according to the first decoded bits and judge according to syndrome whether the first decoded bits forms effective code word.If the first decoded bits forms effective code word, bug check and correcting circuit judge successfully decoded.
Based on above-mentioned, the coding/decoding method that the embodiment of the present invention provides, memory storage apparatus and memorizer control circuit unit, again can obtain to read voltage or reset sign and read voltage, and then again decode.By this, the ability of righting the wrong can be promoted.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and shown in coordinating, accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is the error rate curves figure of low-density parity check code in prior art;
Fig. 2 is the schematic diagram of host computer system and the memory storage apparatus provided according to one embodiment of the invention;
Fig. 3 is the schematic diagram of computer, input/output device and the memory storage apparatus provided according to one embodiment of the invention;
Fig. 4 is the schematic diagram of host computer system and the memory storage apparatus provided according to another embodiment of the present invention;
Fig. 5 is the structural representation of the memory storage apparatus shown in Fig. 2;
Fig. 6 is the structural representation of the reproducible nonvolatile memorizer module provided according to one embodiment of the invention;
Fig. 7 is the schematic diagram of the memory cell array provided according to one embodiment of the invention;
Fig. 8 is the statistical figure of the grid voltage corresponding to the write data being stored in memory cell array provided according to one embodiment of the invention;
Fig. 9 is the schematic diagram of the sequencing storage unit provided according to one embodiment of the invention;
Figure 10 is the schematic diagram reading data from storage unit provided according to one embodiment of the invention;
Figure 11 is the schematic diagram reading data from storage unit provided according to another embodiment of the present invention;
Figure 12 is the schematic diagram of the management reproducible nonvolatile memorizer module provided according to the embodiment of the present invention;
Figure 13 is the structural representation of the memorizer control circuit unit provided according to one embodiment of the invention;
Figure 14 is the schematic diagram that the hard bit mode provided according to one embodiment of the invention is decoded;
Figure 15 A and Figure 15 B is the schematic diagram that the soft bit mode provided according to one embodiment of the invention is decoded;
Figure 16 is the process flow diagram that the execution hard bit mode decoding provided according to one embodiment of the invention is decoded with soft bit mode;
Figure 17 is the process flow diagram of the coding/decoding method provided according to one embodiment of the invention.
Description of reference numerals:
180,190: curve;
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212:U dish;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connecting interface unit;
104: memorizer control circuit unit;
106: reproducible nonvolatile memorizer module;
2202: memory cell array;
2204: character line control circuit
2206: bit line control circuit;
2208: row decoder;
2210: data input/output (i/o) buffer;
2212: control circuit;
702: storage unit;
704: bit line;
706: character line;
708: source electrode line;
712: select grid leak gated transistors;
714: select grid source transistor;
VA, VB, VC, VD, VE, VF, VG: read voltage;
400 (0) ~ 400 (N): entity erase unit;
202: memory management circuitry;
204: host interface;
206: memory interface;
208: bug check and correcting circuit;
210: memory buffer;
212: electric power management circuit;
1410,1420,1510,1520: distribution;
1430,1501 ~ 1506: region;
1440 ~ 1444, V1 ~ V5, V ' 1 ~ V ' 5: read voltage;
B1 ~ b5: checking bit;
S1601 ~ S1611, S1701 ~ S1706: step.
Embodiment
Generally speaking, memory storage apparatus (also claiming, storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.
Fig. 2 is the schematic diagram of host computer system and the memory storage apparatus provided according to one embodiment of the invention.Fig. 3 is the schematic diagram of computer, input/output device and the memory storage apparatus provided according to one embodiment of the invention.
Please refer to Fig. 2, host computer system 1000 generally comprises computer 1100, and (input/output is called for short: I/O) device 1106 with I/O.RAM) 1104, system bus 1108 and data transmission interface 1110 computer 1100 comprises microprocessor 1102, (randomaccess memory is called for short: random access memory.Input/output device 1106 comprises as the mouse 1202 of Fig. 3, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the device shown in Fig. 3 does not limit input/output device 1106, and input/output device 1106 also can comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the operation of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be that (Solid State Drive is called for short: SSD) the type nonvolatile memory storage of 1216 grades for USB flash disk 1212 as shown in Figure 3, storage card 1214 or solid state hard disc.
Fig. 4 is the schematic diagram of host computer system and the memory storage apparatus provided according to another embodiment of the present invention.
Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in embodiments of the present invention, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in an alternative embodiment of the invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its safety digit used (Secure Digital, be called for short: SD) block 1312, multimedia storage card (Multi Media Card, be called for short: mmc card) 1314, memory stick (memory stick, MS) 1316 be called for short:, (CompactFlash is called for short: CF) block 1318 or embedded memory storage 1320 (as shown in Figure 4) compact flash.Embedded memory storage 1320 comprises embedded multi-media card, and (Embedded MMC is called for short: eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 5 is the structural representation of the memory storage apparatus shown in Fig. 2.
Please refer to Fig. 5, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
In embodiments of the present invention, connecting interface unit 102 is compatible to Serial Advanced Technology Attachment (SerialAdvanced Technology Attachment, abbreviation: SATA) standard.But it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet parallel advanced technology annex (ParallelAdvanced Technology Attachment, abbreviation: PATA) standard, (Institute of Electrical and Electronic Engineers, is called for short: IEEE) 1394 standards Institute of Electrical and Electric Engineers, (Peripheral Component Interconnect Express, is called for short: PCIExpress) standard interconnection-interface, (Universal Serial Bus, is called for short: USB) standard USB (universal serial bus), SD interface standard, (Ultra High Speed-I, is called for short: UHS-I) interface standard a hypervelocity generation, in hypervelocity two generation, (Ultra High Speed-II, was called for short: UHS-II) interface standard, MS interface standard, MMC interface standard, eMMC interface standard, (Universal Flash Storage, is called for short: UFS) interface standard general flash memory, CF interface standard, (Integrated Device Electronics is called for short: IDE) standard or other standards be applicable to ide interface.Connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104, or connecting interface unit 102 is laid in one to comprise outside the chip of memorizer control circuit unit 104.
Memorizer control circuit unit 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as erasing.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 can be individual layer storage unit (Single Level Cell, be called for short: SLC) NAND flash memory module, multilayered memory unit (Multi Level Cell, be called for short: MLC) NAND flash memory module (namely, the flash memory module of 2 Bit datas can be stored) in a storage unit, three layers of storage unit (Trinary Level Cell, be called for short: TLC) NAND flash memory module (namely, the flash memory module of 3 Bit datas can be stored) in a storage unit, other flash memory module or other there is the memory module of identical characteristics.
Fig. 6 is the structural representation of the reproducible nonvolatile memorizer module provided according to one embodiment of the invention.Fig. 7 is the schematic diagram of the memory cell array provided according to one embodiment of the invention.
Please refer to Fig. 6, reproducible nonvolatile memorizer module 106 comprises memory cell array 2202, character line control circuit 2204, bit line control circuit 2206, row decoder (column decoder) 2208, data input/output (i/o) buffer 2210 and control circuit 2212.
Memory cell array 2202 comprises storing multiple storage unit 702 of data, multiple selection grid leak pole (select gate drain, be called for short: SGD) transistor 712 and multiple selection grid source electrode (select gatesource, be called for short: SGS) transistor 714 and connect many bit lines 704 of this little storage unit, many character lines 706, with common source line 708 (as shown in Figure 7).Storage unit 702 is configured in bit line 704 with on the point of crossing of character line 706 with array way (or three-dimensional stacking mode).When receiving write instruction or reading command from memorizer control circuit unit 104, control circuit 2212 meeting control character line control circuit 2204, bit line control circuit 2206, row decoder 2208, data input/output (i/o) buffer 2210 writes data and reads data to memory cell array 2202 or from memory cell array 2202, wherein character line control circuit 2204 is in order to control the voltage being imparted to character line 706, bit line control circuit 2206 is in order to control the voltage being imparted to bit line 704, row decoder 2208 according to the column address in instruction to select corresponding bit line, and data input/output (i/o) buffer 2210 is in order to temporal data.
Storage unit in reproducible nonvolatile memorizer module 106 is to store many bits (bits) with the change of critical voltage.Specifically, an electric charge capture layer is had between the control gate (control gate) of each storage unit and passage.By bestowing a write voltage to control gate, the amount of electrons of electric charge capture layer can be changed, thus change the critical voltage of storage unit.This change critical voltage program also referred to as " data are write to storage unit " or " sequencing storage unit ".Along with the change of critical voltage, each storage unit of memory cell array 2202 has multiple store status.And can judge storage unit belongs to which store status, obtains the bit that storage unit stores by this by reading voltage.
Fig. 8 is the statistical figure of the grid voltage corresponding to the write data being stored in memory cell array provided according to one embodiment of the invention.
Please refer to Fig. 8, for MLC NAND flash memory, along with different critical voltages, each storage unit has 4 kinds of store statuss, and this little store status represents the bit such as " 11 ", " 10 ", " 00 " and " 01 " respectively.In other words, each store status comprise minimum effective bit (LeastSignificant Bit, be called for short: LSB) and the highest significant bit (Most Significant Bit, be called for short: MSB).In embodiments of the present invention, the 1st bit counted from left side in store status (that is, " 11 ", " 10 ", " 00 " and " 01 ") is LSB, and the count from left side the 2nd bit is MSB.Therefore, in embodiments of the present invention, each storage unit can store 2 bits.It must be appreciated, the critical voltage shown in Fig. 8 and store status thereof to should be only an embodiment.In an alternative embodiment of the invention, critical voltage and store status corresponding may also be along with critical voltage is larger and arrange with " 00 " with " 11 ", " 10 ", " 01 ", or other arrange.In addition, in an alternative embodiment of the invention, the 1st bit that also definable is counted from left side is MSB, and the count from left side the 2nd bit is LSB.
Fig. 9 is the schematic diagram of the sequencing storage unit provided according to one embodiment of the invention.
Please refer to Fig. 9, in embodiments of the present invention, the sequencing of storage unit writes/verify critical voltage method by pulse to have come.Specifically, during for data are write to storage unit, memorizer control circuit unit 104 can set initial write voltage and write pulse time, and indicate the control circuit 2212 of reproducible nonvolatile memorizer module 106 to use set initial write voltage and write pulse time sequencing storage unit, to carry out the write of data.Afterwards, memorizer control circuit unit 104 can apply verifying voltage to control gate to judge storage unit whether conducting, and then judges whether storage unit has been in correct store status (having correct critical voltage).If when storage unit is not programmed into correct store status, memorizer control circuit unit 104 indicates control circuit 2212 to add that (Incremental-step-pulseprogramming is called for short: ISPP) adjusted value carrys out sequencing storage unit as new write voltage again according to new write voltage and write pulse time an incremental step pulse program with the write voltage bestowed at present.Otherwise, if when storage unit has been programmed into correct store status, then represented that data have been correctly written to storage unit.Such as, initial write voltage can be set to 16 volts, and (Voltage, is called for short: V), the write pulse time can be set to 18 microsecond (microseconds, μ s) and incremental step pulse program adjusted value is set to 0.6V be called for short:, but the present invention is not limited thereto.
Figure 10 is the schematic diagram reading data from storage unit provided according to one embodiment of the invention, and it is for MLC NAND flash memory.
Please refer to Figure 10, the read operation of the storage unit of memory cell array 2202 reads voltage in control gate by bestowing, and by the conducting state of storage unit, carrys out the data that recognition memory cell stores.Checking bit (VA) be in order to instruction bestow read voltage VA time storage unit whether be conducting; Checking bit (VC) be in order to instruction bestow read voltage VC time storage unit whether be conducting; Checking bit (VB) be in order to instruction bestow read voltage VB time storage unit whether be conducting.At this hypothesis verification bit be " 1 " time represent corresponding memory cell conducts, and verify that bit is " 0 " time represent that corresponding storage unit does not have conducting.In the operation of reading cells, character line control circuit 2204 meeting first applying reading voltage VA is in control gate and whether conducting decides LSB with the equation (1) of correspondence according to storage unit.
LSB=(VA)Lower_pre1 (1)
Wherein (VA) Lower_pre1 represents checking bit (VA).
Such as, when reading voltage VA and being less than the critical voltage of storage unit, storage unit can not conducting and verify that bit (VA) is for ' 0 '.When reading voltage VA and being greater than the grid voltage of storage unit, storage unit is understood conducting and is verified that bit (VA) is for ' 1 '.
Then, character line control circuit 2204 can respectively by reading voltage VB with read voltage VC bestow control gate and foundation storage unit conducting and corresponding equation (2) decide MSB.
MSB=((VB)Upper_pre2)xor(～(VC)Upper_pre1)(2)
Wherein (VC) Upper_pre1 represent checking bit (VC), and (VB) Upper_pre2 represent checking bit (VB), wherein symbol " ~ " represent anti-phase.
Therefore, according to equation (2), when reading voltage VC is all less than the critical voltage of storage unit with reading voltage VB, checking bit (VC) is " 0 " and verify that bit (VB) is " 0 ", now MSB can be identified as " 1 ".When reading voltage VC is greater than the critical voltage of storage unit and reading voltage VB is less than the critical voltage of storage unit, checking bit (VC) is " 1 ", and verify that bit (VB) is " 0 ", now MSB can be identified as " 0 ".When reading voltage VC and being all greater than the critical voltage of storage unit with reading voltage VB, checking bit (VC) with checking bit (VB) is " 1 ", now MSB can be identified as " and 1 ".
It must be appreciated, although the present invention explains with MLC NAND flash memory.But the present invention is not limited thereto, other multilayered memory unit NAND flash memories also can carry out the reading of data according to above-mentioned principle.In addition, can calculate MSB and LSB with being different from the formula of equation (1) with (2) in an alternative embodiment of the invention, the present invention does not limit how to calculate MSB and LSB yet.
Figure 11 is the schematic diagram reading data from storage unit provided according to another embodiment of the present invention.
Please refer to Figure 11, for TLC NAND flash memory, each store status comprise left side count the 1st bit minimum effective bit LSB, count from left side the 2nd bit middle significant bit (Center Significant Bit, abbreviation: the highest significant bit MSB of the 3rd bit CSB) and from left side counted.In the present embodiment, according to different critical voltages, storage unit has 8 kinds of store statuss (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ").By applying to read voltage VA ~ VG in control gate, can the bit that stores of recognition memory cell.
Figure 12 is the schematic diagram of the management reproducible nonvolatile memorizer module provided according to the embodiment of the present invention.
Please refer to Figure 12, the storage unit 702 of reproducible nonvolatile memorizer module 106 can form multiple entity program unit, and this little entity program unit can form multiple entity erase unit 400 (0) ~ 400 (N).Specifically, the storage unit on same character line can form one or more entity program unit.If each storage unit can store the bit of more than 2, then the entity program unit on same character line can be classified as lower entity program unit and upper entity program unit.Such as, the LSB of each storage unit belongs to lower entity program unit, and the MSB of each storage unit belongs to entity program unit.In general, the writing speed of lower entity program unit can be greater than the writing speed of entity program unit.In this embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Such as, entity program unit is physical page or entity fan (sector).If entity program unit is physical page, then each entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, error correcting code) of storage system.In embodiments of the present invention, each data bit district comprises 32 entity fans, and the size of an entity fan is that (byte is called for short: B) 512 bytes.But, in other embodiments of the present invention, also can comprise in data bit district 8,16 or number more or less entity fan, the present invention do not limit entity fan size and number.On the other hand, entity erase unit is the least unit of erasing.Also namely, each entity erase unit contains the storage unit be wiped free of in the lump of minimal amount.Such as, entity erase unit is physical blocks.
Figure 13 is the structural representation of the memorizer control circuit unit provided according to one embodiment of the invention.It must be appreciated, the structure of the memorizer control circuit unit shown in Figure 13 is only an embodiment, and the present invention is not as limit.
Please refer to Figure 13, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204, memory interface 206 and bug check and correcting circuit 208.
Memory management circuitry 202 is in order to the overall operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the running such as erasing.When the operation of memory management circuitry 202 is below described, be equal to the operation that memorizer control circuit unit 104 is described, below and repeat no more.
In embodiments of the present invention, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as erasing.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has driving code, and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the operation such as erasing.
In addition, in an alternative embodiment of the invention, the steering order of memory management circuitry 202 also a hardware pattern can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Storage Unit Management circuit, storer write circuit, memory reading circuitry, memory erase circuit and data processing circuit.Storage Unit Management circuit, storer write circuit, memory reading circuitry, memory erase circuit and data processing circuit are electrically connected to microcontroller.Wherein, Storage Unit Management circuit is in order to manage the physical blocks of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory erase circuit is in order to assign erasing instruction data to be wiped from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In embodiments of the present invention, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.
Bug check and correcting circuit 208 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 208 can be that the corresponding data that this writes instruction produce corresponding error correcting code (error correcting code, ECCcode) or bug check code (error detecting code be called for short:, be called for short: EDC), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding error correcting code or bug check code by memory management circuitry 202.Afterwards, can read error correcting code corresponding to these data or bug check code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 208 can according to this error correcting code or bug check code to read data execution error inspection and correction programs simultaneously.
In an embodiment of the present invention, memorizer control circuit unit 104 also comprises memory buffer 210 and electric power management circuit 212.Memory buffer 210 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.Electric power management circuit 212 is electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.
Figure 14 is the schematic diagram that the hard bit mode provided according to one embodiment of the invention is decoded.
Please refer to Figure 14, at this for SLC flash memory, distribution 1,410 1420 is used to the store status representing multiple first storage unit with distribution, and distributes and 1,410 1420 represent different store statuss respectively from distributing.These first storage unit can belong to same entity program unit or different entity program unit, and the present invention is also not subject to the limits.When this hypothesis belongs to distribution 1410 when a storage unit, what this storage unit stored is bit " 1 "; When storage unit belongs to distribution 1420, this cell stores be bit " 0 ".When memory management circuitry 202 carrys out reading cells to read voltage 1440, memory management circuitry 202 can obtain checking bit, and whether it is used to indicate this storage unit to be conducting.When this hypothesis memory cell conducts, checking bit is " 1 ", otherwise is then " 0 ", but the present invention not subject to the limits.If this checking bit is " 1 ", then memory management circuitry 202 can judge that this storage unit belongs to distribution 1410, otherwise is then distribution 1420.But distribution 1410 is overlapping with distribution 1420 in region 1430.That is, there are several storage unit should be belong to distribution 1410 but be recognized as distribution 1420, and have several storage unit should be belong to distribution 1420 but be recognized as distribution 1410.
In this embodiment of the present invention, when these first storage unit will be read, memory management circuitry 202 first can read voltage (such as, reading voltage 1441) according to first and read these first storage unit to obtain the checking bit (also claiming the first checking bit) of the first storage unit.
Bug check and correcting circuit 208 can verify bit to perform according to these decoding program (also referred to as the first decoding program) comprising a probability decoding algorithm, to produce multiple decoded bits (also referred to as the first decoded bits).In embodiments of the present invention, probability decoding algorithm is as a candidate (candidate) decoded result possible for symbol (symbol), and the numerical value of the information inputted in decode procedure or intermediate operations process represents with the ratio of probability between the probit value of these candidates or candidate, and then determine which most possible candidate is.For example, if a symbol has two candidates (bit 0and1), probability decoding algorithm is that the probability occurred according to 0 or 1 separately goes to calculate most possible candidate, or goes to calculate most possible candidate with the ratio of probability between 0 and 1.If be N number of candidate, such as under finite field (Finite Field), possible numerical value is that (N is positive integer to 0 ~ N-1, each candidate represents multiple bit), then probability decoding algorithm is that the probability calculating N number of candidate separately decides most possible candidate, or goes the relative probability ratio of calculating to decide most possible candidate using the probability of one of them numerical value as denominator.In an embodiment of the present invention, the ratio of above-mentioned probability also can represent by the form of logarithm.
In embodiments of the present invention, probability decoding algorithm can be convolution code (convolutional code), turbine code (turbo code), low-density parity check code (low-density parity-check code) or other there is the algorithm of probability decode features.For example, in convolution code and turbine code, encoding and decoding can be carried out with finite state machine (finite state machine), and most possible multiple states can be calculated according to checking bit in embodiments of the present invention, and then produce decoded bits.Below will be described for low-density parity check code.
If use low-density parity check code, when performing the first decoding program according to checking bit, according to each, memory management circuitry 202 also can verify that bit obtains the decoding initial value (also claiming the first decoding initial value) of each storage unit.Such as, if checking bit is " 1 ", the decoding initial value that memory management circuitry 202 can set corresponding storage unit is-n; If checking bit is " 0 ", then initial value of decoding is n.Wherein n is positive number, but the value that the present invention does not limit positive integer n is how many.
Next, bug check and correcting circuit 208 can perform low-density parity according to these initial values of decoding and check that the iterative decoding of algorithm is to produce multiple first decoded bits.In iterative decoding, these decoding initial values can constantly be updated to represent a probit value, and this probit value is also referred to as fiduciary level (realiability) or confidence degree (belief).The decoding initial value be updated can be converted into multiple decoded bits, bug check and correcting circuit 208 can be used as these decoded bits as a vector, and this vector is checked that the parity check matrix (parity-check matrix) of algorithm does the matrix multiple of mould 2 (module2), to obtain multiple syndrome (syndrome) with low-density parity.These syndromes can be used for judging whether the code word that decoded bits forms is effective code word.If the code word that decoded bits forms is effective code word, then iterative decoding can stop, and bug check and correcting circuit 208 can export these decoded bits to become the first decoded bits.If decoded bits forms invalid code word, then can continue more new decoding initial value and produce new decoded bits to carry out next iteration.When iterations arrives default iterations, iterative decoding also can stop, and the decoded bits that wherein last iteration produces is called as the first decoded bits.Bug check and correcting circuit 208 can utilize these first decoded bits to judge whether successfully decoded.Such as, if judge that the first decoded bits forms effective code word according to syndrome, be then successfully decoded; If the first decoded bits forms invalid code word, then represent and decode unsuccessfully.
Probability decoding algorithm in an alternative embodiment of the invention included by decoding program is convolution code and turbine code, and also can comprise other error-correcting code in decoding program.Such as, convolution code and turbine code can arrange in pairs or groups any particular algorithms parity code together with use.After in decoding program, the decoded portion of convolution code or turbine code is finished, parity code can be used for judging that whether the decoded bits produced is effective code word, and then judge whether successfully decoded.
No matter use which kind of error-correcting code, if decode unsuccessfully, represent that these first cell stores have the error bit that can not correct.If decode unsuccessfully, memory management circuitry 202 can obtain reading voltage again, and (also claim second to read voltage with the reading voltage again obtained, such as read voltage 1442) read these the first storage unit, again to obtain the checking bit (also claiming the second checking bit) of storage unit.Memory management circuitry 202 can perform the first above-mentioned decoding program, to obtain the second decoded bits according to the checking bit again obtained.
In an embodiment of the present invention, bug check and correcting circuit 208 can utilize the second decoded bits to judge whether successfully decoded (that is, whether the second decoded bits forms effective code word).If utilize the second decoded bits to judge to decode unsuccessfully, memory management circuitry 202 can judge whether the number of times again obtaining the second reading voltage has exceeded a preset times.If the number of times again obtaining the second reading voltage has exceeded preset times, then memory management circuitry 202 can stop again obtaining the second reading voltage.If the number of times again obtaining the second reading voltage has not exceeded preset times, then memory management circuitry 202 again can obtain second and obtain voltage (such as, read voltage 1443), and read voltage 1443 according to again obtain second and read the first storage unit, again to obtain the second checking bit.Memory management circuitry 202 also can perform the first decoding program according to the second checking bit again obtained.
In other words, when there being the error bit that can not correct, by again obtaining reading voltage, the checking bit of some storage unit can be changed, and then changes several probit values in probability decoding algorithm, and then has an opportunity to change the decoded result of decoding program.In logic, the above-mentioned action again obtaining reading voltage to overturn the some bits in (flip) code word, and again decode to new code word.In some cases, the code word (having the error bit that can not correct) cannot decoded before upset, likely can decode after upset.Further, the trial solution of memory management circuitry 202 meeting in an embodiment of the present invention yardage time, until the number of times attempted exceedes preset times.But it is how many that the present invention does not limit preset times.
In fig. 14, reading voltage 1440 is a default reading voltage, and it represents can be minimum at reading voltage 1440 times error bits.Memory management circuitry 202 can obtain to preset by various algorithm and read voltage 1440.Such as, memory management circuitry 202 first can write known bit to these the first storage unit, scan the error bit number of these first storage unit under various critical voltage again and read voltage to obtain to preset, the present invention does not limit how to calculate to preset and reads voltage.In this inventive embodiments, memory management circuitry 202 is when again obtaining reading voltage, and new reading voltage and old reading voltage can in the both sides of default reading voltage 1440.For example, memory management circuitry 202 first can use and read voltage 1441, then adjust to preset according to an off-set value (just can be or bearing) and read voltage 1440 to obtain reading voltage 1442, wherein default reading voltage 1440 is between reading voltage 1441 and reads between voltage 1442.In an embodiment of the present invention, this off-set value calculated according to reading voltage 1441 and presetting the difference read between voltage 1440.Such as, reading voltage 1441 and the default difference read between voltage 1440 can be multiplied by a multiplier to obtain off-set value by memory management circuitry 202, and default reading voltage 1440 is deducted off-set value and read voltage 1442 to obtain, it can be written as following equation (3).
R i+1=K-Q(R i-K)…(3)
Wherein Ri+1 represents the reading voltage used when (i+1) secondary trial, and i is positive integer.Q is a real number, represents above-mentioned multiplier.K reads voltage for presetting.
In other embodiments of the present invention, old reading voltage and new reading voltage also can in the same sides of default reading voltage 1440.Or the reading voltage that memory management circuitry 202 first time uses can be preset to read voltage 1440, then just sequentially use and read voltage 1441 ~ 1444.The present invention does not limit old reading voltage and the value newly reading voltage.
It should be noted that lifted in fig. 14 is the example of SLC flash memory, but again obtain the step reading voltage and also go for MLC or TLC flash memory.As shown in Figure 10, change and read the LSB that voltage VA can overturn a storage unit, change and read the MSB that voltage VB or VC then can overturn a storage unit.Therefore, change reading voltage VA, VB or VC and a code word can be changed into another code word.The result changing code word is also applicable to the TLC flash memory of Figure 11.The present invention does not limit used SLC, MLC or TLC flash memory.
In the embodiment shown in fig. 14, the decoding initial value of storage unit is divided into two numerical value (such as, n and-n) according to a checking bit.The iterative decoding performed according to two kinds of numerical value is also referred to as the iterative decoding of hard bit mode (hard bit mode).But the step of above-mentioned change reading voltage also can be applied in the iterative decoding of soft bit mode (soft bit mode), and wherein the decoding initial value of each storage unit determined according to multiple checking bit.No matter it should be noted that it is hard bit mode or soft bit mode, in iterative decoding, all can calculate the probit value of bit, therefore all belong to probability decoding algorithm.
Figure 15 A and Figure 15 B is the schematic diagram that the soft bit mode provided according to one embodiment of the invention is decoded.
As mentioned above, when applying reads voltage after the control gate of storage unit, along with storage unit whether conducting, the checking bit acquired by memory management circuitry 202 can be " 0 " or " 1 ".If when this hypothesis storage unit does not have conducting, corresponding checking bit is " 0 ", otherwise be then " 1 ".In Figure 15 A, memory management circuitry 202 can apply to read voltage V1 ~ V5 (also claiming first to read voltage) to storage unit to obtain 5 checking bits (also claiming the first checking bit).Specifically, read voltage V1 and correspond to checking bit b1; Read voltage V2 and correspond to checking bit b2; Read voltage V3 and correspond to checking bit b3; Read voltage V4 and correspond to checking bit b4; Read voltage V5 and correspond to checking bit b5.If the critical voltage of a storage unit is interval 1501, then from checking bit b1 to checking bit b5, the checking bit acquired by memory management circuitry 202 can be " 11111 "; If the critical voltage of storage unit is interval 1502, then verify that bit can be " 00111 "; If the critical voltage of storage unit is interval 1503, then verify that bit can be " 00011 "; If the critical voltage of storage unit is interval 1504, then verify that bit can be " 00001 "; If the critical voltage of storage unit is interval 1505, then verify that bit can be " 00000 ".
In this inventive embodiments, one of them reading voltage V1 ~ V5 can be set to sign (sign) and read voltage.This sign reads the sign that voltage is used to determine decoding initial value.Such as, if reading voltage V3 is that sign reads voltage, then interval 1501 ~ interval decoding initial value corresponding to 1503 can be less than 0, and interval decoding initial value corresponding to 1504 ~ 1 intervals 506 can be greater than 0.In addition, in each interval, can calculated in advance go out storage unit belong to the probability of distribution 1510 with belong to the probability of distribution 1520.(Log LikelihoodRatio, is called for short: LLR), and this log likelihood ratio can be used to the size of the absolute value determining decoding initial value can to calculate log likelihood ratio according to these two probability.Therefore, memory management circuitry 202 reads voltage and checking bit b1 ~ checking bit b5 according to sign to obtain the decoding initial value of storage unit under soft bit mode (also claim first decode initial value).In an embodiment of the present invention, the decoding initial value corresponding to each interval can be calculated in advance and be stored in a look-up table.Checking bit b1 ~ checking bit b5 can input in this look-up table by memory management circuitry 202, obtains corresponding decoding initial value by this.In other words, in implementation, memory management circuitry 202 also according to checking bit b1 ~ checking bit b5, and can not read voltage with reference to sign, just obtains the decoding initial value of storage unit under soft bit mode.In addition, if set different signs to read voltage, memory management circuitry 202 can use different look-up tables.
After memory management circuitry 202 obtains decoding initial value, bug check and correcting circuit 208 can perform iterative decoding to obtain multiple decoded bits (also claiming the first decoded bits) to initial value of decoding, and utilize these decoded bits to judge whether successfully decoded.If decode unsuccessfully, memory management circuitry 202 again can obtain and read voltage (also claiming second to read voltage).Such as, memory management circuitry 202 can obtain 5 off-set values according to reading voltage V1 ~ V5 and the default difference read between voltage V3, and will adjust to preset according to these 5 off-set values and read voltage V3 (such as, deducting this 5 off-set values) to obtain new reading voltage.In other words, aforesaid equation (3) also may be used in the middle of soft bit mode.Such as, as shown in fig. 15b, reading voltage V ' 1 ~ reading voltage V ' 5 is the reading voltage after changing.In this inventive embodiments, before changing with change after, the distribution of sign of decoding initial value is all symmetrical, and the reading voltage V3 namely in Figure 15 A and the reading voltage V ' 3 in Figure 15 B reads voltage for sign.With another angle, in Figure 15 A and Figure 15 B, the number being less than the reading voltage of sign reading voltage is same as to be greater than the number that sign reads the reading voltage of voltage.In the embodiment shown in Figure 15 B, read the voltage V ' 1 ~ spacing read between voltage V ' 5 not change, but, memory management circuitry 202 also at random can change reading voltage V1 ~ V5 to obtain new reading voltage, and the amplitude that each reading voltage V1 ~ reading voltage V5 changes can be the same or different.In addition, in Figure 15 B, preset and read voltage V3 and drop on to read voltage V ' 2 ~ read between voltage V ' 3, but preset and read voltage V3 and also can drop on any two new reading voltage V ' 1 ~ read in the middle of voltage V ' 5, the present invention is also not subject to the limits.
After again obtaining reading voltage, the log likelihood ratio corresponding to each interval also can change, and therefore memory management circuitry 202 can use different look-up tables to obtain decoding initial value.In logic, changing reading voltage is to overturn several bits in a code word, and give different decoding initial values (changing numerical values recited or sign), make the code word (having the error bit that can not correct) cannot decoded before changing, likely can decode after the change.
Please refer to Figure 15 A, in an alternative embodiment of the invention, memory management circuitry 202 can reset sign and read voltage to change a code word.For example, if reading voltage V3 is that sign reads voltage, then interval decoding initial value corresponding to 1504 can be greater than 0; If but reading voltage V4 or V5 is that sign reads voltage, then interval decoding initial value corresponding to 1504 can be less than 0.Therefore, if the decoding program utilizing sign originally to read performed by voltage does not have successfully decoded, then memory management circuitry 202 can set another reading voltage is that sign reads voltage (also claiming the second sign to read voltage), and again obtains decoding initial value according to the sign reading voltage reset with the checking bit of script.Read after voltage resetting sign, it is asymmetric that the distribution of the sign of decoding initial value may become.For example, reading voltage V4 is that new sign reads voltage, and the number being less than the reading voltage reading voltage V4 is different from the number being greater than the reading voltage reading voltage V4, namely there is the decoding initial value corresponding to four intervals to be less than 0, but have the decoding initial value only corresponding to an interval to be greater than 0.In an embodiment of the present invention, memory management circuitry 202 first sets the reading voltage V3-being positioned at centre in reading voltage V1 ~ reading voltage V5 to read voltage as sign, then sequentially setting is read voltage V2-, V4, V1, V5 and is read voltage as sign, until successfully decoded.Wherein reading voltage V1 and V2-(also claiming the second sign to read voltage) is in the side of reading voltage V3, and to read voltage V3 and V4 (also claiming the 3rd sign reading voltage) be opposite side at reading voltage V3.
It should be noted that after the sign that setting is new reads voltage, read voltage V1 ~ reading voltage V5 and do not change, therefore memory management circuitry 202 does not need again to read the first storage unit yet.In other words originally obtain 5 checking bits can't change, sign reads the sign that voltage is used to change decoding initial value.In an embodiment of the present invention, read voltage for different signs, script 5 checking bits can be inputed to different look-up tables, again to obtain decoding initial value by memory management circuitry 202.Next, bug check and correcting circuit 208 just can carry out iterative decoding according to the decoding initial value again obtained.
In the embodiment shown in Figure 15 A and Figure 15 B, the decoding initial value of a soft bit mode decoding determined by 5 checkings bit (reading voltage).But in other embodiments of the present invention, the decoding initial value of a soft bit mode decoding also can be decided by the checking bit that number is more or less, and the present invention is also not subject to the limits.
Figure 16 is the process flow diagram that the execution hard bit mode decoding provided according to one embodiment of the invention is decoded with soft bit mode.
Please refer to Figure 16, in the embodiment shown in Figure 16, memory management circuitry 202 is the iterative decodings first carrying out hard bit mode.If the not success of hard bit mode, then carry out the iterative decoding of soft bit mode.Specifically, in step S1601, memory management circuitry 202 can read voltage (also claiming first to read voltage) according to one and read multiple storage unit (also claiming the first storage unit) to obtain checking bit (also claiming the first checking bit), and performs the first decoding program (it comprises the iterative decoding producing decoding initial value and hard bit mode) accordingly.In step S1602, bug check and correcting circuit 208 can utilize produced decoded bits to judge whether successfully decoded.If successfully decoded, memory management circuitry 202 can export decoded bits.If decoding is success not, in step S1603, memory management circuitry 202 can obtain another reading voltage again (becomes the second reading voltage, it is different from the first reading voltage) and read the first storage unit again to obtain checking bit (also claiming the second checking bit) according to the reading voltage again obtained, and perform the first decoding program accordingly.In step S1604, bug check and correcting circuit 208 can utilize the decoded bits produced at present to judge whether successfully decoded.Unsuccessful if decode, in step S1605, memory management circuitry 202 can judge whether the number of times again obtaining the second reading voltage exceedes preset times.If the number of times again obtaining the second reading voltage does not exceed preset times, get back to step S1603.
If the number of times again obtaining the second reading voltage has exceeded preset times, in step S1606, memory management circuitry 202 can read the first storage unit to obtain checking bit (also claiming the 3rd checking bit) according to multiple reading voltage (also claiming third reading power taking pressure), obtain decoding initial value, and perform the second decoding program (it comprises the iterative decoding of soft bit mode) according to decoding initial value.In step S1607, bug check and correcting circuit 208 can utilize the decoded bits produced at present to judge whether successfully decoded.Unsuccessful if decode, in step S1608, memory management circuitry 202 can obtain reading voltage again, or resets sign reading voltage; Again obtain decoding initial value, and re-execute the second decoding program.In step S1609, bug check and correcting circuit 208 can judge whether successfully decoded.If successfully decoded in step S1609, then can export the decoded bits (also claiming the 3rd decoded bits) produced at present.If do not have successfully decoded in step S1609, in step S1610, memory management circuitry 202 can judge whether the number of times of again decoding exceedes preset times.If the number of times of again decoding does not exceed preset times, get back to step S1608.If the number of times of again decoding exceedes preset times, then represent and decode unsuccessfully (step S1611).
It should be noted that the number of the reading voltage used in step S1601 and step S1603 is all 1, and step S1601 be identical the first decoding program (comprising the iterative decoding of hard bit mode) performed by step S1603.In addition, the number of the reading voltage that step S1606 and step S1608 use is identical (and being greater than 1), and step S1606 be identical the second decoding program (comprising the iterative decoding of soft bit mode) performed by step S1608.
Figure 17 is the process flow diagram of the coding/decoding method provided according to one embodiment of the invention.
Please refer to Figure 17, in step S1701, read voltage according at least one first and read multiple first storage unit, to obtain at least one first checking bit of each the first storage unit.In step S1702, according to first checking bit perform comprise a probability decoding algorithm a decoding program to produce multiple first decoded bits.In step S1703, the first decoded bits is utilized to judge whether successfully decoded.
If successfully decoded, in step S1704, export the first decoded bits.
If decode unsuccessfully, in step S1705, read voltage according at least one second and read the first storage unit to obtain at least one second checking bit of each the first storage unit.In step S1706, perform the first decoding program to produce multiple second decoded bits according to the second checking bit.
It should be noted that in step S1701 first read voltage be different from step S1705 second read voltage.But the first number reading voltage is the number being same as the second reading voltage.If the number that the first reading voltage and second reads voltage is 1, then the first decoding program in step S1702 and step S1706 just comprises the iterative decoding of hard bit mode.If the first reading voltage and the second number reading voltage are greater than 1, then the first decoding program just comprises the iterative decoding of soft bit mode.In Figure 17, each step has described in detail as above, just repeats no more at this.It should be noted that in Figure 17, each step can implementation be multiple procedure code or circuit.In addition, the method for Figure 17 above embodiment of the present invention of can arranging in pairs or groups uses, and also can be used alone, the present invention is also not subject to the limits.
In sum, the coding/decoding method that the embodiment of the present invention provides, memory storage apparatus and memorizer control circuit unit are when code word has the error bit that can not correct, and attempt some bits in upset code word or change decoding initial value.Thus, the code word that cannot decode likely can be decoded after the change, can increase the ability of decoding by this under the condition of same code rate.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (30)

1. a coding/decoding method, is characterized in that, for a reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module comprises multiple storage unit, and this coding/decoding method comprises:
Multiple first storage unit in those storage unit are read, to obtain at least one first checking bit of each those the first storage unit according at least one first reading voltage;
According at least one first checking bit of this of those the first storage unit perform comprise a probability decoding algorithm one first decoding program to produce multiple first decoded bits, and utilize those first decoded bits to judge whether successfully decoded; And
If decode unsuccessfully, read voltage according at least one second and read those first storage unit to obtain at least one second checking bit of each those the first storage unit, this at least one second checking bit according to those the first storage unit performs this first decoding program to produce multiple second decoded bits
Wherein this at least one second reading voltage is different from this at least one first reading voltage, and this at least one second number reading voltage is same as the number of this at least one first reading voltage.
2. coding/decoding method according to claim 1, is characterized in that, also comprises:
According to this at least one first read voltage one of them and one preset the difference read between voltage obtain an off-set value; And
Utilize this off-set value to adjust this and preset reading voltage to obtain this at least one second reading voltage.
3. coding/decoding method according to claim 2, is characterized in that, at least one first to read number of voltage be 1 for this, and this is preset, and to read voltage be first read voltage and this second reads between voltage between this.
4. coding/decoding method according to claim 2, is characterized in that, the step obtaining this off-set value comprises:
By this at least one first read voltage this one of them and this preset the difference read between voltage and be multiplied by a multiplier to obtain this off-set value.
5. coding/decoding method according to claim 1, is characterized in that, also comprises:
Those second decoded bits are utilized to judge whether successfully decoded;
If utilize those second decoded bits to judge to decode unsuccessfully, judge that whether the number of times again obtaining this at least one second reading voltage is more than a preset times;
If again obtain this at least one second this number of times reading voltage not exceed this preset times, again this at least one second reading voltage is obtained, read those first storage unit again to obtain those the second checking bits according to this at least one second reading voltage again obtained, those the second checking bits according to again obtaining perform this first decoding program; And
If again obtain this at least one second this number of times reading voltage to exceed this preset times, stop again obtaining this at least one second reading voltage.
6. coding/decoding method according to claim 5, is characterized in that, number and this at least one second number reading voltage of this at least one first reading voltage are 1, and this coding/decoding method also comprises:
If again obtain this second this number of times reading voltage to exceed this preset times, read those first storage unit according to multiple third reading power taking pressure, to obtain multiple 3rd checking bits of each those the first storage unit;
One of them setting those third reading power taking pressures is that one first sign reads voltage;
Those reading voltage and each those the first storage unit according to this first sign the 3rd verify that bit obtains one of each those the first storage unit and to decode initial value;
One second decoding program is performed to obtain multiple 3rd decoded bits to those decoding initial values;
Those the 3rd decoded bits are utilized to judge whether successfully decoded; And
If utilize those the 3rd decoded bits to judge to decode unsuccessfully, wherein another setting those third reading power taking pressures is that one second sign reads voltage, read voltage according to this second sign and the 3rd verify that bit obtains those initial values of decoding again with those, and perform this second decoding program according to those again obtaining initial values of decoding.
7. coding/decoding method according to claim 6, it is characterized in that, it is the centre being positioned at those third reading power taking pressures that this first sign reads voltage, and it is be positioned at the side that this first sign reads voltage that this second sign reads voltage, and this coding/decoding method also comprises:
If this second decoding program utilizing this second sign to read performed by voltage does not have successfully decoded, set those third reading power taking pressures wherein more another be one the 3rd sign read voltage, voltage is read and those the 3rd verify that bit obtains those initial values of decoding again according to the 3rd sign, and those decoding initial values according to again obtaining perform this second decoding program
Wherein the 3rd sign reads the opposite side that voltage is positioned at this first sign reading voltage.
8. coding/decoding method according to claim 6, is characterized in that, also comprises:
Voltage is read for this different signs, those the 3rd checking bits are inputed to different look-up tables, again to obtain those decoding initial values.
9. coding/decoding method according to claim 1, is characterized in that, this probability decoding algorithm is low-density parity check code.
10. coding/decoding method according to claim 1, is characterized in that, utilizes those first decoded bits to judge whether that the step of successfully decoded comprises:
Multiple syndrome is produced according to those first decoded bits;
Judge whether those first decoded bits form effective code word according to those syndromes; And
If those first decoded bits form effective code word, judge successfully decoded.
11. 1 kinds of memory storage apparatus, is characterized in that, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, comprises multiple storage unit; And
One memorizer control circuit unit, be electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, in order to read multiple first storage unit in those storage unit according at least one first reading voltage, to obtain at least one first checking bit of each those the first storage unit
Wherein, this memorizer control circuit unit in order to perform according at least one first checking bit of this of those the first storage unit comprise a probability decoding algorithm one first decoding program to produce multiple first decoded bits, and utilize those first decoded bits to judge whether successfully decoded
If decode unsuccessfully, this memorizer control circuit unit reads those first storage unit to obtain at least one second checking bit of each those the first storage unit in order to read voltage according at least one second, and this at least one second checking bit according to those the first storage unit performs this first decoding program to produce multiple second decoded bits
Wherein this at least one second reading voltage is different from this at least one first reading voltage, and this at least one second number reading voltage is same as the number of this at least one first reading voltage.
12. memory storage apparatus according to claim 11, it is characterized in that, this memorizer control circuit unit also in order to according to this at least one first read voltage one of them and one preset the difference read between voltage obtain an off-set value, and utilize this off-set value adjust this preset read voltage with obtain this at least one second reading voltage.
13. memory storage apparatus according to claim 12, is characterized in that, at least one first to read number of voltage be 1 for this, and this is preset, and to read voltage be first read voltage and this second reads between voltage between this.
14. memory storage apparatus according to claim 12, is characterized in that, the operation that this memorizer control circuit unit obtains this off-set value comprises:
This memorizer control circuit unit by this at least one first read voltage this one of them and this preset the difference read between voltage and be multiplied by a multiplier to obtain this off-set value.
15. memory storage apparatus according to claim 11, is characterized in that, this memorizer control circuit unit also in order to utilize those second decoded bits to judge whether successfully decoded,
If utilize those second decoded bits to judge to decode unsuccessfully, whether this memorizer control circuit unit obtains the number of times of this at least one second reading voltage more than a preset times again in order to judgement,
If again obtain this at least one second this number of times reading voltage not exceed this preset times, this memorizer control circuit unit is in order to again to obtain this at least one second reading voltage, those first storage unit are read again to obtain those the second checking bits according to this at least one second reading voltage again obtained, and those the second checking bits according to again obtaining perform this first decoding program
If again obtain this at least one second this number of times reading voltage to exceed this preset times, this memorizer control circuit unit is in order to stop again obtaining this at least one second reading voltage.
16. memory storage apparatus according to claim 15, is characterized in that, number and this at least one second number reading voltage of this at least one first reading voltage are 1,
If again obtain this second this number of times reading voltage to exceed this preset times, this memorizer control circuit unit, in order to read those first storage unit according to multiple third reading power taking pressure, verifies bits with the obtain each those the first storage unit the multiple 3rd,
Wherein, this memorizer control circuit unit is also that one first sign reads voltage in order to one of them setting those third reading power taking pressures, and those reading voltage and each those the first storage unit according to this first sign the 3rd verify that bit obtains one of each those the first storage unit and to decode initial value
Wherein, this memorizer control circuit unit also in order to perform one second decoding program to obtain multiple 3rd decoded bits to those decoding initial values, and utilizes those the 3rd decoded bits to judge whether successfully decoded,
If utilize those the 3rd decoded bits to judge to decode unsuccessfully, this memorizer control circuit unit is that one second sign reads voltage in order to set wherein another of those third reading power taking pressures, read voltage according to this second sign and the 3rd verify that bit obtains those initial values of decoding again with those, and perform this second decoding program according to those again obtaining initial values of decoding.
17. memory storage apparatus according to claim 16, is characterized in that, it is the centre being positioned at those third reading power taking pressures that this first sign reads voltage, and this second sign reading voltage is positioned at the side that this first sign reads voltage,
If this second decoding program utilizing this second sign to read performed by voltage does not have successfully decoded, this memorizer control circuit unit in order to set those third reading power taking pressures wherein more another be one the 3rd sign read voltage, voltage is read and those the 3rd verify that bit obtains those initial values of decoding again according to the 3rd sign, and those decoding initial values according to again obtaining perform this second decoding program
Wherein the 3rd sign reads the opposite side that voltage is positioned at this first sign reading voltage.
18. memory storage apparatus according to claim 16, it is characterized in that, those the 3rd checking bits, also in order to read voltage for this different signs, are inputed to different look-up tables again to obtain those decoding initial values by this memorizer control circuit unit.
19. memory storage apparatus according to claim 11, is characterized in that, this probability decoding algorithm is low-density parity check code.
20. memory storage apparatus according to claim 11, is characterized in that, this memorizer control circuit unit utilizes those first decoded bits to judge whether that the operation of successfully decoded comprises:
This memorizer control circuit unit produces multiple syndrome according to those first decoded bits, and judges whether those first decoded bits form effective code word according to those syndromes;
If those first decoded bits form effective code word, this memorizer control circuit unit judges successfully decoded.
21. 1 kinds of memorizer control circuit unit, is characterized in that, for controlling a reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module comprises multiple storage unit, and this memorizer control circuit unit comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module;
One bug check and correcting circuit; And
One memory management circuitry, be electrically connected to this host interface and this memory interface, in order to read multiple first storage unit in those storage unit according at least one first reading voltage, to obtain at least one first checking bit of each those the first storage unit
Wherein, bug check and correcting circuit are in order at least one first to verify bit to perform that one first decoding program comprising a probability decoding algorithm is to produce multiple first decoded bits according to this of those the first storage unit, and utilize those first decoded bits to judge whether successfully decoded
If decode unsuccessfully, this memory management circuitry reads those first storage unit to obtain at least one second checking bit of each those the first storage unit in order to read voltage according at least one second, and bug check and correcting circuit are in order at least one second to verify that bit performs this first decoding program to produce multiple second decoded bits according to this of those the first storage unit
Wherein this at least one second reading voltage is different from this at least one first reading voltage, and this at least one second number reading voltage is same as the number of this at least one first reading voltage.
22. memorizer control circuit unit according to claim 21, it is characterized in that, this memory management circuitry also in order to according to this at least one first read voltage one of them and one preset the difference read between voltage obtain an off-set value, and utilize this off-set value adjust this preset read voltage with obtain this at least one second reading voltage.
23. memorizer control circuit unit according to claim 22, is characterized in that, at least one first to read number of voltage be 1 for this, and this is preset, and to read voltage be first read voltage and this second reads between voltage between this.
24. memorizer control circuit unit according to claim 22, it is characterized in that, the operation that this memory management circuitry obtains this off-set value comprises:
This memory management circuitry by this at least one first read voltage this one of them and this preset the difference read between voltage and be multiplied by a multiplier to obtain this off-set value.
25. memorizer control circuit unit according to claim 21, is characterized in that, this memory management circuitry also in order to utilize those second decoded bits to judge whether successfully decoded,
If utilize those second decoded bits to judge to decode unsuccessfully, whether this memory management circuitry obtains the number of times of this at least one second reading voltage more than a preset times again in order to judgement,
If again obtain this at least one second this number of times reading voltage not exceed this preset times, this memory management circuitry is in order to again to obtain this at least one second reading voltage, and read those first storage unit again to obtain those the second checking bits according to this at least one second reading voltage again obtained
Wherein, bug check and correcting circuit in order to second to verify that bit performs this first decoding program according to those again obtaining,
If again obtain this at least one second this number of times reading voltage to exceed this preset times, this memory management circuitry is in order to stop again obtaining this at least one second reading voltage.
26. memorizer control circuit unit according to claim 25, is characterized in that, number and this at least one second number reading voltage of this at least one first reading voltage are 1,
If again obtain this second this number of times reading voltage to exceed this preset times, this memory management circuitry, in order to read those first storage unit according to multiple third reading power taking pressure, verifies bits with the obtain each those the first storage unit the multiple 3rd,
Wherein, this memory management circuitry is also that one first sign reads voltage in order to one of them setting those third reading power taking pressures, and those reading voltage and each those the first storage unit according to this first sign the 3rd verify that bit obtains one of each those the first storage unit and to decode initial value
Wherein, bug check and correcting circuit also perform one second decoding program to obtain multiple 3rd decoded bits in order to initial value of decoding to those, and utilize those the 3rd decoded bits to judge whether successfully decoded,
If utilize those the 3rd decoded bits to judge to decode unsuccessfully, this memory management circuitry is that one second sign reads voltage in order to set wherein another of those third reading power taking pressures, and read voltage according to this second sign and those the 3rd verify that bit obtains those initial values of decoding again
Wherein, bug check and correcting circuit are in order to perform this second decoding program according to those initial values of decoding again obtained.
27. memorizer control circuit unit according to claim 26, is characterized in that, it is the centre being positioned at those third reading power taking pressures that this first sign reads voltage, and this second sign reading voltage is positioned at the side that this first sign reads voltage,
If this second decoding program utilizing this second sign to read performed by voltage does not have successfully decoded, this memory management circuitry in order to set those third reading power taking pressures wherein more another be one the 3rd sign read voltage, and read voltage according to the 3rd sign and those the 3rd verify that bit obtains those initial values of decoding again
Wherein, those initial values of decoding that bug check and correcting circuit obtain again in order to basis perform this second decoding program,
Wherein the 3rd sign reads the opposite side that voltage is positioned at this first sign reading voltage.
28. memorizer control circuit unit according to claim 26, it is characterized in that, those the 3rd checking bits, also in order to read voltage for this different signs, are inputed to different look-up tables again to obtain those decoding initial values by this memory management circuitry.
29. memorizer control circuit unit according to claim 21, is characterized in that, this probability decoding algorithm is low-density parity check code.
30. memorizer control circuit unit according to claim 21, is characterized in that, this bug check and correcting circuit utilize those first decoded bits to judge whether that the operation of successfully decoded comprises:
This bug check and correcting circuit produce multiple syndrome according to those first decoded bits, and judge whether those first decoded bits form effective code word according to those syndromes; And
If those first decoded bits form effective code word, bug check and correcting circuit judge successfully decoded.
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