CN104539263B - Reconfigurable low-power dissipation digital FIR filter - Google Patents
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a reconfigurable low-power dissipation digital FIR filter. The FIR filter comprises a serial-in parallel-out module, a mode control module, a coefficient storage module, a multiplication unit dynamic switch module, a multiplication and addition operation module and a parallel-in serial-out module. The mode control module is mainly used for receiving the data of the fixed word length, which are input by the serial-in parallel-out module, the filter is arranged to be in a configuration mode or in an operation mode under the control of outside control signals, the configuration mode is used for setting the coefficients of the filter, then the multiplication operation unit at each step is judged through the multiplication unit dynamic switch module, and multiplication operation can be canceled according to judging results. The reconfigurable low-power dissipation digital FIR filter has the advantages that the coefficients can be configured according to needs, and accordingly the filter can be made to be suitable for different application scenes; the multiplication operations which have a small influence on the results are dynamically closed, and the dynamic power consumption of the filter can be effectively reduced. The reconfigurable low-power dissipation digital FIR filter is particularly suitable for FIR filters.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a reconfigurable low-power-consumption digital FIR filter.
Background
Digital fir (finite Impulse response) filter is a very common digital integrated circuit module in the field of signal processing. It has linear phase-frequency characteristics, limited unit impulse response, no input-to-output feedback, and stable system. Therefore, in the fields of audio, video, communication, automatic control, etc., digital filters are widely used to perform specific processing on various signals, and by changing the frequency characteristics of the signals, the digital filters play roles in acquiring useful signals, filtering noise, stabilizing loops, etc.
The simplest FIR filter is, as shown in fig. 1, constituted by multiplication and addition units, and implements the following operations:
Y[n]＝C0×X[n]+C1×X[n-1]+……+Cn-2×X[2]+Cn-1×X[1]+Cn×X[0]
in the formula: c0、C1、C2……Cn-1、CnAre coefficients that can determine the filter characteristics, where n is referred to as the order of the filter. Once the performance index of the filter is determined, its coefficient values and order can be determined by the Matlab tool. By setting different coefficients, the filter can process signals differently, such as low-pass, high-pass, band-stop, and the like. X0]、X[1]、X[2]、…….X[n-1]、X[n]The data to be processed is input from the outside and forms a data sequence to be processed.
The digital filter operating frequency f is a measure of the operating speed of the circuit. In the structure of fig. 1, every other period T equal to 1/f, the data sequence X [0], X [1], X [2], … …, X [ n-1], X [ n ] originally stored in each stage collectively propagates backward one stage, X [0] of the last stage is covered by the original X [1], X [ n ] receives a new data from the outside, which constitutes a new data sequence, and Y [ n ] is assigned a new value. The new Y [ n ] output is obtained from the new X [ n ] input to the calculation, and the time is not longer than one period, namely, the operation must be finished before the rising edge of the next period comes.
For a common FIR filter, coefficients and orders are given before design, and once the chip design is completed, the performance index cannot be changed. In some application scenarios, the characteristics of the FIR may be required to be changed artificially, and the FIR with fixed coefficients and orders has the disadvantage of being inflexible. Such as: in the field of wired communication and wireless communication, with the diversification of various communication standards, a traditional filter with single performance gradually fails to meet the application requirements brought by the diversification.
In addition, power consumption of digital circuits is also becoming a focus of attention. The power consumption of the digital circuit consists of two parts, namely static power consumption and dynamic power consumption. We can reduce the overall power consumption of the circuit by reducing the dynamic power consumption of the FIR, which is expressed as follows:
where α is the average activity factor, representing the turnover rate of each node in the circuit, f represents the operating frequency, VddDenotes the operating voltage, CtotalRepresenting the sum of the capacitances of the various nodes. The dynamic power consumption of the FIR filter circuit is determined by the above factors. The overall power consumption of the circuit can be reduced by reducing any one of them.
In the conventional FIR filter, the input data and coefficients are processed indiscriminately, and even if the absolute values of some data and coefficients are small, the product of the data and the coefficients has very little influence on the final result, and the FIR filter still performs multiplication and addition operation on the data like processing other data. However, the high bits of the data with smaller absolute values are all 0 or all 1, and during the operation, the bits will cause a great amount of signal inversion during the transition from 0 to 1 or from 1 to 0, and high dynamic power consumption is introduced. But because of their small absolute values, the product has little effect on the final result, which may even be negligible in certain applications where the accuracy requirements are not high. In summary, these data, which have little impact on the results, introduce a large amount of unnecessary dynamic power consumption, which makes the conventional FIR power consumption high. Compared with the traditional FIR, the invention improves the method in that the multiplication operation with small influence on the result is omitted in the range of acceptable precision, and the aim of reducing the dynamic power consumption is fulfilled.
Disclosure of Invention
The invention aims to provide a reconfigurable digital FIR filter structure with more flexible application and lower power consumption aiming at the defects of insufficient application range and overlarge power consumption of the existing digital FIR filter.
The technical scheme of the invention is as follows: a reconfigurable low-power-consumption digital FIR filter comprises a serial-in parallel-out module, a mode control module, a coefficient storage module, a multiplication unit dynamic switch module, a multiplication and addition operation module and a parallel-in serial-out module; the input end of the serial-in parallel-out module is connected with the external data input end, and the output end of the serial-in parallel-out module is connected with the data input end of the mode control module; the input end of the control signal of the mode control module is connected with an external control signal, the data output end of the mode control module is connected with the data input end of the multiplication and addition operation module and the input end of the multiplication unit dynamic switch module, and the coefficient output end of the mode control module is connected with the input end of the coefficient storage module; the output end of the multiplication unit dynamic switch module is connected with a multiplication and addition operation module; the coefficient input end of the multiplication and addition operation module is connected with the output end of the coefficient storage module; the output end of the multiplication and addition operation module is connected with the input end of the parallel-in serial-out module; the output end of the parallel-in serial-out module is the data output end of the filter; wherein,
the serial-in parallel-out module is used for converting single data input by an external data input end into data with a fixed word length and then inputting the data into the mode control module;
the mode control module receives data with fixed word length input by the serial-in parallel-out module and sets the filter to be in a configuration mode or an operation mode under the control of an external control signal;
the coefficient storage module is used for receiving coefficient data input by the mode control module, storing the coefficient of each order of the filter, and the coefficient output end of the coefficient storage module is connected with the multiplication and addition operation module;
the multiplication unit dynamic switch module is used for judging the multiplication operation unit of each stage and reserving or canceling the multiplication operation according to the judgment result; the judging method is that the data input by the mode control module is compared with a preset threshold value, if the data is larger than the threshold value, multiplication is reserved, and if the data is smaller than the threshold value, the multiplication is cancelled;
the multiplication and addition operation module is used for completing multiplication and addition operation required by the filter and inputting an operation result to the parallel-in serial-out module;
and the merging and serial output module is used for serially outputting the operation result with fixed bit width input by the multiply-add operation module.
The mode control module is used for determining the coefficient of the filter when the mode control module is set to be a configuration mode under the control of an external signal, and inputting the coefficient input by the serial-in parallel-out module into the coefficient storage module for storage;
and when the mode control module is set to be an operation mode under the control of an external signal, the data input by the serial-in parallel-out module is input to the multiply-add operation module for processing.
The method for judging the multiplication operation unit of each step by the multiplication unit dynamic switch module is that according to the size of the input data, the method is compared with a preset threshold value: if the absolute value of the input data is less than or equal to the threshold, the result value obtained by the data through multiplication is very small, and the influence on the final result is also very small, the multiplication unit corresponding to the data is turned off through an enable signal, the multiplication operation is cancelled, and therefore the power consumption consumed by one multiplication operation is saved; if the absolute value of the input data is larger than the threshold, the result obtained by the data through multiplication is larger, and the influence on the final result is larger, and then the data is sent to the corresponding multiplication unit for multiplication. By pre-judging the precision influence of the operation result of a certain order on the final output result, multiplication operations with small influence on the result precision are selectively abandoned, and the precision of the operation result can be ensured while the dynamic power consumption is reduced.
The filter has the advantages that the coefficient can be configured according to needs, so that the filter can be suitable for different application scenes; meanwhile, the dynamic power consumption of the filter can be effectively reduced by dynamically closing multiplication operations which have small influence on the result.
Drawings
Fig. 1 is a logical structure diagram of a conventional direct type FIR filter;
fig. 2 is a logical structure diagram of an FIR filter proposed in the present invention;
FIG. 3 is a block diagram of a multiply-add operation module;
FIG. 4 is a diagram of a partial product generation module;
FIG. 5 is a drawing of the Wallace tree structure;
FIG. 6 is a block diagram of a multiply-accumulate module;
FIG. 7 is a diagram of a dynamic switch module of the multiplication unit;
FIG. 8 is a diagram of an absolute value comparison module;
fig. 9 is a diagram showing a structure of a comparison result counting module.
Detailed Description
The invention is described in detail below with reference to the attached drawing
The embodiment of the invention provides a reconfigurable low-power-consumption digital FIR filter, which can configure coefficients according to needs and is suitable for different application scenes; meanwhile, the dynamic power consumption of the filter is reduced by dynamically closing multiplication operations which have small influence on the result.
As shown in fig. 2, the overall filter system is a 25-order 16 × 16 FIR filter comprising: the device comprises a serial-in parallel-out module, a mode control module, a coefficient storage module, a multiplication unit dynamic switch module, a multiplication and addition operation module and a parallel-in serial-out module 6 modules. Firstly, the FIR filter needs to configure the coefficients, the mode control module controls the entire FIR filter to be in a "configuration mode", the configuration enable signal is turned high, and the operation enable signal is kept at a low level. The serial-in parallel-out module inputs one bit of data from the data input end, outputs the data with fixed bit width after adjustment, and sends the data to the mode control module at the later stage, and the mode control module processes the data according to the mode of the current FIR filter. Under the 'configuration mode', data is taken as 'coefficients' and sent to a coefficient storage module at the later stage, if the coefficient storage module judges that all the coefficients are received, a high-level state flag signal is output to indicate that the coefficient configuration is finished and the coefficients are not received any more, and the FIR filter can be switched to the 'operation mode' to start operation. The FIR filter enters an operation mode by turning up the operation enabling signal, and data output by the serial-in parallel-out module is sent to the multiply-add operation module to carry out filtering operation with the previously configured coefficient in the operation mode.
As shown in fig. 3, the multiply-add operation module is composed of 25 partial product generation modules, 1 wallace tree, and 1 shift accumulation module. Fig. 4 is a partial product generation block structure, fig. 5 is a wallace tree structure diagram, and fig. 6 is a shift accumulation block structure diagram. The multiplication and addition module realizes multiplication operation by the idea of firstly solving the sum of partial products with the same weight and then shifting and accumulating to obtain a final result. The multiply-add operation module receives 16-bit data and a 16-bit "coefficient" as inputs and outputs a result after the multiply-add operation. The structure of the partial product generation module is shown in FIG. 4, and one operation period T iscomputeIn which the data is constant and the coefficients are every other clock period TperiodThe whole is shifted right by one bit (bit), and the rightmost bit of the coefficient is ANDed with the whole data to obtain the partial product corresponding to the bit of the coefficient, so that 25 partial products with the same weight are obtained in each clock cycle. All partial products are input into the Wallace tree at the later stage, and are input into the shift accumulation module at the later stage for storage after being compressed by the Wallace tree. And when the next clock period is reached, the coefficient is shifted to the right by one bit, the rightmost bit of the coefficient is updated, and the 25 new partial products are obtained after the operation, the weight of the 25 partial products is 1/2 of the partial product of the previous period, so that the result compressed by the Wallace tree cannot be directly added by shifting the result stored in the accumulator, but the original result is shifted first, and after the weight is adjusted, the original result is added with the sum of the newly obtained partial products, and the same weight is ensured. The result of the addition is stored in the shift accumulation module to wait for the nextArrival of partial product addition results. After 16 clock cycles, each bit of the 16-bit coefficient is subjected to three steps of calculating a corresponding partial product, compressing the partial product and shifting and accumulating. The result of shift accumulation has added the partial products of each weight to obtain the final result of the 25 factorial addition operation. The merging and deserializing unit of the later stage samples the operation result once every 16 clock cycles and then serially outputs the operation result. By this time, a filtering operation is completed, and one filtering operation period is ended, so that the operation period T is completedcompute＝16*TperiodAnd finishing operation every sixteen clock cycles, initializing a coefficient in the partial product generation module, inputting new data from the mode control module, merging into the serial output module, outputting a final calculation result, and starting a new operation cycle.
The multiplication and addition operation structure adopted by the invention replaces the traditional multiplier by using the shift operation of the coefficient in the register and the AND gate, and omits 25 multipliers. Meanwhile, the scale of the Wallace tree is greatly reduced, the Wallace tree in the invention compresses 25 16-bit partial products, and the Wallace tree needs to compress 25 32-bit products in the traditional multiplication unit. Therefore, the multiplication and addition operation module adopted by the invention reduces the circuit scale and saves the hardware resource.
The invention adopts a multiplication unit dynamic switch module, as shown in fig. 7, the module judges the absolute value of the data which needs multiplication through an absolute value comparison module, and the structure diagram of the module is shown in fig. 8. The thresholds in the absolute value comparison module are determined at the beginning of the design, where the positive number threshold is set to "0000 _0111_1111_ 1111" and the negative number threshold is set to "1111 _1000_0000_ 0000". In fig. 8, a five-input and gate and a five-input or gate check the absolute values of positive and negative numbers, respectively. If the data is positive and the absolute value is smaller than the threshold, the five-input AND gate outputs 0, the five-input OR gate also outputs 0, the XNOR gate outputs 1, and the absolute value comparison module outputs '1', at this time, the absolute value of the data is smaller than the threshold, the enable end of the partial product generation module corresponding to the data is enabled to be invalid, and the module does not perform operation. If the data is negative and the absolute value is smaller than the threshold, the five-input AND gate outputs 1, the five-input OR gate also outputs 1, the XNOR gate outputs 1, and the absolute value comparison module outputs '1', the absolute value comparison module also indicates that the absolute value of the data is smaller than the threshold, the enabling end of the partial product generation module corresponding to the data is enabled and disabled, and the module does not perform operation. On the contrary, if the output of the absolute value comparison module is '0', the data is represented that the absolute value is greater than the threshold value no matter whether the absolute value is positive or negative, the enabling end of the partial product generation module corresponding to the data is enabled to be effective, and the module carries out operation.
In order to avoid the introduction of large power consumption by frequent switching of the enabling end, the invention provides that when the absolute value of data is detected to be less than the threshold value for three times continuously, the partial product generating modules corresponding to the three data are turned off once. Therefore, a comparison result counting module is introduced, as shown in fig. 9, the input is the output comparison result signal of the absolute value comparison module, and the output is the shutdown control signal. Every time the comparison result signal is 1, the comparison result counting module adds 1, if the comparison result signals are all 1 for three times, the counting result is added to three, namely Q [2:0] is equal to 2' b011, at the moment, the output turn-off control signal is high, and the three continuous partial product generation modules are turned off at one time until the comparison result signal is detected to be 0. The comparison result counting module can immediately clear the count as long as the comparison result signal is detected to be 0, namely Q [2:0] is equal to 2' b000, and simultaneously, the OR gate is utilized to realize one-time shutdown of the three multiplication operation units. By dynamically turning off the operation of the multiplication unit, the multiplication operation with less influence on the result can be eliminated, thereby achieving the purpose of saving power consumption.
Claims (1)
1. A reconfigurable low-power-consumption digital FIR filter comprises a serial-in parallel-out module, a mode control module, a coefficient storage module, a multiplication unit dynamic switch module, a multiplication and addition operation module and a parallel-in serial-out module; the input end of the serial-in parallel-out module is connected with the external data input end, and the output end of the serial-in parallel-out module is connected with the data input end of the mode control module; the input end of the control signal of the mode control module is connected with an operation enabling signal and a configuration enabling signal, the data output end of the mode control module is connected with the data input end of the multiplication and addition operation module and the input end of the multiplication unit dynamic switch module, and the coefficient output end of the mode control module is connected with the input end of the coefficient storage module; the output end of the multiplication unit dynamic switch module is connected with a multiplication and addition operation module; the coefficient input end of the multiplication and addition operation module is connected with the output end of the coefficient storage module; the output end of the multiplication and addition operation module is connected with the input end of the parallel-in serial-out module; the output end of the parallel-in serial-out module is the data output end of the filter; wherein,
the serial-in parallel-out module is used for converting single data input by an external data input end into data with a fixed word length and then inputting the data into the mode control module;
the mode control module receives data with fixed word length input by the serial-in parallel-out module and sets the filter to be in a configuration mode or an operation mode under the control of an external control signal;
the coefficient storage module is used for receiving coefficient data input by the mode control module, storing the coefficient of each order of the filter, and the coefficient output end of the coefficient storage module is connected with the multiplication and addition operation module;
the multiplication unit dynamic switch module is used for judging the multiplication operation unit of each stage and reserving or canceling the multiplication operation according to the judgment result; the method for judging the multiplication operation unit of each stage by the multiplication unit dynamic switch module is to compare data input by the mode control module with a preset threshold, if the data are greater than the threshold, the multiplication operation is reserved, and if the data are less than the threshold, the multiplication operation is cancelled;
the multiplication and addition operation module consists of 25 partial product generation modules, 1 Wallace tree and 1 shift accumulation module; the partial product generating module receives 16-bit data and a 16-bit coefficient as input, and is used for enabling the data to be unchanged in one operation period, enabling the coefficient to integrally shift right by one bit every other clock period, and performing AND operation on the rightmost bit of the coefficient and the whole data to obtain a partial product corresponding to the bit of the coefficient, so that 25 partial products with the same weight can be obtained in each clock period, all the partial products are input into a Wallace tree at the later stage, and are input into a shift accumulation module at the later stage for storage after Wallace tree compression; when the next clock period is reached, the coefficient is shifted to the right by one bit, the rightmost bit of the coefficient is updated, and 25 new partial products are obtained after operation, the weight of the 25 partial products is 1/2 of the partial product of the previous period, so that the result compressed by the Wallace tree cannot be directly added by the result stored in the shift accumulator, but the original result is shifted first, and after the weight is adjusted, the original result is added with the sum of the newly obtained partial products, and the same weight is ensured; the added result is stored in the shift accumulation module continuously, and the arrival of the next partial product addition result is waited; after 16 clock cycles, each bit of the 16-bit coefficient is subjected to three steps of calculation of corresponding partial product, partial product compression and shift accumulation; the result of shift accumulation has added the partial product of each weight to get the final result of 25 factorial addition operation;
and the merging and serial output module is used for serially outputting the operation result with fixed bit width input by the multiply-add operation module.
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