CN104538454A - 低温多晶硅薄膜晶体管及其制造方法 - Google Patents

低温多晶硅薄膜晶体管及其制造方法 Download PDF

Info

Publication number
CN104538454A
CN104538454A CN201410837376.8A CN201410837376A CN104538454A CN 104538454 A CN104538454 A CN 104538454A CN 201410837376 A CN201410837376 A CN 201410837376A CN 104538454 A CN104538454 A CN 104538454A
Authority
CN
China
Prior art keywords
layer
film transistor
low
lug boss
light shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410837376.8A
Other languages
English (en)
Other versions
CN104538454B (zh
Inventor
***
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201410837376.8A priority Critical patent/CN104538454B/zh
Priority to US14/424,432 priority patent/US9899530B2/en
Priority to PCT/CN2015/072595 priority patent/WO2016101402A1/zh
Publication of CN104538454A publication Critical patent/CN104538454A/zh
Application granted granted Critical
Publication of CN104538454B publication Critical patent/CN104538454B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02592Microstructure amorphous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/126Shielding, e.g. light-blocking means over the TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供一种低温多晶硅薄膜晶体管及其制造方法,包括:基板(1)、设于基板(1)上的遮光层(2)、设于遮光层(2)上的衬垫层(3)、设于衬垫层上的介质层(4)、设于介质层上的有源层(5)、设于有源层(5)上的栅极绝缘层(6)、设于栅极绝缘层(6)上的栅极层(7);其中,遮光层(2)包括设于基板(1)上的平坦部(21)、及设于平坦部(21)上的凸起部(22);有源层(5)的投影至少覆盖所述凸起部(22)的上表面局部区域及所述凸起部(22)的一个侧壁(224),能够在不改变显示装置开口率的前提下,有效地增加沟道宽度,增加沟道的宽长比,提高了开态电流,提升低温多晶硅薄膜晶体管的驱动能力及器件性能。

Description

低温多晶硅薄膜晶体管及其制造方法
技术领域
本发明涉及显示技术领域,尤其涉及一种低温多晶硅薄膜晶体管及其制造方法。
背景技术
随着显示技术的发展,平板显示装置因具有高画质、省电、机身薄及应用范围广等优点,而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品,成为显示装置中的主流。
主动矩阵式(Active Matrix,AM)平板显示装置是目前最常用的显示装置,所述主动矩阵式平板显示装置通过一薄膜晶体管开关(Thin FilmTransistor,TFT)来控制数据信号的输入,进而控制画面显示。
目前的显示技术朝着高分辨率的方向不断发展,例如手机的分辨率已经达到1080P的水准(1080×1920),而电视的分辨率更是达到4K(4096×2160)的级别,伴随着分辨率的不断提升,需要不断提高TFT器件的驱动能力。因而,具有高分辨率、反应速度快、高亮度、高开口率等优点的低温多晶硅(LowTemperature Poly-silicon,LTPS)薄膜晶体管显示装置也越来越受关注,为了满足高分辨率的显示装置的驱动能力要求,需要提高显示装置像素区和驱动区的开态电流,提高开态电流的方法为增大TFT器件沟道的宽长比,具体的,所述开态电流ID与TFT器件沟道的宽长比的相关公式为:线性区: I D = W T μ C ox ( V G - V T ) V D ; 饱和区: I D = 1 2 W T μ C ox ( V G - V T ) 2 ; 从上述公式可确定,无论是对于线性区还是饱和区,提高开态电流都有两种方法,一是增加沟道宽度W,但是随着沟道宽度W的增加,显示装置的开口率也会随之降低,从而降低面板设计的空间;二是减小沟道长度L,但是沟道长度L过小会增加沟道被击穿风险,因此在沟道长度L的变化上范围十分有限。
发明内容
本发明的目的在于提供一种低温多晶硅薄膜晶体管,用于驱动主动矩阵式显示器件,该低温多晶硅薄膜晶体管能够在不改变显示装置开口率的前提下,有效地增加沟道宽度,增加沟道的宽长比,提高了开态电流,进而提升了低温多晶硅薄膜晶体管的驱动能力及器件性能。
本发明的目的还在于提供一种低温多晶硅薄膜晶体管的制造方法,采用该法能够制造具有较大的沟道宽度与沟道的宽长比低温多晶硅薄膜晶体管,进而提高开态电流,使得该低温多晶硅薄膜晶体管具有优异的驱动能力及器件性能。
为实现上述目的,本发明首先提供一种低温多晶硅薄膜晶体管,包括:基板、设于所述基板上的遮光层、设于所述遮光层上的衬垫层、设于所述衬垫层上的介质层、设于所述介质层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极层;
其中,所述遮光层包括设于所述基板上的平坦部、及设于所述平坦部上的凸起部;
所述有源层的投影至少覆盖所述凸起部的上表面局部区域及所述凸起部的一个侧壁。
所述遮光层的材料为钼。
所述遮光层位于凸起部处的厚度为800至2500埃,所述凸起部的高度为300至800埃,所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
所述衬垫层的材料为氮化硅,厚度为400至500埃;所述介质层的材料为二氧化硅,厚度为1000至2000埃。
所述有源层的厚度为400至500埃。
本发明还提供一种低温多晶硅薄膜晶体管的制造方法,包括如下步骤:
步骤1、提供一基板,在所述基板上通过物理气相沉积工艺沉积一遮光层,通过灰阶曝光和刻蚀形成所述遮光层的平坦部与凸起部;
步骤2、采用等离子增强化学气相沉积工艺在所述遮光上依次沉积形成衬垫层、及介质层;
步骤3、在介质层上与所述遮光层的凸起部相对应的区域沉积一非晶硅层,所述非晶硅层的投影覆盖整个凸起部,然后将所述非晶硅层转化为多晶硅层;
步骤4、刻蚀所述多晶硅层形成一有源层,所述有源层至少覆盖在所述凸起部上表面的局部区域及所述凸起部的一个侧壁上;
步骤5、在所述有源层的上方依次沉积并刻蚀形成栅极绝缘层及栅极层。
所述步骤1中所述遮光层的材料为钼。
所述步骤1中所述遮光层位于凸起部处的厚度为800至2500埃,所述凸起部的高度为300至800埃,所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
所述步骤2中所述衬垫层的材料为氮化硅,厚度为400至500埃;所述介质层的材料为二氧化硅,厚度为1000至2000埃。
所述步骤4中所述有源层的厚度为400至500埃。
本发明的有益效果:本发明提供一种低温多晶硅薄膜晶体管及其制造方法,通过在基板上设置一具有凸起的遮光层,再在遮光层上设置其余部分,有效地增加了该低温多晶硅薄膜晶体管沟道宽度和沟道的宽长比,提高了开态电流,提升了低温多晶硅薄膜晶体管的驱动能力及器件性能,且不影响显示器件的开口率,采用的制造方法工艺简单,易于操作。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为一种低温多晶硅薄膜晶体管的平面示意图;
图2为本发明的低温多晶硅薄膜晶体管沿A-A线截面图;
图3为本发明的低温多晶硅薄膜晶体管的制造方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
图1为一种低温多晶硅薄膜晶体管的平面示意图;如图1所示,所述低温多晶硅薄膜晶体管包括栅极100、源极200、漏极300及有源层400,所述源极200与漏极300分别通过过孔500与有源层400相接触。
图2为本发明的低温多晶硅薄膜晶体管沿A-A线截面图,如图2所示,本发明提供一种低温多晶硅薄膜晶体管,包括:基板1、设于所述基板1上的遮光层2、设于所述遮光层2上的衬垫层3、设于所述衬垫层3上的介质层4、设于所述介质层4上的有源层5、设于所述有源层5上的栅极绝缘层6、设于所述栅极绝缘层6上的栅极层7;
具体的,所述遮光层2包括设于所述基板1上的平坦部21、及设于所述平坦部21上的凸起部22;所述遮光层2的材料为钼。所述遮光层2位于凸起部22处的厚度为800至2500埃,所述凸起部22的高度为300至800埃,所述凸起部22的两侧侧壁224与所述衬垫层3之间的角度为35°至70°。通过在所述遮光层2上制备凸起部22,可以在不改变显示装置开口率的前提下,有效地增加沟道宽度。
进一步的,所述衬垫层3的材料为氮化硅,厚度为400至500埃;所述介质层4的材料为二氧化硅,厚度为1000至2000埃。所述衬垫层3和介质层4共同构成缓冲层。
此外,所述有源层5的投影至少覆盖所述凸起部22的上表面局部区域及所述凸起部22的一个侧壁224。所述有源层5的厚度为400至500埃。
请参阅图2及图3,本发明还提供了一种低温多晶硅薄膜晶体管的制造方法,包括如下步骤:
步骤1、提供一基板1,在所述基板1上通过物理气相沉积工艺沉积一遮光层2,通过灰阶曝光和刻蚀形成所述遮光层2的平坦部21与凸起部22;
具体的,所述遮光层2的材料为钼或其他类似的金属或有机材料,所述遮光层2位于凸起部22处的厚度为800至2500埃,所述凸起部22的高度为300至800埃,所述凸起部22的两侧侧壁224与所述衬垫层3之间的角度为35°至70°。通过在所述遮光层2上制备凸起部22,然后在所述凸起部22上形成有源层,可以在不改变显示装置开口率的前提下,有效地增加的沟道宽度。
具体的,采用半透掩模工艺,利用干刻蚀形成所述遮光层2的平坦部21和的凸起部22。
步骤2、采用等离子增强化学气相沉积工艺在所述遮光层2上依次沉积形成衬垫层3、及介质层4;
具体的,沉积的温度为400度至450度,所述衬垫层3的材料为氮化硅,厚度为400至500埃;所述介质层4的材料为二氧化硅,厚度为1000至2000埃。所述衬垫层3与介质层4共同构成缓冲层。
步骤3、在介质层2上与所述遮光层2的凸起部22相对应的区域沉积一非晶硅层,所述非晶硅层的投影覆盖整个凸起部22,然后将所述非晶硅层转化为多晶硅层;
具体的,采用化学气相沉积工艺沉积所述非晶硅层,沉积的温度为400℃至500℃,沉积的非晶硅层的厚度为400至500埃。采用准分子激光退火(ELA)或固相结晶(SPC)的方法将非晶硅层转化为多晶硅层。
步骤4、刻蚀所述多晶硅层形成一有源层5,所述有源层5至少覆盖在所述凸起部22上表面的局部区域及所述凸起部22的一个侧壁224;
具体的,所述有源层5的厚度为400至500埃。
步骤5、在所述有源层5的上方依次沉积并刻蚀形成栅极绝缘层6及栅极层7。
此外,该低温多晶硅薄膜晶体管的制造方法还可以包括:
步骤6、在具有栅极层7的基板1表面上,再沉积一介电层,该介电层的材料可以为氧化硅或氮化硅;接着利用光刻和蚀刻工序在源极欧姆接触区域以及漏极欧姆区域的上方的介电层以及栅极绝缘层6内分别形成直达源极的接触孔以及直达漏极的接触孔;
步骤7、最后在基板1表面上沉积第二金属层,如一铝层、一钨层、一铬层或其他金属单层或复合多层导电层;接着利用光刻及刻蚀工序,形成源极和漏极,这样就可以把信号从源极电连接至漏极,完成整个低温多晶硅薄膜晶体管的制造过程。
综上所述,本发明提供一种低温多晶硅薄膜晶体管及其制造方法,通过在基板上设置一具有凸起的遮光层,再在遮光层上设置其余部分,可以有效地增加该低温多晶硅薄膜晶体管的沟道宽度和沟道的宽长比,提高了开态电流,进而提升了低温多晶硅薄膜晶体管的驱动能力及器件性能,且不影响显示器件的开口率,采用的制造方法工艺简单,易于操作。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种低温多晶硅薄膜晶体管,其特征在于,包括:基板(1)、设于所述基板(1)上的遮光层(2)、设于所述遮光层(2)上的衬垫层(3)、设于所述衬垫层(3)上的介质层(4)、设于所述介质层(4)上的有源层(5)、设于所述有源层(5)上的栅极绝缘层(6)、设于所述栅极绝缘层(6)上的栅极层(7);
其中,所述遮光层(2)包括设于所述基板(1)上的平坦部(21)、及设于所述平坦部(21)上的凸起部(22);
所述有源层(5)的投影至少覆盖所述凸起部(22)的上表面局部区域及所述凸起部(22)的一个侧壁(224)。
2.如权利要求1所述的低温多晶硅薄膜晶体管,其特征在于,所述遮光层(2)的材料为钼。
3.如权利要求2所述的低温多晶硅薄膜晶体管,其特征在于,所述遮光层(2)位于凸起部(22)处的厚度为800至2500埃,所述凸起部(22)的高度为300至800埃,所述凸起部(22)的两侧侧壁(224)与所述衬垫层(3)之间的角度为35°至70°。
4.如权利要求1所述的低温多晶硅薄膜晶体管,其特征在于,所述衬垫层(3)的材料为氮化硅,厚度为400至500埃;所述介质层(4)的材料为二氧化硅,厚度为1000至2000埃。
5.如权利要求1所述的低温多晶硅薄膜晶体管,其特征在于,所述有源层(5)的厚度为400至500埃。
6.一种低温多晶硅薄膜晶体管的制造方法,其特征在于,包括如下步骤:
步骤1、提供一基板(1),在所述基板(1)上通过物理气相沉积工艺沉积一遮光层(2),通过灰阶曝光和刻蚀形成所述遮光层(2)的的平坦部(21)与凸起部(22);
步骤2、采用等离子增强化学气相沉积工艺在所述遮光层(2)上依次沉积形成衬垫层(3)、及介质层(4);
步骤3、在介质层(2)上与所述遮光层(2)的凸起部(22)相对应的区域沉积一非晶硅层,所述非晶硅层的投影覆盖整个凸起部(22),然后将所述非晶硅层转化为多晶硅层;
步骤4、刻蚀所述多晶硅层形成一有源层(5),所述有源层(5)至少覆盖在所述凸起部(22)上表面的局部区域及所述凸起部(22)的一个侧壁(224)上;
步骤5、在所述有源层(5)的上方依次沉积并刻蚀形成栅极绝缘层(6)及栅极层(7)。
7.如权利要求6所述的低温多晶硅薄膜晶体管的制造方法,其特征在于,所述步骤1中所述遮光层(2)的材料为钼。
8.如权利要求6所述的低温多晶硅薄膜晶体管的制造方法,其特征在于,所述步骤1中所述遮光层(2)位于凸起部(22)处的厚度为800至2500埃,所述凸起部(22)的高度为300至800埃,所述凸起部(22)的两侧侧壁(224)与所述衬垫层(3)之间的角度为35°至70°。
9.如权利要求6所述的低温多晶硅薄膜晶体管的制造方法,其特征在于,所述步骤2中所述衬垫层(3)的材料为氮化硅,厚度为400至500埃;所述介质层(4)的材料为二氧化硅,厚度为1000至2000埃。
10.如权利要求6所述的低温多晶硅薄膜晶体管的制造方法,其特征在于,所述步骤4中所述有源层(5)的厚度为400至500埃。
CN201410837376.8A 2014-12-26 2014-12-26 低温多晶硅薄膜晶体管及其制造方法 Active CN104538454B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410837376.8A CN104538454B (zh) 2014-12-26 2014-12-26 低温多晶硅薄膜晶体管及其制造方法
US14/424,432 US9899530B2 (en) 2014-12-26 2015-02-09 Low temperature poly-silicon thin-film transistor and manufacturing method thereof
PCT/CN2015/072595 WO2016101402A1 (zh) 2014-12-26 2015-02-09 低温多晶硅薄膜晶体管及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410837376.8A CN104538454B (zh) 2014-12-26 2014-12-26 低温多晶硅薄膜晶体管及其制造方法

Publications (2)

Publication Number Publication Date
CN104538454A true CN104538454A (zh) 2015-04-22
CN104538454B CN104538454B (zh) 2017-12-01

Family

ID=52853954

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410837376.8A Active CN104538454B (zh) 2014-12-26 2014-12-26 低温多晶硅薄膜晶体管及其制造方法

Country Status (3)

Country Link
US (1) US9899530B2 (zh)
CN (1) CN104538454B (zh)
WO (1) WO2016101402A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017121139A1 (zh) * 2016-01-11 2017-07-20 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN108198861A (zh) * 2017-12-28 2018-06-22 武汉华星光电技术有限公司 薄膜晶体管
CN108231794A (zh) * 2018-01-02 2018-06-29 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板
WO2018214635A1 (zh) * 2017-05-24 2018-11-29 京东方科技集团股份有限公司 阵列基板、显示装置以及制备阵列基板的方法
CN111969029A (zh) * 2020-08-31 2020-11-20 江苏仕邦柔性电子研究院有限公司 一种用于oled显示面板的tft器件结构
CN112071863A (zh) * 2020-09-04 2020-12-11 Tcl华星光电技术有限公司 一种阵列基板
WO2023077661A1 (zh) * 2021-11-05 2023-05-11 京东方科技集团股份有限公司 显示基板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285976A (ja) * 2004-03-29 2005-10-13 Seiko Epson Corp 半導体装置及びその製造方法、並びにこれを備えた電気光学装置及び電子機器
JP2008116531A (ja) * 2006-11-01 2008-05-22 Seiko Epson Corp 遮光膜の形成方法及び電気光学装置の製造方法
JP2010074030A (ja) * 2008-09-22 2010-04-02 Seiko Epson Corp 薄膜トランジスタおよび電気光学装置
CN103268855A (zh) * 2012-12-19 2013-08-28 上海天马微电子有限公司 多晶硅形成方法、tft阵列基板制造方法及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3701832B2 (ja) * 2000-02-04 2005-10-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 薄膜トランジスタ、液晶表示パネル、および薄膜トランジスタの製造方法
JP4569016B2 (ja) * 2000-07-27 2010-10-27 旭硝子株式会社 液晶表示装置用ブラックマトリクスおよびカラーフィルタ
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
FR2848011B1 (fr) * 2002-12-03 2005-12-30 Thales Sa Structure de matrice active pour ecran de visualisation et ecran comportant une telle matrice
KR100675631B1 (ko) * 2003-06-27 2007-02-01 엘지.필립스 엘시디 주식회사 횡전계방식 액정표시장치 및 그 제조방법
US8110832B2 (en) * 2007-02-22 2012-02-07 Seiko Epson Corporation Electro-optical substrate, method for designing the same, electro-optical device, and electronic apparatus
JP5458367B2 (ja) * 2007-07-09 2014-04-02 Nltテクノロジー株式会社 薄膜トランジスタ及びその製造方法
WO2012050006A1 (ja) * 2010-10-12 2012-04-19 シャープ株式会社 アレイ基板、及び、その製造方法
KR101284287B1 (ko) * 2010-12-21 2013-07-08 엘지디스플레이 주식회사 액정 표시장치와 이의 제조방법
CN105097940A (zh) * 2014-04-25 2015-11-25 上海和辉光电有限公司 薄膜晶体管阵列衬底结构及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285976A (ja) * 2004-03-29 2005-10-13 Seiko Epson Corp 半導体装置及びその製造方法、並びにこれを備えた電気光学装置及び電子機器
JP2008116531A (ja) * 2006-11-01 2008-05-22 Seiko Epson Corp 遮光膜の形成方法及び電気光学装置の製造方法
JP2010074030A (ja) * 2008-09-22 2010-04-02 Seiko Epson Corp 薄膜トランジスタおよび電気光学装置
CN103268855A (zh) * 2012-12-19 2013-08-28 上海天马微电子有限公司 多晶硅形成方法、tft阵列基板制造方法及显示装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017121139A1 (zh) * 2016-01-11 2017-07-20 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
US10032807B2 (en) 2016-01-11 2018-07-24 Boe Technology Group Co., Ltd. Array substrate and fabrication method thereof, and display panel
WO2018214635A1 (zh) * 2017-05-24 2018-11-29 京东方科技集团股份有限公司 阵列基板、显示装置以及制备阵列基板的方法
CN108198861A (zh) * 2017-12-28 2018-06-22 武汉华星光电技术有限公司 薄膜晶体管
CN108231794A (zh) * 2018-01-02 2018-06-29 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板
CN108231794B (zh) * 2018-01-02 2020-07-17 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板
CN111969029A (zh) * 2020-08-31 2020-11-20 江苏仕邦柔性电子研究院有限公司 一种用于oled显示面板的tft器件结构
CN112071863A (zh) * 2020-09-04 2020-12-11 Tcl华星光电技术有限公司 一种阵列基板
WO2022047908A1 (zh) * 2020-09-04 2022-03-10 Tcl华星光电技术有限公司 一种阵列基板及其制备方法
US12002814B2 (en) 2020-09-04 2024-06-04 Tcl China Star Optoelectronics Technology Co., Ltd. Array substrate and manufacturing method thereof
WO2023077661A1 (zh) * 2021-11-05 2023-05-11 京东方科技集团股份有限公司 显示基板和显示装置

Also Published As

Publication number Publication date
CN104538454B (zh) 2017-12-01
US9899530B2 (en) 2018-02-20
WO2016101402A1 (zh) 2016-06-30
US20160343874A1 (en) 2016-11-24

Similar Documents

Publication Publication Date Title
CN104538454A (zh) 低温多晶硅薄膜晶体管及其制造方法
CN103824780B (zh) 一种低温多晶硅tft器件及其制造方法
CN106558593A (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN101325201B (zh) 一种透明薄膜晶体管的阵列基板结构及其制造方法
CN107425044B (zh) 一种柔性显示面板、其制作方法及显示装置
CN105097675A (zh) 阵列基板及其制备方法
CN103314431A (zh) 制造氧化物薄膜晶体管阵列的方法和结合其的装置
CN105470197A (zh) 低温多晶硅阵列基板的制作方法
US20180190490A1 (en) Thin film transistor and method for fabricating the same
CN105097550A (zh) 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN103489921B (zh) 一种薄膜晶体管及其制造方法、阵列基板及显示装置
CN104952880A (zh) 双栅极tft基板的制作方法及其结构
US10121883B2 (en) Manufacturing method of top gate thin-film transistor
CN105470196A (zh) 薄膜晶体管、阵列基板及其制造方法、和显示装置
CN109524419A (zh) Tft阵列基板的制作方法
CN106449655A (zh) 薄膜晶体管阵列基板及其制作方法
CN106356306A (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
CN103928472A (zh) 一种阵列基板及其制作方法和显示装置
EP3001460B1 (en) Thin film transistor and preparation method therefor, display substrate, and display apparatus
US20160181290A1 (en) Thin film transistor and fabricating method thereof, and display device
CN102629589B (zh) 一种阵列基板及其制作方法和显示装置
US10957713B2 (en) LTPS TFT substrate and manufacturing method thereof
US10629746B2 (en) Array substrate and manufacturing method thereof
CN103730474B (zh) 一种阵列基板及其制造方法、显示装置
CN103022083A (zh) 一种阵列基板、显示装置及阵列基板的制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant