CN1045356C - Signal processing apparatus - Google Patents
Signal processing apparatus Download PDFInfo
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- CN1045356C CN1045356C CN93100375A CN93100375A CN1045356C CN 1045356 C CN1045356 C CN 1045356C CN 93100375 A CN93100375 A CN 93100375A CN 93100375 A CN93100375 A CN 93100375A CN 1045356 C CN1045356 C CN 1045356C
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Abstract
The present invention relates to a signal processing device used for processing and limiting line synchronous pulses in line synchronous signals of analog video signal line periods. The device comprises a phase-locked loop (40) for generating a clock signal, wherein the frequency of the signal is an integer multiple of the frequency of a line synchronous signal, and the phase-locked loop comprises a counter (100) used for dividing a clock signal by the integer multiple. The device also comprises a logical part (110, 50) which is used for detecting the reset counter (100) when spurious pulses introduce a time interval shorter than a video signal line period in the line synchronous signal. The device is especially suitable for quantizing image processing systems with the analog video signals of line synchronous pulses.
Description
The present invention relates to a kind of signal processing apparatus, it is used for revising the horizontal synchronizing pulse of looking genuine that video tape recorder jumps and produces because of magnetic head.
With the analog video signal of the generation of gamma camera and so on, the mode with the series of parallel road is encoded on the videotape by magnetic usually, and these parallel track and videotape path are with an angle is arranged.A field of frame of video is represented in each road.Represent the road of odd field to be staggered in the road of representing even field.To the frame of video of 625 row, per pass is represented 325.5 row like this, and each row all separates with delegation's (Sync) pulse synchronously.
Traditional resembling with video tape recorder comprises a cylindricality reproducing head, and this is loaded with two along a magnetic pick-up that diameter is relative.Be in operation, videotape is being taken turns when advancing on this recording-playing head to another from a wheel.The rotating manner of head makes a pick-up only read the road of representing odd field and another pick-up only reads the road of representing even field.By when two pick-ups alternately contact with in succession road on the videotape, between them, switching, be able to reproducing of video.Thereby the geometry transient state between replay signal requires the videotape motion and head rotates is aimed at.But aim at because the end in road in succession is common, thereby the horizontal synchronizing pulse of looking genuine is added on the playback of video signal in practice, with the exchange of pick-up.The horizontal synchronizing pulse of respectively looking genuine between the consecutive line near the playback video signal of each end, has risen up into a time interval effectively.The length in this time interval is than line period much shorter.This result is called " head jumps " sometimes.
The image that traditional radio and television receiver shows, at the end that closes on a field and at the place that begins of next, its scanning has exceeded the edge of screen.This provides a period of time, and receiver can be synchronized to incoming sync pulse between the picture frame that shows in succession therebetween.Thereby when vision signal displayed image that this class receiver reproduces according to the conventional domestic video tape recorder, the time interval that the horizontal synchronizing pulse of looking genuine is introduced can not make image deflects significantly.Yet some display unit, as the computer graphic image display device, the scanning of the image that is produced does not exceed the edge of screen.Thereby the shown image of this device time interval of can being looked genuine significantly twist.
Some image processing system has comprised the signal processing apparatus that is used for the video signal digitization of family expenses video tape recorder reproduction.The sampling clock frequency is controlled in the timing generation that this signal processing apparatus is in operation and relies on the horizontal synchronizing pulse corresponding with vision signal.Generally, this signal processing apparatus comprises and being used for sample video and A/D converter that each sampling is quantized.Carry out at the well-regulated interval that sampling is determined by a clock signal.Use a phase-locked loop, the horizontal synchronizing pulse phase-locked loop that makes clock signal be synchronized with vision signal comprises that one is used for the voltage-controlled oscillator (VCD) of clocking and the number of samples that is used for requiring with each line period is removed the counter of clock signal.One phase comparator is compared horizontal synchronizing pulse with the output of counter, to produce a phase error signal.This phase error signal is added to the VCO input, to determine the frequency of clock signal.The output of counter provides a negative feedback like this, and it makes phase error reduce to zero, and makes clock signal be synchronized with horizontal synchronizing pulse thus.Thereby as long as horizontal synchronizing pulse keeps conforming to the pulse of counter output, the sampling clock frequency just remains unchanged.Yet because the time interval that the horizontal synchronizing pulse of looking genuine is introduced far is shorter than line period, the horizontal synchronizing pulse of looking genuine does not conform to pulse from counter output.This has produced harmful transient state distortion of progressively changing of sampling clock frequency and quantitation video signal.Traditionally, by change the stepping response of phase-locked loop by complicated and expensive analog circuit, compensate the horizontal synchronizing pulse of looking genuine that causes by the head jump.
According to the present invention, a kind of signal processing apparatus is provided, be used for handling the horizontal synchronizing pulse of the line synchronizing signal of determining the analog video signal line period, this device comprises: be used to produce the phase-locked loop of a clock signal, the frequency of this signal is the integral multiple of line synchronizing signal frequency; Counter in phase-locked loop is used for removing clock signal with described multiple; It is characterized in that this device also comprises: be used for the logical gate that makes counter reset when any spurious pulse is incorporated into line synchronizing signal to the time interval less than the vision signal line period detecting.
The present invention is based on such understanding, even in the process of playback video signal from video tape recording, the time interval of looking genuine has been introduced line synchronizing signal, but spurious pulse by the time interval that qualification is looked genuine and phase-locked loop input separate and this pulse are added on the RESET input of counter, and clock pulse is remained unchanged.Thereby the input of phase-locked loop covered by this logical gate, makes it not touch the lock-out pulse that looks genuine in the line synchronizing signal.Like this, what the present invention caused for retrieving head jumps looks genuine the time interval, and effective digital solution is provided, and this method is compared easier thereby also more cheap with the analogy method of traditional change phase-locked loop stepping response.
This logical gate preferably includes a multiplexer, is used for each horizontal synchronizing pulse of responsive trip synchronizing signal, line synchronizing signal is switched to one period less than line period of the RESET input of counter from the phase comparator input of phase-locked loop.The most handy simple thereby cheap gate setting of multiplexer is realized.
In a most preferred embodiment of the present invention, logical gate comprises a timer, is used for when the synchronization signal detection of being expert at during to the trailing edge of horizontal synchronizing pulse, and the control input end of multiplexer is switched to one period resetting time of second state from first state.Timer can have the triggering input of linking the phase comparator input, thereby multiplexer disconnected line synchronizing signal and triggering input in resetting time, thereby prevents that resetting time from prolonging.Perhaps, timer can make and can not trigger again, triggers input and can keep linking to each other with line synchronizing signal in resetting time thereby make.
To see that below this timer can comprise simple thereby cheap one-shot multivibrator.
In a most preferred embodiment of the present invention, multiplexer comprises a pair of AND gate, and timer one monostable circuit, and this circuit has the paraphase and the non-phase output terminal of leading of the AND gate linked, and is used for starting respectively different AND gates.Like this, the present invention can implement with traditional gate.
For increasing the sensitivity to the lock-out pulse that looks genuine as far as possible, this logical gate can be suitable for the reset cycle roughly is set at the poor of line period and horizontal synchronizing pulse width.
It will be appreciated that, the present invention also comprises image-processing system, it is the analog video signal of the line period of mark that this device is used for handling the horizontal synchronizing pulse that has with line synchronizing signal, and this device comprises: the phase-locked loop of clock signal that is used to produce the frequency of the multiple with line synchronizing signal frequency; Counter in phase-locked loop, that be used for removing clock signal with described multiple; The interval of determining with clock signal quantizes the A/D converter of the sampling of vision signal: it is characterized in that this device also comprises: be used for detecting spurious pulse a logical gate that resets register during less than the time interval introducing line synchronizing signal of vision signal line period.
Below in conjunction with accompanying drawing, by way of example, one embodiment of the present of invention are described.In the accompanying drawings:
Fig. 1 is the synchronization scheme that tradition resembles the vision signal of emitting from videotape with video recorder:
Fig. 2 is the block diagram of an example of signal processing apparatus of the present invention:
Fig. 3 is the block diagram that is used for the synchronous logic part of signal processing apparatus of the present invention:
Fig. 4 is the synchronous block diagram corresponding with same logical gate.
Referring to Fig. 1, tradition resembles the analog video signal that reproduces with video recorder and comprises series of fields, and each field all contains the capable analog video data of L5.Field is in succession separated at interval by the field blanking that length equals the capable video data of L2.The field in succession of vision signal is existed in the road in succession on the video tape.Video recorder has one to be loaded with two cylindricality reproducing heads along the relative magnetic pick-up of diameter.When video tape when a reel advances to another, it is round head.The rotation mode of head makes a pick-up only read to represent the equal road of odd number and another pick-up only reads the road of representing even field.By when two pick-ups alternately contact with in succession road on the video tape, between pick-up, switching, reproduced vision signal.In practice, if in succession road end does not align with the exchange of pick-up, then just produced the horizontal synchronizing pulse PE that looks genuine.Spurious pulse PE is inserted into apart from existing the capable part of terminal L6.In the traditional tv receiver, capable being scanned under the visual lower edge of existing terminal L1, thereby end demonstrates.Similarly, next the L3 that begins to locate is capable is scanned on the visual upper edge.L6 is less than L1.Generally, L6 is 8, and L1 is 12.Thereby this receiver has the capable cycle of L6+L2+L3 that adds up to, and can be locked on the line period before showing next image field therebetween.Yet some digital image processing systems can come displayed image according to the vision signal on the visual display unit that overscanning (overscan) can not take place, or in a window of this class display unit displayed image.Thereby for the harmful image in avoiding resetting disturbs, image processing system must compensate this spurious pulse PE.
Now referring to Fig. 2, according to of the present invention, be used to quantize the example that tradition resembles the signal processing apparatus of the analog video signal that reproduces with video recorder and comprise an A/D converter (ADC) 10, it has the analog input end 170 that can link the reproducing head 30 of video recorder through Signal Regulation amplifier 20 with pulling down.ADC 20 has the sampling clock input 60 of the output of linking phase-locked loop 40.The output of phase-locked loop 40 is produced by voltage-controlled oscillator (VCO) 70.VCO 70 has the control input end of the output of linking phase comparator 80.Phase comparator has negative, positive input 180 and 150.The negative input end 180 of phase comparator 80 is linked the output of VCO 70 through counter 100.Sync splits device 90 is also linked the analog input end 1170 of ADC 20.According to the present invention, sync splits device 90 has the line synchronizing signal output 160 of the input of linking selector 50.Selector 50 has the control input end 130 of output of the synchronous logic part 110 of the positive input terminal 150 of linking response phase comparator 150.This selector has two outputs of the RESET input 120 of the positive input terminal 150 of linking phase comparator 80 respectively and counter 100.
Be in operation, video tape 140 is around reproducing head 30.When video tape when reproducing head 30 is pulled through, 30 rotation is so that relative pick- up 25,35 reads adjacent road on the video tape on diameter in 30 upper edges, to rebuild the vision signal on being recorded in 130 at the output of Signal Regulation amplifier 20.ADC10 takes a sample to the signal of rebuilding with the interval that clock signal is determined, and each sampling is converted to numeral.VCO70 is at sampling clock input 60 clockings of ADC10.The frequency of this clock signal is determined by the voltage level of phase comparator 80 outputs.The sampling number that requires in each line period of counter 120 usefulness removes clock signal.For example, for each row vision signal is quantized into 1000 samplings, counter should be clock signal divided by 1000.Sync splits device 90 goes out line synchronizing signal from the reconstruction video signal extraction of the analog input end 170 of ADC 10.The output of phase comparator 80 (phase error signal) is to be determined by the phase difference between the input of the counter on line synchronizing signal on the negative input end 150 and the positive input terminal 180.Thereby as long as the horizontal synchronizing pulse at negative input end 150 places is consistent with the pulsion phase of the output of counter 100, sampling clock signal just will remain unchanged.According to the present invention, detecting looking genuine during horizontal synchronizing pulse of causing by jumping such as video heads, synchronous logic part 110 makes counter reset with selector 50, to prevent the frequency of this class impulse disturbances clock signal.
Referring to Fig. 3, the most preferred embodiment of selector 50 comprises a pair of double input end AND gate 200 and 210, and the most preferred embodiment of synchronous logic part 110 comprises that one has the edge-triggered monostable circuit 220 of paraphase and non-inverted output terminals Q ' and Q.AND gate 200 and 210 all has an input to link sync splits device output 160.Another input of AND gate 200 is linked the non-inverted output terminals Q of monostable circuit 220.Another input of AND gate 210 is linked the paraphase output Q ' of monostable circuit 220.The output of AND gate 200 is linked the RESET input 100 of counter 100.The output of AND gate 210 is linked the negative input end 150 of phase comparator 80 and the triggering input of monostable circuit 220.Monostable circuit 220 is suitable for producing an output pulse when detecting the trailing edge of horizontal synchronizing pulse signal, the length of this output pulse is that be scheduled to and shorter but longer than the time interval of the lock-out pulse introducing of looking genuine than line period.
Referring to Fig. 4, track 300 is represented the part of the horizontal synchronizing pulse signal at sync splits device output 160 places.This part comprises real horizontal synchronizing pulse P1 and the P2 that is separated by line period T1 institute transient state.May have been separated one-period T2 with pulse P2 by transient state ground by the lock-out pulse that looks genuine that causes such as video heads jumps; Period T 2 is generally much smaller than line period T1.For example, to the line period T1 of 64 μ s, period T 2 is generally 5 μ s pulse PE and pulse P3 subsequently is separated out period T 1.
Track 310 and 320 is represented noninvert and the paraphase output Q and the Q ' of monostable circuit respectively.The trailing edge of pulse P1, P2 and P3 switches to metastable state period T 3 to Q and Q ' from stable state.The selection of period T 3 makes that at paraphase and noninvert output Q and Q ' spurious pulse PE takes place during in their separately metastable states.
The positive input terminal 150 of track 330 expression phase comparators.Because paraphase output Q ' is in its metastable state in period T 3, AND gate 210 is closed.Thereby spurious pulse PE does not link the input of phase comparator.Yet, when paraphase output Q ' gets back to its stable state, AND gate 210 conductings.Thereby true pulse P1, P2 and P3 are connected to the positive input terminal 150 of phase comparator.
The RESET input 120 of track 340 expression counters 100.When spurious pulse occurs in non-inverted output terminals Q and is in its metastable state.Therefore, spurious pulse PE is strobed into the RESET input 120 of counter 100 by AND gate 200.Yet when noninvert output Q got back to its stable state, AND gate 200 was closed.Thereby, the RESET input 120 that actual pulse P1P2 and P3 are not linked counter 100.
Because sync splits device output 160 is not linked the triggering input of monostable circuit 220 when monostable circuit 220 is in their separately metastable states, the trailing edge of pulse PE can't trigger monostable circuit 220 again and also prolong period T 3 effectively.But, in other embodiments of the invention, monostable circuit Once is forgivable, twice is not circuits for triggering, it triggers input and links sync splits device input 160 but not the positive input terminal 150 of phase comparator 80.
Track 350 is illustrated in the counting that is stored in the line synchronizing signal part of track 300 representatives in the counter.Each clock cycle exists the counting in the counter all to increase.When counting reaches N-L (wherein N is a desired number of samples in each line period), counter produces an output pulse, and count resets is to zero.The output of track 360 representative words number device in the represented line synchronizing signal part of track 300.In the period T of being expert at 1, be expert at synchronously towards between P1 and the P2, counting is increased to N-1 from zero.When detecting the next cycle of sampling clock pulse, count resets and counter produce output pulse C2.Because pulse C2 is consistent with the pulse P1 at phase comparator place, clock frequency remains unchanged.In time interval T3, between pulse P2 and spurious pulse PE, counting increases to a median n who is lower than N-1 from zero.Yet according to the present invention, and with reference to the description to track 330 and 340, pulse PE is drawn away the RESET input 120 of counter by the positive input terminal 80 from phase comparator.Thereby pulse PE arrives zero to count resets.Like this, among the line period T1 between pulse PE and P3, counting is increased to N-1 from zero rather than n.When detecting the following one-period of clock signal, count resets and counter produce output pulse C3.Because pulse C1, C2 and the C3 of counter output are consistent with pulse P1, P2 and the P3 at phase comparator place, though spurious pulse PE is arranged, clock frequency also remains unchanged.
As previously mentioned, the period T 2 general line period T1 that are shorter than far away.But period T 2 can prolong once in a while.Thereby in most preferred embodiment of the present invention, shown in the dotted line in track 310 and 320, be switched to their metastable cycles separately to T3 ' by prolonging Q and Q ', can improve the look genuine sensitivity of horizontal synchronizing pulse PE of 110 pairs of synchronous logic parts.The maximum that it should be noted that T3 ' equals the width that line period T1 subtracts a horizontal synchronizing pulse because if T3 ' is longer than this, then register 100 will be by real horizontal synchronizing pulse---as P1, P2 and P3 and the lock-out pulse PE that looks genuine---reset.
In the above-mentioned embodiment of the invention, regulate clock signal according to the present invention, thereby quantize the time interval of the vision signal that the conventional domestic video recorder reproduced to determine to take a sample by 10 pairs of vision signals of the A/D converter in the image processing system.According to the present invention, because clock frequency can not change by the time interval of looking genuine that the playback video tape produces, the vision signal of quantification can the transient state distortion, thereby can show on a window of the display unit of not carrying out overscanning or this class device.Yet it should be understood that the present invention is not limited only to video quantizing and uses.In other embodiments of the invention, the clock signal of regulating according to the present invention can be linked the counting logical gate of the line synchronizing signal that is used to recover the vision signal that the conventional domestic video recorder reproduced, and is not had the overscanning display unit without intermediate quantityization by direct feed-in.
Claims (10)
1. signal processing apparatus is used for handling the horizontal synchronizing pulse of the line synchronizing signal of the line period that limits analog video signal, and this device comprises:
A phase-locked loop (40) is used to produce a clock signal, and the frequency of this signal is the multiple of line synchronizing signal frequency;
Counter (100) in the above-mentioned phase-locked loop (40) is used for removing clock signal with described multiple; And
Logical gate (110,50) is used for when detecting the spurious pulse of the time interval introducing line synchronizing signal that is shorter than the vision signal line period counter (100) being resetted;
It is characterized in that: above-mentioned logical gate (110,50) comprise a multiplexer (130), be used for each horizontal synchronizing pulse of responsive trip synchronizing signal and line synchronizing signal is switched to the RESET input (120) of counter (100) and continues a reset cycle from the phase comparator input (150) of phase-locked loop (40), this cycle is shorter than line period.
2. device as claimed in claim 1, it is characterized in that: above-mentioned logical gate (110,50) comprise timer (110), be used for when the trailing edge of the horizontal synchronizing pulse that detects line synchronizing signal, the control input end of multiplexer (130) being switched to second state and continuing a reset cycle from first state.
3. device as claimed in claim 2 is characterized in that: above-mentioned timer (110) has a triggering input that links to each other with phase comparator input (150).
4. device as claimed in claim 2 is characterized in that: above-mentioned timer has an input in response to line synchronizing signal, and can not trigger in the reset cycle again.
5. device as claimed in claim 3 is characterized in that: above-mentioned timer (110) comprises an one-shot multivibrator (220).
6. device as claimed in claim 4 is characterized in that: above-mentioned timer (110) comprises an one-shot multivibrator (220).
7. device as claimed in claim 5, it is characterized in that: above-mentioned multiplexer (50) comprises a pair of AND gate (200,210), and above-mentioned one-shot multivibrator (220) has the AND gate of linking (200,210) to enable different AND gate (200 respectively, 210) paraphase and non-inverted output terminals (Q, Q ').
8. device as claimed in claim 6, it is characterized in that: above-mentioned multiplexer (50) comprises a pair of AND gate (200,210), and above-mentioned one-shot multivibrator (220) has the AND gate of linking (200,210) to enable different AND gate (200 respectively, 210) paraphase and non-inverted output terminals (Q, Q ').
9. aforementioned arbitrary device as claimed in claim is characterized in that: above-mentioned logical gate (110,50) is configured to the reset cycle roughly is set at the poor of a line period and a clock-pulse width.
10. image processing system that is used for the treatment of simulated vision signal, it is characterized in that: be used to quantize the clock signal A/D converter of the sample video of fixed time interval (10) really, and the signal processing apparatus that is used for clocking as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93100375A CN1045356C (en) | 1993-01-11 | 1993-01-11 | Signal processing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93100375A CN1045356C (en) | 1993-01-11 | 1993-01-11 | Signal processing apparatus |
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| Publication Number | Publication Date |
|---|---|
| CN1075388A CN1075388A (en) | 1993-08-18 |
| CN1045356C true CN1045356C (en) | 1999-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN93100375A Expired - Fee Related CN1045356C (en) | 1993-01-11 | 1993-01-11 | Signal processing apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100490541C (en) * | 2005-09-07 | 2009-05-20 | 宏芯科技股份有限公司 | Method for reducing phase-locked-loop shake in video-com application |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0343724A1 (en) * | 1988-05-25 | 1989-11-29 | Koninklijke Philips Electronics N.V. | Device for deriving a sampling rate |
| EP0389849A2 (en) * | 1989-03-29 | 1990-10-03 | Maschinenfabrik Rieter Ag | Control sytem for a textile machine |
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1993
- 1993-01-11 CN CN93100375A patent/CN1045356C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0343724A1 (en) * | 1988-05-25 | 1989-11-29 | Koninklijke Philips Electronics N.V. | Device for deriving a sampling rate |
| EP0389849A2 (en) * | 1989-03-29 | 1990-10-03 | Maschinenfabrik Rieter Ag | Control sytem for a textile machine |
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| CN1075388A (en) | 1993-08-18 |
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