CN104528631A - Preparation method of nanoporous structures on surfaces of silicon wafers - Google Patents
Preparation method of nanoporous structures on surfaces of silicon wafers Download PDFInfo
- Publication number
- CN104528631A CN104528631A CN201410797689.5A CN201410797689A CN104528631A CN 104528631 A CN104528631 A CN 104528631A CN 201410797689 A CN201410797689 A CN 201410797689A CN 104528631 A CN104528631 A CN 104528631A
- Authority
- CN
- China
- Prior art keywords
- etching
- silicon chip
- chip surface
- nano
- cesium chloride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a preparation method of nanoporous structures on surfaces of silicon wafers. The method comprises the following steps: preparing cesium chloride island structures on the surfaces of the silicon wafers; plating aluminum metal films on the surfaces of the silicon wafers with the cesium chloride island structures in a vacuum manner, putting the silicon wafers into deionized water to ultrasonically peel, removing the cesium chloride island structures and the aluminum metal films on the silicon wafers to obtain porous aluminum films; deeply etching the surfaces of the silicon wafers in an etching cavity of a plasma etcher by taking the porous aluminum films as masks; and removing the porous aluminum films on the surfaces of the silicon wafers to obtain the nanoporous structures on the surfaces of the silicon wafers. The nanoporous structures on the surfaces of the silicon wafers prepared by the method are distributed on the surfaces of the silicon wafers in unordered positions; the nanoporous structures are different in sizes and similar in depth, and has Gaussian distribution of diameters and unsmooth side walls.
Description
Technical field
The invention belongs to micron, Nano semiconductor micro-processing technology, especially a kind of preparation method of silicon chip surface nano-pore structure.
Background technology
In recent years, nanostructured has unique electricity, optics, catalysis and biological nature because of it, causes the great interest of the field such as nano material and micro-nano technology researcher.Nano array structure is not only subject to extensive concern at field of scientific study, and is applied in fields such as photoelectric device, magnetic recording, sensor, biological informations.Especially, silicon, as important microelectronic material, for realizing the application of silicon nano electron device, needs the method for development and silicon technology compatibility mutually to prepare silicon nano array structure, one of the study hotspot in this Nano semiconductor field just.The nanostructured of silicon chip surface is also diversified, and mainly comprise various sizes nano-pillar structure and nano-pore structure, different structure and morphologies has different application prospects in different fields.Cesium chloride nano island self-assembling technique is a kind of effective ways making random nano column array, as far back as 2000, the people such as Mino Green just start to apply cesium chloride nano island self-assembling technique at silicon chip surface and prepare cesium chloride nano island, then as mask, the method of association reaction ion etching prepares the nano column array of silicon, also has a go at the silica circular hole that tens nanometers are dark.But, also be not greater than the precedent of the pattern of the nanometer silicon pore of 1 micron at present at silicon face application cesium chloride nano island self-assembling technique preparation size hundreds of nm deep, this patent is exactly the method preparing the nano-pore structure of silicon face for application cesium chloride nano island self-assembling technique.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is the preparation method providing a kind of silicon chip surface nano-pore structure, with Simplified flowsheet, reduces costs.
(2) technical scheme
For achieving the above object, the invention provides a kind of preparation method of silicon chip surface nano-pore structure, the method comprises: step 1: prepare cesium chloride island structure at silicon chip surface; Step 2: at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure, put into deionized water for ultrasonic peel off, remove cesium chloride island structure and on aluminum metal film, obtain porous aluminum film; Step 3: with porous aluminum film for mask, carries out deep etching to silicon chip surface in the etching cavity of plasma etching machine; Step 4: the porous aluminum film removing silicon chip surface, obtains nano-pore structure at silicon chip surface.
In such scheme, silicon chip described in step 1, thickness 0.2 millimeter-0.5 millimeter, P type, resistivity is 1 Ω cm-10 Ω cm, and surface is burnishing surface or matsurface.Describedly prepare cesium chloride island structure at silicon chip surface, be adopt cesium chloride self-assembling technique to realize, the diameter of cesium chloride island structure is in 500-1500 nanometer, and thickness is 200-7000 dust.
In such scheme, at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure described in step 2, be adopt the method for thermal evaporation to realize, the thickness of aluminum metal film is 40 nanometers.
In such scheme; described in step 3 with porous aluminum film for mask carries out deep etching to silicon chip surface in the etching cavity of plasma etching machine; realize etching by alternately conversion etching gas and passivation gas to occur in vertical direction; and less for the etching of horizontal direction, sidewall is protected.Described etching gas is SF
6, passivation gas is C
4f
8, He is refrigerating gas, passivation gas C
4f
8can form fluorocarbons family macromolecule polymer in the plasma, this fluorocarbons family macromolecule polymer deposits stops the reaction of fluorine ion and silicon at silicon face.
In such scheme, described alternately conversion etching gas and passivation gas, specifically comprise: etching and passivation change one-period in every 5 to 15 seconds, at once by etched silicon face passivation after of short duration isotropic etching; Bombard owing to there being the physical sputtering of ion at depth direction, passivating film is stripped, and chemical reaction ion etching can be occurred further; But sidewall direction can not be subject to Ions Bombardment, and passivating film remains, would not there is side direction etching in the etching of such next cycle; By such periodicity " etching-passivation-etching ", etching is only carried out along depth direction, and the degree of depth needed for etching can be controlled by etching period number.
In such scheme, described in step 4, remove the porous aluminum film of silicon chip surface, be adopt mass fraction be 5% sodium hydroxide solution realize.
(3) beneficial effect
The preparation method of silicon chip surface nano-pore structure provided by the invention, vacuum cesium chloride plated film, cesium chloride self assembly, vacuum thermal evaporation plated film, lift-off technology and plasma deep etching technique is adopted to complete, the silicon chip surface nano-pore structure utilizing the present invention to prepare, position is distributed in silicon chip surface disorderly, nano-pore structure varies in size, diameter is Gaussian Profile, and the degree of depth is close, and sidewall is unsmooth.
Accompanying drawing explanation
Fig. 1 is the method flow diagram preparing silicon chip surface nano-pore structure provided by the invention.
Fig. 2 to Fig. 7 is the process chart preparing silicon chip surface nano-pore structure according to the embodiment of the present invention.
Fig. 8 is the SEM plane of the silicon chip surface nano-pore structure according to the embodiment of the present invention.
Fig. 9 is the SEM vertical cross-section diagram of the silicon chip surface nano-pore structure according to the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of preparation method of silicon chip surface nano-pore structure, the method adopts vacuum cesium chloride plated film, cesium chloride self assembly, vacuum thermal evaporation plated film, lift-off technology and plasma deep etching technique to complete.First cesium chloride Nano Islands Lithography is utilized to complete original cesium chloride nano island structure, then thermal evaporation techniques is utilized to be the aluminum metal layer of 40 nanometers in cesium chloride nano island surface evaporation a layer thickness, the aluminium on cesium chloride surface is peeled off again with lift-off technology, the porous membrane structure of aluminium is obtained at silicon chip surface, then utilize reactive ion deep etching technology that pore structure is transferred to silicon materials surface, finally remove the porous aluminum film on surface with the sodium hydroxide solution of dilution, so far complete the preparation of nano-pore structure at silicon face.
As shown in Figure 1, Fig. 1 is the method flow diagram preparing silicon chip surface nano-pore structure provided by the invention, and the method comprises the following steps:
Step 1: prepare cesium chloride island structure at silicon chip surface;
In this step, silicon wafer thickness 0.2 millimeter-0.5 millimeter, P type, resistivity is 1 Ω cm-10 Ω cm, and surface is burnishing surface or matsurface.Describedly prepare cesium chloride island structure at silicon chip surface, be adopt cesium chloride self-assembling technique to realize, the diameter of cesium chloride island structure is in 500-1500 nanometer, and thickness is 200 dust-7000 dusts.
Step 2: at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure, put into deionized water for ultrasonic to peel off, remove cesium chloride island structure and on aluminum metal film, obtain porous aluminum film, namely the upset that this layer of porous aluminium achieves figure makes originally to come out by the part of cesium chloride protection, and the resistance to quarter property of aluminium mask to dry etching is better than cesium chloride mask;
In this step, at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure, be adopt the method for thermal evaporation to realize, the thickness of aluminum metal film is 40 nanometers.
Step 3: with porous aluminum film for mask, in the etching cavity of plasma etching machine, deep etching is carried out to silicon chip surface, very serious with the lithographic method undercutting of routine, be not suitable for the pore structure doing nanoscale, aluminium nano-pore mask prepared by application cesium chloride nano island technology, can only combine with deep etching, the transfer of figure could be realized, make silicon nano hole structure, also just because of this deep etching method just makes the sidewall of nano-pore smooth not, occur periodic pattern;
In this step; with porous aluminum film for mask carries out deep etching to silicon chip surface in the etching cavity of plasma etching machine; realize etching by alternately conversion etching gas and passivation gas to occur in vertical direction, and less for the etching of horizontal direction, and sidewall is protected.Etching gas is SF
6, passivation gas is C
4f
8, He is refrigerating gas, passivation gas C
4f
8can form fluorocarbons family macromolecule polymer in the plasma, this fluorocarbons family macromolecule polymer deposits stops the reaction of fluorine ion and silicon at silicon face.Etching and passivation change one-period in every 5 to 15 seconds, at once by etched silicon face passivation after of short duration isotropic etching; Bombard owing to there being the physical sputtering of ion at depth direction, passivating film is stripped, and chemical reaction ion etching can be occurred further; But sidewall direction can not be subject to Ions Bombardment, and passivating film remains, would not there is side direction etching in the etching of such next cycle; By such periodicity " etching-passivation-etching ", etching is only carried out along depth direction, and the degree of depth needed for etching can be controlled by etching period number.
Step 4: the porous aluminum film removing silicon chip surface, obtains nano-pore structure at silicon chip surface;
In this step, remove the porous aluminum film of silicon chip surface, be adopt mass fraction be 5% sodium hydroxide solution realize.
Based on the method flow diagram preparing silicon chip surface nano-pore structure shown in Fig. 1, Fig. 2 to Fig. 7 is the process chart preparing silicon chip surface nano-pore structure according to the embodiment of the present invention, have employed cesium chloride nano island self-assembling technique and micro-machined stripping and plasma deep etching technology in the present embodiment to complete the preparation of silicon face nano-pore structure, the method comprises the following steps:
As shown in Figure 2, after Wafer Cleaning is clean, put into vacuum coating cavity, evaporation cesium chloride film, thickness 200 dust-7000 dust.The silicon chip that silicon chip selects semi-conductor industry to use, thickness 0.2 millimeter-0.5 millimeter, P type, resistivity is 1 Ω cm-10 Ω cm, and surface is burnishing surface or matsurface.
As shown in Figure 3, after cesium chloride film has plated, in cavity, pass into the gas of certain humidity, relative humidity is 10%-70%, development cesium chloride film, cesium chloride is reunited under the effect of humidity gas, forms the nanometer cesium chloride peninsular structure of similar water droplet one by one at silicon chip surface.
As shown in Figure 4, because cesium chloride nano island structure is obtained by self assembly, the cesium chloride island diameter grown is not identical, and have wider diameter size distribution, diameter dimension roughly meets Gaussian Profile.By the method for vacuum thermal evaporation, evaporate at the silicon chip surface with cesium chloride nano island the aluminum metal film that one deck content is 99.99%, the thickness of film is approximately 40 nanometers.
As shown in Figure 5, the silicon chip having plated aluminium film is put into deionized water, ultrasonic stripping, due to the characteristic that cesium chloride is soluble in water, the aluminium on cesium chloride surface departs from silicon chip surface, and directly evaporate at the aluminium of silicon face intact, so just prepare the aluminum metal porous membrane of 40 nanometer thickness at silicon chip surface, the average diameter in hole can control between 400 nanometers are to 1.5 microns, at same silicon chip surface, hole has wider diameter size distribution, and diameter dimension roughly meets Gaussian Profile.
As shown in Figure 6; with this layer of porous aluminium for mask; plasma deep etching is carried out to silicon chip; plasma etch process is by F ion and is exposed to outer pasc reaction and is fallen by silicon etching; there is borehole structure; and remain intact at the position silicon face of aluminium film protection, realize the Graphic transitions of pore structure.Plasma deep etching is to ensure that etching occurs in vertical direction, and less for the etching of horizontal direction, and sidewall is protected, and it is by alternately conversion etching gas and passivation gas realize etching and limit wall passivation.Wherein etching gas is SF
6, passivation gas is C
4f
8, He is refrigerating gas.C
4f
8can form fluorocarbons family macromolecule polymer in the plasma, it is deposited on the reaction that silicon face can stop fluorine ion and silicon.Etching and passivation change one-period in every 5 to 15 seconds.At once by just etched silicon face passivation after of short duration isotropic etching.Bombard owing to there being the physical sputtering of ion at depth direction, passivating film is stripped, and chemical reaction ion etching can be occurred further.But sidewall direction can not be subject to Ions Bombardment, passivating film can remain, and side direction etching would not occur the etching of such next cycle.By such periodicity " etching-passivation-etching ", etching is only carried out along depth direction, and the required degree of depth can be controlled by etching period number, as shown in Figure 5.
Finally, silicon chip later for deep etching is put into the alkaline solution of sodium hydroxide that mass fraction is 5%, the porous aluminium lamination of surperficial 40 nanometer thickness will be corroded, and so far completes the preparation of silicon chip surface nano-pore structure, as shown in Figure 7.
Fig. 8 is that the SEM of silicon chip surface nano-pore structure schemes (plane), and Fig. 9 is SEM figure (vertical cross-section) of silicon chip surface nano-pore structure.
Embodiment
Be below the process chart preparing silicon chip surface nano-pore structure of the embodiment of the present invention, the method comprises the following steps:
Step 1: with the method evaporation cesium chloride film of thermal evaporation on silicon chip, film thickness 300 nanometer, thickness is measured by quartz crystal calibrator and controlled.
Step 2: the silicon chip being coated with cesium chloride film is put into the ventilation cavity that humidity is 50%, humidity is by the wet gas flow-control passing into cavity, develop 1 hour under this damp condition, make cesium chloride film be agglomerated into nano island structure, form cesium chloride nano island structure at silicon chip surface.Cesium chloride nano island average diameter 600 nanometer.
Step 3: had on surface the silicon chip of cesium chloride nano island structure to put into vacuum coating equipment cavity, evaporation source to be purity be 99.99% aluminium wire, the film thickness of evaporation is 40 nanometers.
Step 4: put into deionized water by after silicon chip extracting, ultrasonic stripping, 5 minutes time, makes the aluminium on cesium chloride nano island depart from, and the aluminium of silicon face keeps coherent condition, obtains at silicon chip surface the porous aluminum film that average diameter is 600 nanometers.
Step 5: the etching cavity being had on surface the silicon chip of nanoporous aluminium film to put into plasma etching machine carries out deep etching, etching condition is SF
6: He=60: 10sccm, exciting power 400 watts, substrate bias power is 30 watts, pressure 3.5 handkerchief, etch period 8 seconds.Passivating conditions is C
4f
8: He=150: 10sccm, exciting power 400 watts, substrate bias power is 0 watt, pressure 4 handkerchief, passivation time 10 seconds.Etch 10 cycles.
Step 6: will the sodium hydroxide solution that volume fraction is 5% be put into, 10 minutes, the porous aluminium of surperficial 40 nanometer thickness will be corroded, and obtains nano-pore structure at silicon chip surface, clean by washed with de-ionized water, so far complete the preparation of silicon chip surface nano-pore structure.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a preparation method for silicon chip surface nano-pore structure, is characterized in that, the method comprises:
Step 1: prepare cesium chloride island structure at silicon chip surface;
Step 2: at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure, put into deionized water for ultrasonic peel off, remove cesium chloride island structure and on aluminum metal film, obtain porous aluminum film;
Step 3: with porous aluminum film for mask, carries out deep etching to silicon chip surface in the etching cavity of plasma etching machine;
Step 4: the porous aluminum film removing silicon chip surface, obtains nano-pore structure at silicon chip surface.
2. the preparation method of silicon chip surface nano-pore structure according to claim 1, is characterized in that, silicon chip described in step 1, thickness 0.2 millimeter-0.5 millimeter, P type, and resistivity is 1 Ω cm-10 Ω cm, and surface is burnishing surface or matsurface.
3. the preparation method of silicon chip surface nano-pore structure according to claim 1, it is characterized in that, prepare cesium chloride island structure described in step 1 at silicon chip surface, is adopt cesium chloride self-assembling technique to realize, the diameter of cesium chloride island structure is in 500-1500 nanometer, and thickness is 200-7000 dust.
4. the preparation method of silicon chip surface nano-pore structure according to claim 1, it is characterized in that, at the silicon chip surface evaporation one deck aluminum metal film with cesium chloride nano island structure described in step 2, be adopt the method for thermal evaporation to realize, the thickness of aluminum metal film is 40 nanometers.
5. the preparation method of silicon chip surface nano-pore structure according to claim 1; it is characterized in that; described in step 3 with porous aluminum film for mask carries out deep etching to silicon chip surface in the etching cavity of plasma etching machine; realize etching by alternately conversion etching gas and passivation gas to occur in vertical direction; and less for the etching of horizontal direction, sidewall is protected.
6. the preparation method of silicon chip surface nano-pore structure according to claim 5, is characterized in that, described etching gas is SF
6, passivation gas is C
4f
8, He is refrigerating gas, passivation gas C
4f
8can form fluorocarbons family macromolecule polymer in the plasma, this fluorocarbons family macromolecule polymer deposits stops the reaction of fluorine ion and silicon at silicon face.
7. the preparation method of silicon chip surface nano-pore structure according to claim 5, is characterized in that, described alternately conversion etching gas and passivation gas, specifically comprise:
Etching and passivation change one-period in every 5 to 15 seconds, at once by etched silicon face passivation after of short duration isotropic etching; Bombard owing to there being the physical sputtering of ion at depth direction, passivating film is stripped, and chemical reaction ion etching can be occurred further; But sidewall direction can not be subject to Ions Bombardment, and passivating film remains, would not there is side direction etching in the etching of such next cycle; By such periodicity " etching-passivation-etching ", etching is only carried out along depth direction, and the degree of depth needed for etching can be controlled by etching period number.
8. the preparation method of silicon chip surface nano-pore structure according to claim 1, is characterized in that, removes the porous aluminum film of silicon chip surface described in step 4, be adopt mass fraction be 5% sodium hydroxide solution realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797689.5A CN104528631A (en) | 2014-12-18 | 2014-12-18 | Preparation method of nanoporous structures on surfaces of silicon wafers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797689.5A CN104528631A (en) | 2014-12-18 | 2014-12-18 | Preparation method of nanoporous structures on surfaces of silicon wafers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104528631A true CN104528631A (en) | 2015-04-22 |
Family
ID=52844329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410797689.5A Pending CN104528631A (en) | 2014-12-18 | 2014-12-18 | Preparation method of nanoporous structures on surfaces of silicon wafers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104528631A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104986725A (en) * | 2015-07-15 | 2015-10-21 | 桂林电子科技大学 | Periodic bowl-shaped structural template and preparation method thereof |
| CN109994576A (en) * | 2018-01-02 | 2019-07-09 | 山东浪潮华光光电子股份有限公司 | A kind of GaAs base LED die production method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101117726A (en) * | 2006-07-31 | 2008-02-06 | 国家纳米技术与工程研究院 | Composite nano hole mask plate based on aluminium anodized film and preparation method and application thereof |
| KR20110094261A (en) * | 2011-08-02 | 2011-08-23 | 강원대학교산학협력단 | Forming method of nano structure using the metal nano ring pattern |
| CN102683518A (en) * | 2012-05-30 | 2012-09-19 | 中国科学院半导体研究所 | Preparation method for nanopore-shaped patterned sapphire substrate |
| CN102683522A (en) * | 2012-06-04 | 2012-09-19 | 中国科学院半导体研究所 | Manufacture method of light-emitting diode with air bridge structure |
| CN103030096A (en) * | 2011-10-09 | 2013-04-10 | 中国科学院高能物理研究所 | Silicon material with nano-structure surface and manufacturing method thereof |
-
2014
- 2014-12-18 CN CN201410797689.5A patent/CN104528631A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101117726A (en) * | 2006-07-31 | 2008-02-06 | 国家纳米技术与工程研究院 | Composite nano hole mask plate based on aluminium anodized film and preparation method and application thereof |
| KR20110094261A (en) * | 2011-08-02 | 2011-08-23 | 강원대학교산학협력단 | Forming method of nano structure using the metal nano ring pattern |
| CN103030096A (en) * | 2011-10-09 | 2013-04-10 | 中国科学院高能物理研究所 | Silicon material with nano-structure surface and manufacturing method thereof |
| CN102683518A (en) * | 2012-05-30 | 2012-09-19 | 中国科学院半导体研究所 | Preparation method for nanopore-shaped patterned sapphire substrate |
| CN102683522A (en) * | 2012-06-04 | 2012-09-19 | 中国科学院半导体研究所 | Manufacture method of light-emitting diode with air bridge structure |
Non-Patent Citations (1)
| Title |
|---|
| JING LIU, ET AL.: "Fabrication and antireflection properties of solar cells with pyramid-nanohole texture by caesium chloride lithography", 《JOURNAL OF PHYSICS D: APPLIED PHYSICS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104986725A (en) * | 2015-07-15 | 2015-10-21 | 桂林电子科技大学 | Periodic bowl-shaped structural template and preparation method thereof |
| CN109994576A (en) * | 2018-01-02 | 2019-07-09 | 山东浪潮华光光电子股份有限公司 | A kind of GaAs base LED die production method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6392866B2 (en) | Surface texture structure of crystalline silicon solar cell and manufacturing method thereof | |
| TWI472477B (en) | Silicon nanostructures and method for producing the same and application thereof | |
| JP5690348B2 (en) | Microstructuring of the surface of a light-absorbing substrate | |
| CN105776125A (en) | Wedge-shaped patterned super-wettability surface and preparation method thereof | |
| CN103199161B (en) | A kind of method preparing cone structure on GaP surface | |
| TW201126744A (en) | Methods of texturing surfaces for controlled reflection | |
| Yamada et al. | Fabrication of arrays of tapered silicon micro-/nano-pillars by metal-assisted chemical etching and anisotropic wet etching | |
| CN105293427A (en) | Preparation method of super-hydrophobic surface based on limited local plating of meniscus | |
| CN102701141A (en) | Method for manufacturing high depth-to-width ratio micro-nano composite structure | |
| CN103112819A (en) | Preparation method for orderly silicon nanowire array | |
| CN103809376A (en) | Inorganic phase change photoresist and photolithographic technology based on inorganic phase change photoresist | |
| CN111071985A (en) | Method for securing metal nanoparticles with an anodized aluminum film incorporating a sacrificial layer | |
| CN103979485A (en) | Preparation method of micro nano porous silicon material | |
| CN103646876A (en) | SiC etching method of steep smooth side wall morphology | |
| CN105967139A (en) | Method for etching holes on silicon substrate, silicon substrate with holes and semiconductor device | |
| CN104528631A (en) | Preparation method of nanoporous structures on surfaces of silicon wafers | |
| CN106185792A (en) | A kind of population parameter controllable method for preparing of super-hydrophobic micro-nano compound structure | |
| CN103030096A (en) | Silicon material with nano-structure surface and manufacturing method thereof | |
| CN102856165A (en) | Method for simply preparing ordered V-shaped nanometer silicon pore array | |
| CN102856434B (en) | Preparation method for square silicon nano-porous array | |
| CN104538283A (en) | Preparation method for inverted pyramid structure on silicon wafer surface | |
| CN101759143A (en) | Method for controlling growth of micro-nano pore structure on silicon surface | |
| CN109103301B (en) | Preparation method of polycrystalline silicon surface micro-nano composite structure | |
| US8945794B2 (en) | Process for forming silver films on silicon | |
| CN206282822U (en) | A kind of mercury cadmium telluride etch mask for automatically controlling shaping terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150422 |