CN104517571B - Phase inverter and drive circuit, display panel, display device - Google Patents
Phase inverter and drive circuit, display panel, display device Download PDFInfo
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- CN104517571B CN104517571B CN201410784273.XA CN201410784273A CN104517571B CN 104517571 B CN104517571 B CN 104517571B CN 201410784273 A CN201410784273 A CN 201410784273A CN 104517571 B CN104517571 B CN 104517571B
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Abstract
The preferred embodiment of the present invention provides a kind of phase inverter and its drive circuit, display panel, display device, and phase inverter includes the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity and the second electric capacity；Transistor seconds is connected in equivalent diode form, can only one-way conduction, the second electric capacity keeps the current potential stabilization of output end so that the influence of the signal of output end not subject clock signal, namely the signal of inverter output output will not be shaken.And in phase inverter whole work process, output end has the 6th transistor to transmit the first level signal or the 7th transistor transmission second electrical level signal so that the signal of output end output will not be hanging, and output is more stablized.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of phase inverter and drive circuit, display panel, display dress
Put.
Background technology
Phase inverter has acting in opposition to the initial signal for being input into it, it may also be said to, output signal and the starting of phase inverter
Signal inversion signal each other.With the development of electronic technology, also more and more extensively, for example phase inverter can be answered for the application of phase inverter
Used in the launch driving circuit of organic light-emitting display device, for the pixel compensation circuit electrically connected with launch driving circuit provides phase
The current potential answered is so that pixel compensation circuit completes node initializing, valve value compensation and data write-in etc..
The content of the invention
The preferred embodiment of the present invention provides a kind of output signal more stable phase inverter, and the driving comprising the phase inverter
Circuit, display panel, display device.
On the one hand, the preferred embodiment of the present invention provides a kind of phase inverter, including：The first transistor, transistor seconds, the 3rd
Transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity and the second electric capacity；
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end coupling is used
In the first level signal input for receiving the first level signal, the second end coupling Section Point；
When the first end of the transistor seconds is by first electric capacity and for receive the first clock signal first
Clock signal input part is coupled, and grid and the first end of the transistor seconds are coupled, and the second end is coupled to Section Point；
The grid of the third transistor couples the second clock signal input part for receiving second clock signal, second
The first end of the end coupling transistor seconds, first end couples the second electrical level signal input for receiving second electrical level signal
End；
The grid of the 4th transistor is coupled to Section Point, and first end is coupled to the first level signal input
End, the second end is coupled to the first node；
The grid of the 5th transistor is coupled to the initial signal input, and first end is coupled to the second electrical level
Signal input part, the second end is coupled to first node；
The grid of the 6th transistor couples the first node, and first end couples the first level signal input
End, the second end couples the output end of phase inverter；
The grid of the 7th transistor is coupled to Section Point, and first end couples the second electrical level signal input part,
Second end couples the output end of phase inverter；
Second electric capacity is coupled between the Section Point and output end.
On the other hand, the preferred embodiment of the present invention also provides a kind of phase inverter, including the first transistor, transistor seconds,
Third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the first electric capacity and the second electric capacity；
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end coupling is used
In the first level signal input for receiving the first level signal, the second end coupling Section Point；
When the first end of the transistor seconds is by first electric capacity and for receive the first clock signal first
Clock signal input part is coupled, and grid and the first end of the transistor seconds are coupled, and the second end is coupled to Section Point；
The grid coupling Section Point of the third transistor, the second end couples the first end of the transistor seconds, the
One end couples the second electrical level signal input part for receiving second electrical level signal；
The grid of the 4th transistor is coupled to Section Point, and first end is coupled to the first level signal input
End, the second end is coupled to the first node；
The grid of the 5th transistor is coupled to the initial signal input, and first end is coupled to the second electrical level
Signal input part, the second end is coupled to first node；
The grid of the 6th transistor couples the first node, and first end couples the first level signal input
End, the second end couples the output end of phase inverter；
The grid of the 7th transistor is coupled to Section Point, and first end couples the second electrical level signal input part,
Second end couples the output end of phase inverter；
Second electric capacity is coupled between the Section Point and output end.
On the other hand, the preferred embodiment of the present invention also provides a kind of drive circuit, including above-mentioned phase inverter.
On the other hand, the preferred embodiment of the present invention also provides a kind of display panel, including above-mentioned drive circuit.
On the other hand, the preferred embodiment of the present invention also provides a kind of display device, including above-mentioned display panel.
What the phase inverter and drive circuit, display panel, display device that the preferred embodiment of the present invention is provided at least had has
Beneficial effect：The signal of inverter output output will not be shaken, and be not in during operation hanging output so that output is more
Plus stabilization.
Brief description of the drawings
Fig. 1 is the inverter circuit schematic diagram of prior art；
Fig. 2 is each signal timing diagram of phase inverter in Fig. 1；
Fig. 3 is the inverter circuit schematic diagram that the preferred embodiment of the present invention one is provided；
Fig. 4 is each signal timing diagram of phase inverter in Fig. 3；
Fig. 5 a~Fig. 5 d are the corresponding circuit diagrams of each working stage of phase inverter in Fig. 4；
Fig. 6 is the inverter circuit schematic diagram that the preferred embodiment of the present invention two is provided；
Fig. 7 is a kind of drive signal timing diagram of phase inverter in Fig. 6；
Fig. 8 a~Fig. 8 d are the corresponding circuit diagrams of each working stage of phase inverter in Fig. 7；
Fig. 9 is another drive signal timing diagram of phase inverter in Fig. 6；
Figure 10 a~Figure 10 d are the corresponding circuit diagrams of each working stage of phase inverter in Fig. 9；
Figure 11 is the drive circuit connection diagram that the preferred embodiment of the present invention three is provided；
Figure 12 is a kind of structural representation of display panel that the preferred embodiment of the present invention four is provided；
Figure 13 is the structural representation of second substrate in Figure 12；
Figure 14 is the display device structure schematic diagram that the preferred embodiment of the present invention five is provided.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention is illustrate only in description, accompanying drawing and not all.
Fig. 1 is the circuit diagram of the phase inverter of prior art.As shown in figure 1, phase inverter includes the first transistor P1, the second crystalline substance
Body pipe P2, third transistor P3, the 4th transistor P4 and electric capacity C0, wherein, the transistor P4 of the first transistor P1 to the 4th are equal
It is PMOS；The grid of the first transistor P1 electrically connect with the initial signal input IN0 for receiving initial signal, source electrode and
The first level signal input VG1 electrical connections for receiving the first level signal, drain electrode by electric capacity C0 with for receiving the
The first clock signal input terminal electrical connection of one clock signal；The grid of transistor seconds P2 with for receiving second clock signal
Second clock signal input part XCK electrical connection, source electrode respectively with the first transistor P1 drain electrode and the 4th transistor P4 grid
Pole is electrically connected, and drain electrode is electrically connected with for receiving the second electrical level signal input part VG2 of second electrical level signal；Third transistor P3
Grid is electrically connected with initial signal input IN0, and source electrode is electrically connected with the first level signal input VG1, is drained and is used to produce
The output end OUT0 electrical connections of raw output signal；The source electrode of the 4th transistor P4 is electrically connected with output end OUT0, drain electrode and second
Level signal input VG2 is electrically connected.Wherein, the first level signal is constant high level signal, and second electrical level signal is perseverance
Fixed low level signal.
Fig. 2 is the oscillogram of each signal of the phase inverter in Fig. 1.As Fig. 2 shows that SIN0 represents initial signal, SCK1 generations
The clock signal of table first, SXCK represents second clock signal, and SOUT0 represents output signal.Due to the first clock signal SCK1 by
When low level becomes high level, by the bootstrap effect (charge conservation of electric capacity C0) of electric capacity C0, can be to the 4th transistor P4
The current potential of grid produces influence, and influences the conducting situation of the 4th transistor P4, so as to influence second electrical level signal to pass through the 4th
Transistor P4 is transferred to output end OUT, and produces influence to the low level level value of output signal SOUT0, and then causes defeated
Go out the unstable of signal.
Embodiment one
The embodiment of the present invention one provides a kind of phase inverter, as shown in figure 3, phase inverter includes the first transistor M1, the second crystalline substance
Body pipe M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, first
Electric capacity C1 and the second electric capacity C2.
Wherein, the grid of the first transistor M1 couples the initial signal input IN for receiving initial signal, first end
Couple the first level signal input VGH for receiving the first level signal！, the second end couples Section Point N2；Second is brilliant
The first end of body pipe M2 is by the first electric capacity C1 and the first clock signal input terminal CK for receiving the first clock signal
Coupling, grid and the first end of the transistor seconds M2 are coupled, and the second end is coupled to Section Point N2；Third transistor M3's
Grid couples the second clock signal input part XCK for receiving second clock signal, and the second end couples the transistor seconds
The first end of M2, first end couples the second electrical level signal input part VGL for receiving second electrical level signal！；4th transistor
The grid of M4 is coupled to Section Point N2, and first end is coupled to the first level signal input VGH！, the second end is coupled to
First node N1；The grid of the 5th transistor M5 is coupled to initial signal input IN, and first end is coupled to the second electrical level
Signal input part VGL！, the second end is coupled to first node N1；The grid of the 6th transistor M6 couples the first node N1, the
One end couples the first level signal input VGH！, the second end couples the output end OUT of phase inverter；7th transistor M7's
Grid is coupled to Section Point N2, and first end couples the second electrical level signal input part VGL！, the second end coupling phase inverter
Output end OUT；Second electric capacity C2 is coupled between the Section Point N2 and inverter output OUT.
The grid of transistor seconds M2 is electrically connected with first end so that transistor seconds is equivalent to diode, can only be unidirectional
Conducting, the second electric capacity C2 is coupled between Section Point N2 and inverter output out, the electricity for keeping Section Point N2
Position.
Further, the first transistor M1, transistor seconds M2, third transistor in the phase inverter that embodiment one is provided
M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 can be PMOS, or
NMOS tube.Preferably, wherein first clock signal and second clock signal input part of the first clock signal input terminal CK inputs
The second clock signal of XCK inputs is pulse signal, and anti-phase each other；When described the first transistor M1, transistor seconds M2,
When third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 are PMOS,
The first level signal input VGH！First level signal of input is constant high level, second electrical level input VGL！
The second electrical level signal of input is constant low level, when the first transistor M1, transistor seconds M2, third transistor M3,
When four transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 are NMOS tube, the first level letter
Number input VGH！First level signal of input is constant low level, second electrical level input VGL！The second electrical level of input
Signal is constant high level.When actually used, initial signal, output signal, the first clock signal and second clock signal
The level value of high level can select the 10V, low level level value can to select -5V, it is also possible to kind of design according to transistor and
It is actually needed and is set.Specification is needed, for PMOS, the first end of transistor refers to source electrode, the second end
Refer to drain electrode.And for NMOS tube, the first end of transistor refers to drain electrode, the second end refers to source electrode.
Fig. 4 show a kind of preferred working timing figure of the phase inverter of the offer of embodiment one, and it is first crystal that its is corresponding
Pipe M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th crystalline substance
Body pipe M7 is PMOS, the first level signal input VGH！First level signal of input is constant high level, second
Level input VGL！The second electrical level signal of input is constant low level.
Four working stages of the T1~T4 moment correspondence inverter circuit of embodiment one in Fig. 4, respectively such as Fig. 5 a~5d
It is shown.Describe the course of work of the phase inverter of embodiment one in detail with reference to Fig. 4 and Fig. 5 a~5d：
Fig. 5 a are the circuit diagram of the first stage of inverters work, i.e. T1 periods, and initial signal IN is high level, control the
One transistor M1 and the 5th transistor M5 is closed, and second clock signal XCK is low level, and control third transistor M3 is opened, the
Two level signal VGL！Transmitted to transistor seconds M2 source electrodes through third transistor M3, due to the source electrode and grid of transistor seconds
Connected with diode, therefore transistor seconds M2 is turned on, and transmission second electrical level signal VGL！To Section Point N2.Second
The current potential of node N2 is low level, controls the 4th transistor M4 and the 7th transistor M7 to open respectively, the 4th transistor M4 transmission
First level signal VGH of high level！To first node N1, the 6th transistor is then controlled to close.7th transistor M7 is transmitted
Second electrical level signal VGL！To the output end OUT of phase inverter, as the output signal of first stage.
Fig. 5 b are the circuit diagram of the second stage of inverters work, namely T2 periods, second clock signal XCK is electricity high
Flat, control third transistor M3 is closed, and initial signal IN is low level, and control the first transistor M1 and the 5th transistor M5 is opened
Open, the first level signal VGH of high level！Transmitted to Section Point N2 by the first transistor M1 so that Section Point N2 is
High level, the 4th transistor M4 of control and the 7th transistor M7 is closed, herein it should be noted that, although the first clock signal CK
Low level is changed into by high level, by the coupling of the first electric capacity C1, the grid potential of transistor seconds M2 can be dragged down, and
Transmit to Section Point N2, because this process is of short duration coupling effect, and the first transistor M1 transmits constant high level
VGH！To Section Point N2, therefore current potential influences of the transistor seconds M2 on Section Point is limited, the current potential of Section Point N2 according to
It is so high level.Low level second electrical level signal VGL！Transmitted to first node N1, control the 6th by the 5th transistor M5
Transistor M6 is opened, and the 6th transistor M6 transmits the first level signal VGH！To the output end of phase inverter, as the second work rank
The output signal of section；
Fig. 5 c are the circuit diagram of the phase III of inverters work, namely T3 periods, initial signal IN is high level, control
The first transistor M1 and the 5th transistor M5 is closed, and second clock signal XCK is low level, and control third transistor M3 is opened,
Second electrical level signal VGL！Transmitted to transistor seconds M2 source electrodes through third transistor M3, due to the source electrode and grid of transistor seconds
Pole is connected with diode, therefore transistor seconds M2 is turned on, and transmission second electrical level signal VGL！To Section Point N2.The
The current potential of two node N2 is low level, controls the 4th transistor M4 and the 7th transistor M7 to open respectively, and the 4th transistor M4 is passed
First level signal VGH of defeated high level！To first node N1, the 6th transistor is then controlled to close.7th transistor M7 is passed
Defeated second electrical level signal VGL！To the output end OUT of phase inverter, as the output signal of first stage.
Fig. 5 d are the circuit diagram of the fourth stage of inverters work, namely T4 moment, initial signal IN control first crystals
Pipe M1 and the 5th transistor M5 is closed, and second clock signal XCK control third transistor M3 is closed, and the first clock signal CK is by height
Level is changed into low level, by the coupling of the first electric capacity C1, drags down the grid potential of transistor seconds M2, due to the second crystalline substance
Body pipe is equivalent to diode, now transistor seconds M2 conductings, and then transmission grid potential is distinguished to Section Point N2
The 4th transistor M4 and the 7th transistor M7 is controlled to open, the 4th transistor M4 transmits the first level signal VGH！To first node
N1, the 6th transistor of control is closed, the 7th transistor M7 transmission second electrical level signals VGL！To the output end out of phase inverter, make
It is the output signal in the stage.
From the above course of work, there is the second electric capacity, can keep second in Section Point N2 with inverter output
Node and the current potential stabilization of output end, are not influenceed so that phase inverter is defeated by the first clock signal or second clock signal saltus step
The signal for going out to hold OUT to export will not be shaken.And in whole work process, each stage, output end OUT has the 6th transistor M6 to pass
Defeated first level signal VGH！Or the 7th transistor M7 transmission second electrical level signal VGL！So that the signal of output end output is not
Can be hanging, output is more stablized.
It should be noted that the first transistor~the 7th transistor in the phase inverter of the offer of embodiment one can be NMOS
Pipe, in its course of work, only needs initial signal, the first clock signal, second clock signal, the first level signal, second electrical level
Signal is opposite with above-mentioned level value.
Embodiment two
Fig. 6 show another inverter circuit figure of the offer of the preferred embodiment of the present invention two, as shown in fig. 6, phase inverter
Including the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th crystal
Pipe M6, the 7th transistor M7, the first electric capacity C1 and the second electric capacity C2.
Wherein, the grid of the first transistor M1 couples the initial signal input IN for receiving initial signal, first end
Couple the first level signal input VGH for receiving the first level signal！, the second end couples Section Point N2；Second is brilliant
The first end of body pipe M2 is by the first electric capacity C1 and the first clock signal input terminal CK for receiving the first clock signal
Coupling, grid and the first end of the transistor seconds M2 are coupled, and the second end is coupled to Section Point N2；Third transistor M3's
Grid couples Section Point N2, and the second end couples the first end of the transistor seconds M2, and first end is coupled for receiving second
The second electrical level signal input part VGL of level signal！；The grid of the 4th transistor M4 is coupled to Section Point N2, first end coupling
It is connected to the first level signal input VGH！, the second end is coupled to first node N1；The grid coupling of the 5th transistor M5
In initial signal input IN, first end is coupled to the second electrical level signal input part VGL！, the second end is coupled to first segment
Point N1；The grid of the 6th transistor M6 couples the first node N1, and first end couples the first level signal input
VGH！, the second end couples the output end OUT of phase inverter；The grid of the 7th transistor M7 is coupled to Section Point N2, first end coupling
Meet the second electrical level signal input part VGL！, the second end couples the output end OUT of phase inverter；Second electric capacity C2 is coupled to described
Between Section Point N2 and inverter output OUT.
The grid of transistor seconds M2 is electrically connected with first end so that transistor seconds is equivalent to diode, can only be unidirectional
Conducting, the second electric capacity C2 is coupled between Section Point N2 and inverter output out, the electricity for keeping Section Point N2
Position.
Further, the first transistor M1, transistor seconds M2, third transistor in the phase inverter that embodiment two is provided
M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 can be PMOS, or
NMOS tube.When described the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor
When M5, the 6th transistor M6, the 7th transistor M7 are PMOS, the first level signal input VGH！The first of input
Level signal is constant high level, second electrical level input VGL！The second electrical level signal of input is constant low level, when
The first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor
When M6, the 7th transistor M7 are NMOS tube, the first level signal input VGH！First level signal of input is perseverance
Fixed low level, second electrical level input VGL！The second electrical level signal of input is constant high level.When actually used, starting
Signal, output signal, the level value of the high level of the first clock signal can select the 10V, low level level value can to select -5V,
Can also be set according to the kind of design of transistor and being actually needed.Specification is needed, for PMOS, crystal
The first end of pipe refers to source electrode, and the second end refers to drain electrode.And for NMOS tube, the first end of transistor is referred to Lou
Pole, the second end refers to source electrode.
Fig. 7 show a kind of preferred working timing figure of the phase inverter of the offer of embodiment two, and it is first crystal that its is corresponding
Pipe M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th crystalline substance
Body pipe M7 is PMOS, the first level signal input VGH！First level signal of input is constant high level, second
Level input VGL！The second electrical level signal of input is constant low level.
Four working stages of the T1~T4 moment correspondence inverter circuit of embodiment two in Fig. 7, respectively such as Fig. 8 a~8d
It is shown.Describe the course of work of the phase inverter of embodiment two in detail with reference to Fig. 7 and Fig. 8 a~8d：
Fig. 8 a are the circuit diagram of the first stage of inverters work, i.e. T1 periods, and initial signal IN is high level, control the
One transistor M1 and the 5th transistor M5 is closed, and the first clock signal CK is changed into low level from high level, by the first electric capacity C1
Coupling, drag down the grid potential of transistor seconds M2, because transistor seconds is equivalent to diode, now second
Transistor M2 is turned on, and then transmission grid potential controls the 4th transistor M4 and the 7th transistor respectively to Section Point N2
M7 is opened, and the 4th transistor M4 transmits the first level signal VGH！To first node N1, the 6th transistor of control is closed, and the 7th is brilliant
Body pipe M7 transmission second electrical level signals VGL！To the output end out of phase inverter, as the output signal in the stage.
Fig. 8 b are the circuit diagram of the second stage of inverters work, namely T2 periods, initial signal is high level, control control
The first transistor M1 processed and the 5th transistor M5 is closed.First clock signal CK is changed into high level by low level, by first
The coupling of electric capacity C1 so that the grid potential of transistor seconds M2 be high level, therefore transistor seconds M2 close.Due to second
The holding effect of electric capacity C2 so that Section Point N2 still keeps the low level current potential during first stage, therefore the 7th transistor
M7 is still opened, transmission second electrical level signal VGL！Protected to the output end of phase inverter, namely Section Point N2 and output end signal
Hold constant.
Fig. 8 c are the circuit diagram of the phase III of inverters work, namely T3 periods, initial signal IN is low level, control
The first transistor M1 and the 5th transistor M5 is opened, the first level signal VGH of high level！By the first transistor M1 transmit to
Section Point N2 so that Section Point N2 is high level, the 4th transistor M4 of control and the 7th transistor M7 is closed, needed herein
What is illustrated is, although the first clock signal CK is changed into low level by high level, by the coupling of the first electric capacity C1, can draw
The grid potential of low transistor seconds M2, and transmit to Section Point N2, because this process is of short duration coupling effect, and first
Transistor M1 transmits constant high level VGH！To Section Point N2, therefore current potential influences of the transistor seconds M2 on Section Point
Limited, the current potential of Section Point N2 is still high level.Low level second electrical level signal VGL！Passed by the 5th transistor M5
First node N1 is transported to, the 6th transistor M6 of control is opened, and the 6th transistor M6 transmits the first level signal VGH！To phase inverter
Output end, as the output signal of the second working stage.
Fig. 8 d are the circuit diagram of the fourth stage of inverters work, namely T4 moment, initial signal IN is high level, control
The first transistor M1 and the 5th transistor M5 is closed, and the first clock signal CK is changed into high level by low level, by the first electricity
Hold C1 coupling so that the grid potential of transistor seconds M2 be high level, therefore transistor seconds M2 close.Therefore first segment
The signal of point N1 and Section Point N2 will not receive any effect of signals, keep with it is constant on last stage, first node N1 controls the
Six transistor M6 are opened, and Section Point N2 controls the 7th transistor M7 to close, and the output signal of output end keeps constant.
From the above course of work, there is the second electric capacity, can keep second in Section Point N2 with inverter output
Node and the current potential stabilization of output end, are not influenceed so that the letter of inverter output OUT outputs by the first clock signal transitions
Number will not shake.And in whole work process, each stage, output end OUT has the 6th transistor M6 to transmit the first level signal
VGH！Or the 7th transistor M7 transmission second electrical level signal VGL！So that the signal of output end output will not be hanging, and output is more
Plus stabilization.
It should be noted that the first transistor~the 7th transistor in the phase inverter of the offer of embodiment two can be NMOS
Pipe, in its course of work, only needs initial signal, the first clock signal, the first level signal, second electrical level signal and above-mentioned level
Value is opposite.
Fig. 9 show the another kind preferably working timing figure of the phase inverter of embodiment two, its is corresponding be the first transistor M1,
Transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7
It is PMOS, the first level signal input VGH！First level signal of input is constant high level, and second electrical level is defeated
Enter to hold VGL！The second electrical level signal of input is constant low level.
Four working stages of T1~T4 periods correspondence embodiment two inverter circuit in Fig. 9, respectively as Figure 10 a~
Shown in 10d.Describe the course of work of the phase inverter of embodiment two in detail with reference to Fig. 9 and Figure 10 a~10d：
Figure 10 a are the circuit diagram of the first stage of inverters work, i.e. T1 periods, and initial signal IN is high level, control
The first transistor M1 and the 5th transistor M5 is closed, and the first clock signal CK is changed into low level from high level, by the first electric capacity
The coupling of C1, drags down the grid potential of transistor seconds M2, because transistor seconds is equivalent to diode, now
Two-transistor M2 is turned on, and then transmission grid potential controls the 4th transistor M4 and the 7th crystal respectively to Section Point N2
Pipe M7 is opened, and the 4th transistor M4 transmits the first level signal VGH！To first node N1, the 6th transistor of control is closed, and the 7th
Transistor M7 transmission second electrical level signals VGL！To the output end out of phase inverter, as the output signal in the stage.
Figure 10 b are the circuit diagram of the second stage of inverters work, i.e. T2 periods, and the first clock signal CK is turned by low level
It is changed into high level, by the coupling of the first electric capacity C1 so that the grid potential of transistor seconds M2 is high level, therefore second brilliant
Body pipe M2 is closed.Initial signal IN is low level, and control the first transistor M1 and the 5th transistor M5 is opened, the first of high level
Level signal VGH！Transmitted to Section Point N2 by the first transistor M1 so that Section Point N2 is high level, control the 4th
Transistor M4 and the 7th transistor M7 is closed.Low level second electrical level signal VGL！Transmitted to first by the 5th transistor M5
Node N1, the 6th transistor M6 of control is opened, and the 6th transistor M6 transmits the first level signal VGH！To the output end of phase inverter,
As the output signal of the second working stage.Figure 10 c are the circuit diagram of the phase III of inverters work, i.e. T3 periods, starting
Signal IN is high level, and control the first transistor M1 and the 5th transistor M5 is closed, and the first clock signal CK is changed into from high level
Low level, by the coupling of the first electric capacity C1, drags down the grid potential of transistor seconds M2, because transistor seconds is equivalent
In diode, now transistor seconds M2 conductings, and then transmission grid potential controls the 4th respectively to Section Point N2
Transistor M4 and the 7th transistor M7 is opened, and the 4th transistor M4 transmits the first level signal VGH！To first node N1, control
6th transistor is closed, the 7th transistor M7 transmission second electrical level signals VGL！To the output end out of phase inverter, as the stage
Output signal.
Figure 10 d are the circuit diagram of the fourth stage of inverters work, namely T4 moment, initial signal IN is high level, control
The first transistor M1 processed and the 5th transistor M5 is closed, and the first clock signal CK is changed into high level by low level, by first
The coupling of electric capacity C1 so that the grid potential of transistor seconds M2 be high level, therefore transistor seconds M2 close.Therefore first
The signal of node N1 and Section Point N2 will not receive any effect of signals, keep and constant on last stage, first node N1 controls
6th transistor M6 is opened, and Section Point N2 controls the 7th transistor M7 to close, and the output signal of output end keeps constant.
From the above course of work, there is the second electric capacity, can keep second in Section Point N2 with inverter output
Node and the current potential stabilization of output end, are not influenceed so that the letter of inverter output OUT outputs by the first clock signal transitions
Number will not shake.And in whole work process, each stage, output end OUT has the 6th transistor M6 to transmit the first level signal
VGH！Or the 7th transistor M7 transmission second electrical level signal VGL！So that the signal of output end output will not be hanging, and output is more
Plus stabilization.
It should be noted that the first transistor~the 7th transistor in the phase inverter of the offer of embodiment two can be NMOS
Pipe, in its course of work, only needs initial signal, the first clock signal, the first level signal, second electrical level signal and above-mentioned level
Value is opposite.
Embodiment three
Figure 11 show the preferred embodiment of the present invention three and provides a kind of drive circuit schematic diagram.It is electric referring to being driven described in Figure 11
Road can include：N grades of shift register and n phase inverter, wherein, n is the integer more than 1；N grades of shift register includes first
To n-th grade of shift register (corresponding with SR1-SRn respectively), n phase inverter includes the first phase inverter to n-th to level shift register
Phase inverter (corresponding with SF1-SFn respectively)；There are an input (respectively RIN1-RINn) and one per one-level shift register
Individual output end (respectively ROUT1-ROUTn), each phase inverter respectively has an input (respectively FIN1-FINn) and one
Output end (respectively FOUT1-FOUTn)；The input RIN1 of first order shift register SR1 as drive circuit input
End, since second level shift register SR2, input and the shift register of its previous stage per one-level shift register
Output end is electrically connected, and the output end ROUTi of every i grades of shift register is electrically connected with the input FINi of i-th phase inverter,
Wherein, 1≤i≤n, used as the corresponding output end of drive circuit, each phase inverter pair is electrically connected the output end of each phase inverter with it
The output signal of the shift register for connecing carries out anti-phase treatment, and inversion signal that will be resulting is believed as the output of drive circuit
Number.Wherein, phase inverter of the n phase inverter in the present embodiment described in above-described embodiment one or embodiment two.
The drive circuit that the embodiment of the present invention three is provided, employs the phase inverter of stable output signal, therefore, the driving
Circuit can export the output signal of stabilization.
Example IV
The preferred embodiment of the present invention four provides a kind of display panel.Figure 12 is a kind of display that the embodiment of the present invention four is provided
The structural representation of panel.Referring to Figure 12, the display panel in the present embodiment includes：First substrate 11 and with the phase of first substrate 11
To set second substrate 12, wherein, the first substrate 11 can for color membrane substrates, packaged glass (Cover Glass) or
Person's cover-plate glass (Cover Lens) etc., the second substrate 12 can be image element array substrates.
Figure 13 is a kind of structural representation of second substrate that the embodiment of the present invention four is provided.Referring to Figure 13, second substrate
During for image element array substrates, can include：Scan drive circuit 121, data drive circuit 122, launch driving circuit 123, m bars
Scan line (S1, S2 ..., Sm), k data lines (D1, D2 ..., Dk), m bars transmitting drives line (E1, E2 ..., Em) and
Multiple pixels 124；Wherein, the launch driving circuit 123 in the present embodiment is the drive circuit described in above-described embodiment three, at this
Repeated no more in embodiment.
Specifically, the scan drive circuit 121 in the present embodiment, for being provided to each bar scan line (S1, S2 ..., Sn)
Scanning signal；Data drive circuit 122, for providing data-signal to pieces of data line (D1, D2 ..., Dm)；Transmitting drives
Circuit 123, for each bar transmitting drives line (E1, E2 ..., Em) provide transmitting drive signal so that the picture in pixel 124
Plain compensation circuit completes node initializing, valve value compensation and data write-in etc.；Pixel 124 is separately positioned on scan line and data wire
In the region for intersecting to form.
The display panel that the embodiment of the present invention four is provided, by steady using output signal in the second substrate of display panel
Fixed launch driving circuit, can enable the pixel in second substrate stably work, such that it is able to make corresponding display surface
Plate reaches more preferable display effect.
Embodiment five
Figure 14 show the display device structure schematic diagram of the offer of the preferred embodiment of the present invention five, and display device 1 includes aobvious
Show panel 2, wherein display panel structure of the structure of display panel as described in example IV is identical.
It should be strongly noted that described " coupling " in the embodiment of the present invention refers to the electricity between two components
Property connection, including directly be electrically connected with and be indirectly electrically connected with.
Obviously, above-described embodiment is only used for the statement present invention in detail, does not constitute limiting the scope of the invention.
Under design of the invention, any no creative work of one of ordinary skill in the art and the various changes that carry out and modification,
Belong to the protection domain of the claims in the present invention.
Claims (10)
1. a kind of phase inverter, it is characterised in that including：The first transistor, transistor seconds, third transistor, the 4th transistor,
5th transistor, the 6th transistor, the 7th transistor, the first electric capacity and the second electric capacity；
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end is coupled for connecing
Receive the first level signal input of the first level signal, the second end coupling Section Point；
The first end of the transistor seconds is believed by first electric capacity with for receiving the first clock of the first clock signal
The coupling of number input, grid and the first end of the transistor seconds are coupled, and the second end is coupled to Section Point；
The grid of the third transistor couples the second clock signal input part for receiving second clock signal, the second end coupling
The first end of the transistor seconds is connect, first end couples the second electrical level signal input part for receiving second electrical level signal；
The grid of the 4th transistor is coupled to Section Point, and first end is coupled to the first level signal input, the
Two ends are coupled to first node；
The grid of the 5th transistor is coupled to the initial signal input, and first end is coupled to the second electrical level signal
Input, the second end is coupled to first node；
The grid of the 6th transistor couples the first node, and first end couples the first level signal input, the
Two ends couple the output end of phase inverter；
The grid of the 7th transistor is coupled to Section Point, and first end couples the second electrical level signal input part, second
The output end of end coupling phase inverter；
Second electric capacity is coupled between the Section Point and output end；
First clock signal and second clock signal pulse signal anti-phase each other.
2. phase inverter according to claim 1, it is characterised in that the working condition of the phase inverter include the first stage,
Second stage, phase III, fourth stage, wherein：
In the first stage, the initial signal controls the first transistor and the 5th transistor to close, and described the
Two clock signals control the third transistor to open, and the second electrical level signal is transmitted to described the through the third transistor
The grid of two-transistor simultaneously controls transistor seconds to open, then transmitted to Section Point through the transistor seconds, then distinguishes
The 4th transistor and the 7th transistor is controlled to open, the 4th transistor transmits the first level signal to first node, control
6th transistor is closed, and the 7th transistor transmits second electrical level signal to the output end, and the output as the stage is believed
Number；
In the second stage, the second clock signal controls the third transistor to close, and the initial signal controls institute
State the first transistor and the 5th transistor is opened, first level signal is transmitted to second by the first transistor
Node, the 7th transistor of control is closed, and the second electrical level signal is transmitted to first node, control by the 5th transistor
6th transistor is opened, and the 6th transistor transmits the first level signal to the output end, defeated as the stage
Go out signal；
In the phase III, the initial signal controls the first transistor and the 5th transistor to close, and described the
Two clock signals control the third transistor to open, and the second electrical level signal is transmitted to described the through the third transistor
The grid of two-transistor simultaneously controls transistor seconds to open, then transmitted to Section Point through the transistor seconds, then distinguishes
The 4th transistor and the 7th transistor is controlled to open, the 4th transistor transmits the first level signal to first node, control
6th transistor is closed, and the 7th transistor transmits second electrical level signal to the output end, and the output as the stage is believed
Number；
In the fourth stage, the initial signal controls the first transistor and the 5th transistor to close, and described the
Two clock signals control the third transistor to close, and first clock signal is by described in first Capacity control second
So that the transistor seconds is opened, the current potential of the grid of the transistor seconds is by described for the current potential of the grid of transistor
Two-transistor is transmitted to Section Point, and then the 4th transistor of control and the 7th transistor are opened respectively, the 4th transistor
The first level signal to first node is transmitted, the 6th transistor of control is closed, and the 7th transistor transmits second electrical level signal
To the output end, as the output signal in the stage.
3. phase inverter according to claim 1 and 2, it is characterised in that the first transistor, transistor seconds, the 3rd crystal
Pipe, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor are PMOS, and first level signal is perseverance
Fixed high level, described second electrical level signal is constant low level；Or,
The first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th crystalline substance
Body pipe is NMOS tube, and first level signal is constant low level, and described second electrical level signal is constant height electricity
It is flat.
4. a kind of phase inverter, it is characterised in that including：The first transistor, transistor seconds, third transistor, the 4th transistor,
5th transistor, the 6th transistor, the 7th transistor, the first electric capacity and the second electric capacity；
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end is coupled for connecing
Receive the first level signal input of the first level signal, the second end coupling Section Point；
The first end of the transistor seconds is believed by first electric capacity with for receiving the first clock of the first clock signal
The coupling of number input, grid and the first end of the transistor seconds are coupled, and the second end is coupled to Section Point；
The grid coupling Section Point of the third transistor, the second end couples the first end of the transistor seconds, first end
Couple the second electrical level signal input part for receiving second electrical level signal；
The grid of the 4th transistor is coupled to Section Point, and first end is coupled to the first level signal input, the
Two ends are coupled to first node；
The grid of the 5th transistor is coupled to the initial signal input, and first end is coupled to the second electrical level signal
Input, the second end is coupled to first node；
The grid of the 6th transistor couples the first node, and first end couples the first level signal input, the
Two ends couple the output end of phase inverter；
The grid of the 7th transistor is coupled to Section Point, and first end couples the second electrical level signal input part, second
The output end of end coupling phase inverter；
Second electric capacity is coupled between the Section Point and output end.
5. phase inverter according to claim 4, it is characterised in that the working condition of the phase inverter include the first stage,
Second stage, phase III, fourth stage, wherein：
In the first stage, the initial signal controls the first transistor and the 5th transistor to close, and described the
One clock signal is by the current potential of the grid of transistor seconds described in first Capacity control so that the transistor seconds is opened
Open, the current potential of the grid of the transistor seconds is transmitted to Section Point by the transistor seconds, is then controlled respectively
Four transistors and the 7th transistor are opened, and the 4th transistor transmits the first level signal to first node, and control the 6th is brilliant
Body pipe is closed, and the 7th transistor transmits second electrical level signal to the output end, used as the output signal in the stage；
In the second stage, because the holding of the second electric capacity is acted on so that the signal of the Section Point and output end keeps
It is constant；
In the phase III, the initial signal controls the first transistor and the 5th transistor to open, and described the
One level signal is transmitted to Section Point through the first transistor, controls the third transistor and the 7th transistor to close,
The second electrical level signal is transmitted to first node through the 5th transistor, controls the 6th transistor to open, and described the
Six transistors transmit first level signal to output end, used as the output signal in the stage；
In the fourth stage, the initial signal controls the first transistor and the 5th transistor to close, and described the
The signal of one node and the Section Point keeps constant, and the output signal of output end keeps constant.
6. phase inverter according to claim 4, it is characterised in that the working condition of the phase inverter includes：
First stage, first clock signal by the current potential of the grid of transistor seconds described in first Capacity control with
Open the transistor seconds, the current potential of the grid of the transistor seconds is transmitted to second section by the transistor seconds
Point, then the 4th transistor of control and the 7th transistor are opened respectively, and the 4th transistor transmits the first level signal to the
One node, the 6th transistor of control is closed, and the 7th transistor transmits second electrical level signal to the output end, used as the rank
The output signal of section；
Second stage, the initial signal controls the first transistor and the 5th transistor to open, first level
Signal is transmitted to Section Point through the first transistor, controls the third transistor and the 7th transistor to close, and described the
Two level signals are transmitted to first node through the 5th transistor, control the 6th transistor to open, the 6th crystal
Pipe transmits first level signal to output end, used as the output signal in the stage；
Phase III, first clock signal by the current potential of the grid of transistor seconds described in first Capacity control with
Open the transistor seconds, the current potential of the grid of the transistor seconds is transmitted to second section by the transistor seconds
Point, then the 4th transistor of control and the 7th transistor are opened respectively, and the 4th transistor transmits the first level signal to the
One node, the 6th transistor of control is closed, and the 7th transistor transmits second electrical level signal to the output end, used as the rank
The output signal of section；
Fourth stage, because the holding of the second electric capacity is acted on so that the signal of the Section Point and output end keeps constant.
7. the phase inverter according to any one of claim 4~6, it is characterised in that
The first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th crystalline substance
Body pipe is PMOS, and first level signal is constant high level, and described second electrical level signal is constant low electricity
It is flat；Or,
The first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th crystalline substance
Body pipe is NMOS tube, and first level signal is constant low level, and described second electrical level signal is constant height electricity
It is flat.
8. a kind of drive circuit, it is characterised in that including the phase inverter as any one of claim 1-7.
9. a kind of display panel, it is characterised in that including drive circuit as claimed in claim 8.
10. a kind of display device, it is characterised in that including display panel as claimed in claim 9.
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| CN104809979B (en) * | 2015-05-26 | 2017-07-18 | 京东方科技集团股份有限公司 | A kind of phase inverter and driving method, GOA unit, GOA circuits and display device |
| CN104851385B (en) * | 2015-06-08 | 2018-05-08 | 京东方科技集团股份有限公司 | A kind of phase inverter, voltage compensating circuit and display device |
| CN105139825B (en) | 2015-10-20 | 2017-08-25 | 京东方科技集团股份有限公司 | Shift register cell, gate drive apparatus, display device, control method |
| CN106328055B (en) * | 2016-10-25 | 2018-08-14 | 广东聚华印刷显示技术有限公司 | A kind of phase inverter, display driver circuit and display panel |
| CN111210766B (en) * | 2020-02-24 | 2021-04-06 | 厦门天马微电子有限公司 | Inverter and driving method thereof, gate driving circuit and display device |
| CN111613171B (en) * | 2020-06-23 | 2023-11-21 | 京东方科技集团股份有限公司 | Signal selection circuit and display device |
| CN112785959B (en) * | 2021-02-05 | 2024-05-10 | 厦门天马微电子有限公司 | Inverter, driving method thereof, driving circuit and display panel |
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Effective date of registration: 20211102 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Patentee after: Tianma Micro-Electronics Co.,Ltd. Address before: 201201, 889, Qing Qing Road, Shanghai, Pudong New Area Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. Patentee before: Tianma Micro-Electronics Co.,Ltd. |