CN104516477A - Techniques for entering a low power state - Google Patents

Techniques for entering a low power state Download PDF

Info

Publication number
CN104516477A
CN104516477A CN201410502483.5A CN201410502483A CN104516477A CN 104516477 A CN104516477 A CN 104516477A CN 201410502483 A CN201410502483 A CN 201410502483A CN 104516477 A CN104516477 A CN 104516477A
Authority
CN
China
Prior art keywords
power state
low power
platform
software
time phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410502483.5A
Other languages
Chinese (zh)
Other versions
CN104516477B (en
Inventor
L.K.普蒂耶达斯
A.阿加瓦
陆庆达
R.塞斯
M.C.瓦兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN104516477A publication Critical patent/CN104516477A/en
Application granted granted Critical
Publication of CN104516477B publication Critical patent/CN104516477B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3246—Power saving characterised by the action undertaken by software initiated power-off
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)

Abstract

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.

Description

Enter the technology of low power state
Technical field
Described embodiment relates generally to the low power state for calculation element herein.Specifically, embodiment relates to calculation element and the transformation of assembly from normal power state to low power state.
Background technology
The popularization of mobile device increases in continuation, and the processing power of these devices also increases in continuation.Correspondingly, increasing task performs on the mobile device.For guaranteeing that the continuation of mobile device is popularized in a large number, the life-span for the battery of powering for mobile device must be extended.Active computer platform comprises the power division of the assembly for managing this type of platform or one or more feature of power use in every way.This category feature can realize various power rating, and such as, the platform that response user starts suspends or sleep request.Mobile device can be converted to certain power rating based on request subsequently.But, can considerable time be taken between tour, enter low power state in time owing to not allowing mobile device and platform treating apparatus and reduce energy-conservation advantage.
Accompanying drawing explanation
fig. 1one embodiment of the first system is shown.
fig. 2one embodiment of the first logic flow is shown.
fig. 3 Aone embodiment of the first activity level figure is shown.
fig. 3 Bone embodiment of the second activity level figure is shown.
fig. 3 Cone embodiment of the 3rd activity level figure is shown.
fig. 3 Done embodiment of the 4th activity level figure is shown.
fig. 4one embodiment of the second logic flow is shown.
fig. 5one embodiment of calculation element is shown.
fig. 6one embodiment of counting system structure is shown.
Embodiment
Various embodiment relates generally to reduce the equipment of power consumption, method and other technology for computing system and platform treating apparatus being converted to low power state with extending battery life with for computing system.In certain embodiments, information can be sent to platform processes device by the software of such as operating system etc., and power management component can indicate computing system to enter low power state.
Power management component, by hardware automated processes and software process are converted to low power state, starts to the transformation of low power state.In certain embodiments, before these hardware automated processes and software process complete process, platform processes device can not enter low power state.Platform processes device and assembly can enter intermediateness to wait for that hardware automated processes and software process complete.
In certain embodiments, platform processes device can remain on middle power state, until all processes complete process, or until the event of definition occurs, as the cut-off of predefined interruption or scheduled timer.But waiting process completes or until the event of definition occurs to take considerable time, as several seconds or several minutes, and owing to not entering low power state in time, any sizable battery life increase may lose.
By interrupting one or more processor module before the event of definition, to allow one or more one or more software process of processor module process, power management component can reduce the time be converted to needed for low power state.In certain embodiments, power management component can wait for that the platform special time phase is to allow autonomic hardware process to complete and to determine whether platform processes device enters low power state.In certain embodiments, platform processes device can not enter low power state, this is because autonomic hardware process and/or software process not yet end process after the cut-off of platform special time phase.Power management component subsequently one or more processor module of interruptible price with process software process.By waiting for that the platform special time phase is to determine whether platform processes device enters low power state, power management component allows autonomic hardware process to complete, and platform certain power correlativity is hard coded into the needs in operating system by elimination.
In certain embodiments, power management component can receive software ready time from one or more software process, and instruction software process will be when ready, can process.Such as, can require that software process is waited for, until timer expires before treatment.In these embodiments, cross Cheng Qian with process software determining whether platform processes device has been converted to low power state and/or interruption or has waken (PCC) power up, power management component can wait for the shortest time of platform special time phase and software ready time phase interim longer time interval.By wake up process device assembly with process software process, can realize significantly reducing the time being converted to low power state.In addition, by waiting for until the platform special time phase and software ready time interim longer time interval, power management component can avoid too fast and software process can ready with before carrying out process with regard to wake up process device assembly.
By generality with reference to symbol used herein and term, can describe in detail below according to the program process introduction performed on computing machine or computer network.These process prescriptions and expression are used for most effectively its action being conveyed to others skilled in the art by those skilled in the art.
Process herein and be generally regarded as producing the sequence of operation be certainly in harmony of results needed.These operations are that those need the operation of the physical manipulation of physical quantity.This tittle usually but not necessarily adopts the form of electricity, magnetic or the light signal that can store, transmit, combine, compare and otherwise manipulate.These signals be called bit, value, element, symbol, character, item, numeral or like thisly sometimes prove easily, the mainly reason of Common usage.But it should be noted, all these and similar term will be associated with suitable physical quantity, and be just applied to the convenient mark of those amounts.
In addition, the manipulation of execution is often called terms such as such as adding or compare, and these terms are associated with the mental operation that operating personnel perform usually.In most of the cases, in any operation described herein of a part forming one or more embodiment, this type of ability of operating personnel is not required or desired.On the contrary, operation is machine operation.Useful machine for performing the operation of various embodiment comprises universal digital computer or similar device.
Various embodiment also relates to for performing these equipment operated or systems.This equipment can be required object and builds specially, or it can comprise the multi-purpose computer as optionally activated by the computer program stored in computing machine or reconfigured.The process introduced herein does not relate to certain computer or miscellaneous equipment in itself.Various general-purpose machinery can use together with the program write according to instruction herein, or provable structure more specialized apparatus to perform the desired method step be easily.Structure for the requirement of these machines multiple will appear in the description that provides.
Referring now to figure, wherein, similar label is used for referring to similar element in the whole text.In the following description, for ease of explaining, set forth many details to provide its detailed understanding.But, can it is realized that, the novel embodiment of practice can not need these specific detail.In other cases, the construction and device known illustrates in form of a block diagram to be conducive to it and describes.Object comprises all modifications consistent with described theme, equivalent and alternative.
fig. 1one embodiment of the suitable computing system 105 being suitable for realizing various embodiment is as described herein shown.In various embodiments, computer system 105 comprises platform processes device 110, controller 120, storage arrangement 130 and I/O (I/O) device 140.Platform processes device 110 can be the calculating element of any type, such as, but not limited to processor or the treatment circuit of other type any on microprocessor, processor, CPU (central processing unit), digital signal processing unit, dual core processor, mobile device processor, desktop computer processor, single core processor, system on chip (SoC) device, sophisticated vocabulary calculating (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor or single-chip or integrated circuit.Platform processes device 110 122,132 and 142 can be connected to controller 120, storage arrangement 130 and I/O device 140 through interconnecting respectively, and communicates with it.In addition, controller 120, storage arrangement 130 and I/O device 140 can communicate with all component of platform processes device 110.
Although not limited in this regard, platform processes device 110 can comprise outer (non-core) assembly (not shown) of power management component 115, one or more processor module 112, Graphics Processing Unit 114, platform I/O device 116, platform memory device 118 and other core any.The outer assembly of core can comprise other storer, high-speed cache, streamline, I/O device and controller.In certain embodiments, platform processes device 110 such as can have more than two process cores.One or more processor module 112 can have a more than processing unit or process core.One or more processor module 112 include but not limited to obtain instruction fetch logic, by the decode logic of instruction decoding, perform the actuating logic of instruction and like this.
In certain embodiments, platform processes device 110 comprises Graphics Processing Unit 114.Graphics Processing Unit 114 can serve as the attached processor of managing graphic and/or vision operation and/or process.
In certain embodiments, platform processes device 110 comprises platform I/O device 116 and platform storage arrangement 118.Platform I/O device 116 is provided for the external interface of other device in platform processes device 110 to computer system 105.In addition, the instruction of platform memory device 118 storage platform treating apparatus 110 and/or data, and specifically, the instruction of one or more processor module 112 and/or data.And platform processes device 110 and one or more processor module 112 are while execution instruction, platform memory device 118 also can store temporary variable or other intermediate information.In another embodiment, platform memory device 118 includes but not limited to other configuration any of the cache memory in one-level, secondary and three grades of cache memories or platform processes device 110.Processor module 112, Graphics Processing Unit 114, platform I/O device 116 can communicate through interconnection (not shown) mutually with platform storage arrangement 118.
Power management component 115 can be used for the power rating of management computing system 105, and specifically, the power rating of platform processes device 110 and assembly.In certain embodiments, power management component 115 can be used for for platform processes device 110 starts the transformation entering low power state.Low power state can be as on Dec 6th, 2011 announce advanced configuration and Power Interface Specification, any advanced configuration of the 5.0th edition (Advanced Configuration and Power Interface Specification, Revision 5.0) or definition in later or more early announcing and power interface (ACPI) state.In certain embodiments, low power state can be idle state, as SOix.
In certain embodiments, power management component 115 can receive instruction from the such as software such as operating system or other program any or information, and instruction platform processes device 110 can enter low power state.In one example, by starting to entering of the middle power state such as Mwait C state that such as corresponds to ACPI C3 state, operating system can indicate it to enter low power state to platform processes device 110 and power management component 115.ACPI C3 state is commonly referred to sleep state, and provide than C1 and C2 state improve energy-conservation.While in C3 state, cut down all internal clock signals from process core.But one or more process core high-speed cache is kept.Operating system is responsible for guaranteeing that high-speed cache keeps coherence.
Once the autonomous component process of all hardware and software process complete, processing platform treating apparatus 110 just can enter low power state.The autonomous component process of hardware can be the process not requiring software process information performed by the nextport hardware component NextPort of the platform processes devices such as such as register, storer, high-speed cache, transistor, clock, process core, controller, I/O assembly.Software process can be the requirement that stores in storer or the high-speed cache any process by nextport hardware component NextPort process.In certain embodiments, the autonomous component process of hardware and software process can be the processes for making nextport hardware component NextPort and software process be converted to low power state and generate.
In certain embodiments, these hardware automated processes and software process can not complete process immediately, and platform processes device 110 can be stoped to be converted to target low power state.Under certain situation, stage apparatus 110 can be in middle power state, in the maximal efficiency of the unrealized low power state of this state.Platform processes device 110 can remain on this middle power state, until the autonomous component process of all hardware and software process end process.In certain embodiments, there is the event of the definition such as cut-off of predefined interruption or scheduled timer, wake platform processes device 110 and assembly up and before processing one or more software process, process can not terminate from intermediateness.Predefine interrupts can being any interruption of being dispatched by hardware or software before starting to low power state.Scheduled timer can be scheduled to be interrupted by karyogenesis when timer expires or any hardware of start treatment or software timer or clock.
In certain embodiments, power management component 115 can determine the process of autonomic hardware assembly, software process or both when stop platform processes device 110 to enter low power state.After power management component 115 can be ended based on the cut-off of interval when predefined, whether platform processes device 110 enters low power state and makes and determining.The time predefined phase can be any time phase, enters low power state averaging time used as made platform processes device 110.Power management component also can monitor from master component and software process to determine whether these assemblies and process require other process.In addition, power management component 115 is in the signal of low power state by the instruction platform processes device 110 received from processor module 112, determines whether platform processes device 110 is in low power state.
If power management component 115 determines that one or more autonomic hardware assembly or software process enter low power state at prevention platform processes device 110, interval when then power management component 115 waits for certain, as platform special time phase or software ready time phase, and make the determination whether associated platform processing components 110 is in low power state subsequently.In certain embodiments, power management component 115 can make determine before wait for the platform special time phase and software ready time interim longer time interval.
The platform special time phase can be that platform processes device 110 arranges to allow autonomic hardware assembly to end process the time predefined of information.In certain embodiments, one or more autonomic hardware assembly can be sent to power management component 115 by indicating the temporal information of the required time amount that end process.In this example, the plateau time phase can be the maximum duration that power management component 115 receives.
The software ready time phase be next software event of instruction when ready with carry out processing time interval.In various embodiments, software ready time information can be sent to power management component 115 by one or more software process, and the software ready time that the software ready time phase can be power management component 115 to be received interim the shortest time interval.
In various embodiments, when power management component 115 determines that platform processes device not yet enters low power state in platform special time phase and the interim longer time after date of software ready time, power management component 115 can generate interruption or wake events with from Mwait or C3 state, namely middle power state wakes the processing components of such as processor module 112 grade up, to process one or more software process.Interruption or wake events can generate before the event of definition.By generating non-scheduled interruption or wake events with process software process, platform processes device 110 can enter low power state within the time of more much shorter.
In certain embodiments, platform processes device 110 and power management component 115 can be received in after process software process completes, and platform processes device 110 is ready with another instruction entering low power state.Platform processes device 110 can enter low power state subsequently.But in certain embodiments, before platform processes device 110 can enter low power state, other autonomic hardware assembly and software process can require process.Such as, other process can rely on other process always and terminate, and can process afterwards to them.Power management component 115 as above and described in more detailly in fig. 2 can complete identical process, to process the process of all autonomic hardware assemblies and software process.Before the process of all autonomic hardware assemblies and software process complete, this process can repeatedly iteration.
Calculation element 105 also can comprise controller 120, and controller 120 can comprise the treatment circuit of microcontroller or other type, storer and interface logic.In certain embodiments, controller 120 can the operation of monitoring and controlling computer system 105, includes but not limited to the operation of monitoring and controlling storage arrangement 130 and I/O device 140.Controller 120 also can the various aspects of monitoring and controlling platform processes device 110, include but not limited to the communication between computer system 105 and the various assemblies of platform treating apparatus 110.In various embodiments, controller 122 can be coupled with platform processes device 110 through interconnecting.
Storage arrangement 130 stores instruction and/or the data of computer system 105.Computer system 105 is when performing instruction, and storage arrangement 130 also can store temporary variable or other intermediate information.I/O device 140 is the interfaces between computer system 105 and external system or device.I/O device 140 can communicate with external system or device through connecting 144.Connecting 144 can be wired or wireless or any alternate manner well known to those skilled in the art.In one embodiment, I/O device 140, by platform I/O device 116,142 to communicate with platform processes device 110 through interconnecting.Power management component 115, storage arrangement 130 and I/O device 140 also can communicate through interconnection (not shown) mutually.
Assembly shown in computer system 105 has no intention to limit, and its statement is for convenience of explanation.In other embodiments, the configuration of computer system 105 comprises (more or less) assembly different from shown in Fig. 1.Various equivalent modifications will understand, and other configuration of computer system 105 can be used without the effect of impact described embodiment herein.
fig. 2comprise and illustrate that platform processes device enters the logical flow chart of an example of low power state.For clarity, the computer system 105 with reference to Fig. 1 discusses logic flow.At frame 201, the transformation of low power state can be started to.Such as, power management component 115 can receive instruction from the such as software such as operating system or other program any or information, and instruction platform processes device 110 can enter low power state.In one example, by platform processes device 110 and/or processor module 112 being placed in the middle power state of the Mwait C state etc. such as corresponding to ACPI C3 state, operating system can indicate it to enter low power state to platform processes device 110 and power management component 115.
At decision box 203, all component of associated platform treating apparatus 110 can be made whether in the determination of low power state.Such as, power management component 115 can determine when predefined after interval cut-off, whether all component is at low power state.In another example, power management component 115 can monitoring component, component process and software process to determine that whether platform processes device 110 is at low power state.In the 3rd example, power management component 115 is applied to processor module 112 and the voltage of other platform processes device 110 assembly and the hardware context of storer by checking, determines that whether platform processes device 110 is at low power state.
If determine that platform processes device 110 is in target low power state at frame 203, then platform processes device 110 can remain on this state, until platform processes device 110 wakes up from this state by event or interruption.But if determine that platform processes device 110 is not in target low power state at frame 203, then at frame 205, power management component 115 can wait for that the process of autonomic hardware assembly and/or software process complete.
In various embodiments, power management component 115 can wait for the platform special time phase and software ready time interim longer time interval complete to allow the process of autonomic hardware assembly.In certain embodiments, power management component 115 can not receive the software ready time information from software process as mentioned above, and can make before whether associated platform treating apparatus 110 entered the determination of low power state at decision box 207, a wait platform special time phase.
If determine that platform processes device 115 is in low power state in decision box 207 power management component 115, then at frame 209, logic flow can terminate.But, if determine that platform processes device 110 is not in low power state in decision box 207 power management component 115, then power management component 115 can generate interruption or wake events with from Mwait or C3 state, namely middle power state wakes the processing components such as such as processor module 112 up, to process one or more software process.Interruption or wake events can generate before the event of definition.By generating non-scheduled interruption or wake events with process software process, platform processes device 110 can enter low power state within the time of more much shorter.At frame 213, one or more processor module 112 can process software process, and logic flow 200 can repeat.Such as, automated processes and the responsible software process of other software process complete, and can process afterwards to them.In various embodiments, before platform processes device 110 and assembly are in low power state, logic flow 200 can iteration repeatedly.
fig. 3 Aone example embodiment of first activity level Figure 30 0 for platform processes device being converted to low power state is shown.First activity level Figure 30 0 illustrates normal power state rank 301, middle power state levels 303 and low power state level 305.Normal power state is that platform processes device 110 and assembly are energized and completely when process information.Middle power state can be Mwait state and/or ACPI C3 state, and in a state in which, processor module 112 is not in process, but other is not yet converted to low power state from master component and software process.Low power state level 305 can be that platform processes device 110 and assembly are when being in the idle states such as such as SOix.
At point 307, activity level Figure 30 0 illustrates that power management component 115 receiving platform treating apparatus 110 can enter the instruction of more low power state.In one example, by platform processes device 110 and/or processor module 112 being placed in the middle power state such as Mwait C state such as corresponding to ACPI C3 state, operating system can indicate it to enter low power state, as shown in activity level Figure 30 0 to platform processes device 110 and power management component 115.
At the point 309 of activity level Figure 30 0, the event of the definition that platform processes device can indicate based on lines 315, transforms back into normal power state.Once in normal power state, platform processes device 115 enters any software process of low power state with endorsing process prevention platform processes device 115.Once software process is processed, platform processes device 110 and power management component 115 just can receive another instruction of the transformation of more low power state, and can start at point 311 to the transformation of low power state.In addition, platform processes device 110 can enter low power state at point 313, and remains on this state, until platform processes device 110 wakes up from low power state by event or interruption.
fig. 3 B/3Can embodiment for the second activity level Figure 32 5 and the 3rd activity level Figure 35 0 being converted to low power state is shown.In these embodiments, platform processes device 110 and assembly can exit middle power state 303 with process software process, to be converted to low power state before the event 315 of definition.Such as, can to interrupt from middle power rating 303 or wake up process assembly is converted to one or more autonomic hardware process or software process of more low power state to process to stop.At point 307, platform processes device 110 can enter the instruction of low power state by receiving platform treating apparatus 110, and can start to the transformation of low power state 305.As previously described, platform processes device 110 can enter middle power state 303, until interval cut-off when platform special time phase or software ready time interim longer.
In certain embodiments, platform processes device 110 and power management component 115 can exit middle power state 303 before the event of the definition of lines 315 instruction.Lines 317 and 319 illustrate when platform special time phase and software ready time phase end respectively.In figure 3b, the software ready time phase is in the cut-off of platform special time after date, and power management component 115 can be waited for, until the cut-off of software ready time phase just starts the transformation getting back to normal power state 303 at point 309.But, as shown in Figure 3 C, the platform special time phase can as lines 317 be shown in software ready time after occur.In this example, get back to normal power state 301 with the transformation of process software process before, power management component 115 can be waited for, until the platform special time phase cut-off.
Platform processes device 110 can enter normal power state 301 and processing requirements completes to be converted to any software process of low power state 305.Platform processes device 110 completes these software process of process with endorsing at point 311, and can be started by platform processes device 110 to another transformation of low power state 311, or be started by making platform processes device 110 enter middle power state 303 by operating system.In certain embodiments, all hardware independently processes and can complete with software process, and platform processes device 110 can be allowed to enter low power state at point 313.
fig. 3 Done embodiment of the 4th activity level Figure 37 5 for platform processes device being converted to low power state is shown.4th activity level Figure 37 5 is similar to activity level Figure 35 0, and transforms back into normal power state 301 when the platform special time phase cut-off that lines 317 indicate.But in this embodiment, when platform processes device 110 reception enters the instruction of low power state, not all hardware automated processes and software process complete at point 311.Such as, the completing of some hardware automated processes and/or software process other software process responsible.Platform processes device 110 and assembly can get back to middle power state 303, and before exiting middle power state 303 and process other software process, wait for the platform special time phase and software ready time interim longer time interval.
In one example, the software ready time phase can as the lines 329 that occur after the lines 327 be shown in platform special time after date and occur.Platform processes device 110 can transform back into normal process state 301 to process other software process at point 321 subsequently.At point 323, platform processes device 110 can end process these software process, and receives the instruction entering low power state 303.Platform processes device 325 can enter low power state at point 325 subsequently.Various embodiment is not limited to above-mentioned example, and in certain embodiments, the platform special time phase can end at software ready time after date.
In addition, as above relative to as described in Fig. 2, the platform special time phase and software ready time interim longer time interval cut-off time, power management component 115 can determine whether that all automated processes and software process complete, and if be, then platform processes device 110 can be converted to low power state 305.More particularly, platform processes device 110 and assembly can not get back to normal power state 301, but will be converted to low power state 305.
fig. 4an embodiment of the second logic flow 400 is shown.Logic flow 400 can represent the some or all of operations of described one or more embodiment execution herein.Such as, logic flow 400 can illustrate by system 100, and more particularly, the operation performed by the computer system 105 of system 100.In the illustrated embodiment shown in Fig. 4, logic flow 400 can be included in the transformation that frame 402 starts to low power state.More particularly, the platform processes device 110 that makes that power management component 115 can receive from the software of such as operating system etc. is placed in the instruction of low power state.In one example, instruction can be the information comprising instruction platform processes device being placed in the middle power states such as the Mwait C state that such as corresponds to ACPI C3 state.Power management component by platform processes device 110 is placed in middle power state, starts to the transformation of low power state subsequently.
At frame 404, logic flow 400 can comprise deterministic process and when stop system to be accomplished to the transformation of more low power state.In various embodiments, process can be autonomic hardware process or software process, and has failed process due to process, and therefore, process stops platform processes device 110 to enter low power state.In certain embodiments, a more than process can stop platform processes device 110 to enter low power state.
Logic flow 400 also can comprise from middle power rating interrupt handler so that this process of execution pre-treatment of the event in definition.Specifically, the power management component 115 of platform processes device 110 can wait for the platform special time phase or software ready time interim longer time interval, and interrupt such as processor such as processor module 112 grade subsequently with process or calculate this process (or several process) stoping platform processes device 110 to enter low power state.In certain embodiments, platform processes device 110 can enter low-power and not process one or more process, this is because hardware automated processes can complete before the cut-off of platform special time phase.
fig. 5illustrating can the embodiment of calculation element 500 of implementation system 100.In an embodiment, such as, device 500 can be embodied as the mobile computing device with radio function.Mobile computing device such as can refer to have disposal system and any device as the mobile power sources such as one or several battery or power supply.
As mentioned above, the example of mobile computing device can comprise personal computer (PC), laptop computer, super laptop computer, flat board, touch pad, portable computer, handheld computer, palmtop computer, personal digital assistant (PDA), cell phone, combination cellular phone/PDA, TV, intelligent apparatus (such as, smart phone, Intelligent flat or intelligent television), mobile Internet device (MID), messaging device, data communication equipment (DCE) etc.
The example of mobile computing device also can comprise the computing machine being arranged to be worn by people, as wrist computing machine, finger computer, finger ring computing machine, eyeglass computer, strap clamp computing machine, arm straps computing machine, footwear computing machine, clothing computers and other wearable computer.In an embodiment, such as, mobile computing device can be embodied as the smart phone that can perform computer applied algorithm and Speech Communication and/or data communication.Although some embodiments are by example, be described by means of the mobile computing device being embodied as smart phone, can understand, other embodiment also can use other wireless mobile computing device to realize.Embodiment is not limited thereto context.
As shown in Figure 5, device 500 can comprise display 554, navigation controller 550, user interface 553, shell 555, I/O device 556 and antenna 557.Display 554 can comprise any applicable display unit for showing the suitable information of mobile computing device.Navigation controller 550 can comprise and can be used for one or more navigation characteristic mutual with user interface 553.I/O device 556 can comprise any suitable I/O device for information being inputted in mobile computing device.The example of I/O device 556 can comprise alphanumeric keyboard, numeric keypad, touch pad, enter key, button, switch, rocker switch, microphone, loudspeaker, voice recognition device and software etc.Information is also by microphone device input 500.This type of information can carry out digitizing by voice recognition device.Embodiment is not limited thereto context.
fig. 6one embodiment of the demonstration counting system structure 600 being suitable for realizing various embodiment is as previously described shown.In one embodiment, counting system structure 600 can comprise or be embodied as a part for calculation element 115.
When using in this application, term " system " and " assembly " will refer to computing machine concerned entity, and be hardware, the combination of hardware and software, software or software in commission, its example is provided by counting system structure 600 of demonstrating.Such as, assembly can but be not limited to be the process, processor, hard disk drive, (optics and/or magnetic-based storage media) multiple memory driver, object, executable file, the thread of execution, program and/or the computing machine that run on a processor.As explanation, the application program run on the server and server can be all assemblies.In the process that one or more assembly can reside in execution and/or thread, and assembly and/or can be distributed between two or more computing machines on a computing machine.In addition, assembly intercouples by various types of communication media by correspondence with coordinated manipulation.Coordination can relate to the unidirectional of information or two-way exchange.Such as, the assembly signal form transmission of information that can be transmitted by communication media.Information can be embodied as the signal being assigned to various signal line.In this type of distributes, each message is signal.But other embodiment can alternative employing data-message.This type of data-message can send across various connection.Demonstration connection comprises parallel interface, serial line interface and bus interface.
Counting system structure 600 comprises various common calculating element, as one or more processor, polycaryon processor, coprocessor, memory cell, chipset, controller, peripheral hardware, interface, oscillator, timing device, video card, audio card, multimedia I/O (I/O) assembly, power etc.But embodiment is not limited by the realization of counting system structure 600.
As shown in Figure 6, counting system structure 600 comprises processing unit 604, system storage 606 and system bus 608.Processing unit 604 can be any processor of processor on sale on various market, those processors as described above with regard to fig.1 described in platform processes device 110.
System bus 608 is provided for the interface of system component, and system component includes but not limited to system storage 606 and processing unit 604.System bus 608 can be bus-structured any bus structure of several types, bus structure also can use any architecture of multiple bus architecture commercially available, be interconnected to memory bus (with or no memory controller), peripheral bus and local bus.Interface adapter can be connected to system bus 608 through slot architecture.Example slot architecture can include but not limited to Accelerated Graphics Port (AGP), card bus, (expansion) industry standard architecture ((E) ISA), micro channel architecture (MCA), NuBus, peripheral component interconnect (expansion) (PCI (X)), PCI Express, PCMCIA (personal computer memory card international association) (PCMCIA) and like this.
Counting system structure 600 can comprise or realize various goods.Goods can comprise computer-readable recording medium with stored logic.The example of computer-readable recording medium can comprise can any tangible medium of storage of electronic, comprises volatile memory or nonvolatile memory, detachable or non-detachable memory, erasable or non-erasable memory, can write or recordable memory etc.The example of logic can comprise the executable computer program instruction of the codes implement using any applicable type, as source code, coding and decoding, interpreter code, executable code, quiet code, dynamic code, object-oriented code, visible code and like this.Embodiment also can be embodied as the instruction comprised in tangible non-transitory computer-readable medium or on it at least partly, can read and perform to perform described operation herein by one or more processor.
System storage 606 can comprise various types of computer-readable recording mediums of one or more more high-speed memory unit form, as ROM (read-only memory) (ROM), random access memory (RAM), dynamic ram (DRAM), double data rate (DDR) DRAM (DDRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM), programming ROM (PROM), erasable programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, polymer memory, as ferroelectric polymer memory, ovonic memory, phase transformation or ferroelectric memory, silicon oxide nitride oxide silicon (SONOS) storer, magnetic card or optical card, such as redundant array of independent disks (RAID) driver, solid state memory device (such as, USB storage, solid-state drive (SSD)) and the storage medium of other type any of applicable storage information.In the illustrated embodiment shown in Fig. 6, system storage 606 can comprise nonvolatile memory 610 and/or volatile memory 612.Basic input/output (BIOS) can be stored in nonvolatile memory 610.
Computing machine 602 can comprise various types of computer-readable recording mediums of one or more lower speed form of memory, comprise inside (or outside) hard disk drive (HDD) 614, read or write magnetic floppy disk drive (FDD) 616 wherein and from detachable CD 622(such as from detachable disk 618, CD-ROM or DVD) read or write CD drive 620 wherein.HDD 614, FDD 616 and CD drive 620 can be connected to system bus 608 respectively by HDD interface 624, FDD interface 626 and optical drive interface 628.The HDD interface 624 realized for peripheral driver can comprise USB (universal serial bus) (USB) and IEEE 1394 interfacing one of at least or both.
Driver and associated computer-readable media provide volatibility and/or the non-volatile memories of data, data structure, computer executable instructions etc.Such as, multiple program module can be stored in driver and memory cell 610,612, comprises operating system 630, one or more application program 632, other program module 634 and routine data 636.In one embodiment, one or more application program 632, other program module 634 and routine data 636 such as can comprise various application and/or the assembly of system 105.
User can pass through such as one or more wire/wireless input medias such as pointing device such as keyboard 638 and such as mouse 640, will order with in information input computing machine 602.Other input media can comprise microphone, infrared (IR) telepilot, radio frequency (RF) telepilot, game paddle, writing pencil, card reader, dongle, fingerprint reader, gloves, graphic tablet, operating rod, keyboard, retina reader, touch-screen (such as, capacitor type, resistor-type etc.), trace ball, Trackpad, sensor, pointer and like this.These and other input media is connected to processing unit 604 frequently by the input media interface 642 being coupled to system bus 608, but can be connected by other interfaces such as such as parallel port, IEEE 1394 serial port, game port, USB port, IR interfaces.
The display device of monitor 644 or other type is also connected to system bus 608 through interfaces such as such as video adapters 646.Monitor 644 can in the inside of computing machine 602 or outside.Except monitor 644, computing machine generally comprises other peripheral output device, as loudspeaker, printer etc.
Computing machine 602 through the wired and/or radio communication to one or more remote computers such as such as remote computers 648, can use logic to be connected in the environment of networking and operates.Remote computer 648 can be workstation, server computer, router, personal computer, portable computer, the amusement household electrical appliances based on microprocessor, reciprocity device or other common network node, and generally comprise relative to the many or all elements described in computing machine 602, but for simplicity's sake, merely illustrate storage/memory 650.The logic that illustrates connects the wire/wireless being included in the more macroreticular such as LAN (Local Area Network) (LAN) 652 and/or such as wide area network (WAN) 654 and connects.This type of LAN and WAN networked environment is common in office and company, and is conducive to the computer network of the enterprise-wides such as such as Intranet, and all-network can be connected to global communications network, such as, and the Internet.
When using in LAN networked environment, computing machine 602 is connected to LAN 652 by wired and/or wireless communication network interface or adapter 656.Adapter 656 can be conducive to the wired of LAN 652 and/or radio communication, and LAN 552 also can be included in above it and dispose to carry out with the radio function of adapter 656 WAP that communicates.
When using in WAN networked environment, computing machine 602 can comprise modulator-demodular unit 658, or is connected to the communication server on WAN 654, or has other parts for being set up communication by WAN 654, as by means of the Internet.Can inner or outside and be wired and/or the modulator-demodular unit of wireless device 658 is connected to system bus 608 through input media interface 642.In the environment of networking, can be stored in remote memory/memory storage 650 relative to the program module shown in computing machine 602 or its part.To understand, it is for demonstration that shown network connects, and can make between the computers otherwise to set up communication link.
Computing machine 602 for communicating with the wired and wireless device or entity that use IEEE 802 standard series, as operated the wireless device (such as, IEEE 802.11 modulation technique in the air) of deployment in wireless communications.Among other things, this at least comprises WiFi(or Wireless Fidelity), WiMax and Bluetooth wireless technology, 3G, 4G, LTE wireless technology.Therefore, communication can be the predefine structure as by general networks, or the ad hoc communication just between at least two devices.WiFi network use be called IEEE 802.11x(a, b, g, n etc.) radiotelegraphy provide safety, reliably, wireless connections fast.WiFi network can be used in computing machine to be interconnected, and is connected to the Internet and arrives cable network (medium using IEEE 802.3 relevant and function).
As various hardware elements, software element or both combinations can be comprised with reference to the various elements of the computer system 105 of Fig. 1-6 above.The example of hardware elements can comprise device, logical unit, assembly, processor, microprocessor, circuit, processor, electric circuit element (such as, transistor, resistor, capacitor, inductor etc.), integrated circuit, special IC (ASIC), programmable logic device (PLD) (PLD), digital signal processor (DSP), field programmable gate array (FPGA), memory cell, logic gate, register, semiconductor device, chip, microchip, chipset etc.The example of software element can comprise component software, program, application program, computer program, system program, software development procedures, machine program, operating system software, middleware, firmware, software module, routine, subroutine, function, method, process, software interface, application programming interfaces (API), instruction set, Accounting Legend Code, computer code, code segment, computer code segments, word, value, symbol or its any combination.But, determining whether embodiment uses hardware elements and/or software element to realize can according to the needs of given realization, change according to any amount of factor, computation rate as required, power level, heat resistance, treatment cycle budget, input data transfer rate, output data rate, memory resource, data bus speed and other design or performance constraints.
Detailed disclosures forwards the example providing and relate to other embodiment now to.The example one to three provided below 11 (1-31) is intended to demonstration and unrestricted.
In a first example, equipment or calculation element can comprise platform processes device, platform processes device comprises processor module and power management component, power management component starts to the transformation of more low power state, and determine that certain device process stops platform processes device to be accomplished to the transformation of more low power state, power management component is from middle power rating interrupt handler assembly to calculate or implementation before the execution of the event of definition.
In the second example and in the further in-depth of the first example, device process comprises software process or autonomic hardware process, and when power management component determination software process or autonomic hardware process stop platform processes device to be converted to more low power state.
In the 3rd example and in the further in-depth of any earlier examples, equipment or calculation element can comprise power management component to wait for the platform specific timer phase before interrupt handler assembly.
In the 4th example and in the further in-depth of any earlier examples, when equipment or calculation element can comprise power management component to determine platform special time phase or software ready time interim which, interval, is longer, and wait for before interrupt handler assembly the platform special time phase or software ready time interim longer time interval.
In the 5th example and in the further in-depth of any earlier examples, the event of definition comprises the interruption of definition and the cut-off of timer, and the event of definition occurs after platform special time phase and the cut-off of software ready time phase.
In the 6th example and in the further in-depth of any earlier examples, software ready time phase instruction software process when can Processing tasks, and when platform special time phase instruction autonomic hardware process completes.
In the 7th example and in the further in-depth of any earlier examples, equipment or calculation element can comprise power management component and wait for that one or more autonomic hardware process completes and when one or more autonomic hardware process completes, platform processes device is converted to more low power state.
In the 8th example and in the further in-depth of any earlier examples, equipment or calculation element can comprise processor module and perform the process that prevention equipment enters more low power state, and notification platform treating apparatus enters more low power state when complete.
In the 9th example and in the further in-depth of any earlier examples, equipment or calculation element can comprise power management component deterministic process when entry deterrence is when more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process complete, and when platform processes device does not enter described low power state.。
In the tenth example and in the further in-depth of any earlier examples, equipment or calculation element can comprise storer, Graphics Processing Unit and I/O (I/O) device.
In the 11 example and in the further in-depth of any earlier examples, the goods comprising computer-readable recording medium comprise multiple instruction, instruction allows processor to start to the transformation of more low power state when performing, and determine that certain device process stops system to be accomplished to the transformation of more low power state, and the execution pretreatment process of event from middle power rating interrupt handler so that in definition.
In the 12 example and in the further in-depth of any earlier examples, device process comprises software process or autonomic hardware process and multiple instruction, instruction, when being performed by processor, allows system determination software process or autonomic hardware process when to stop system transition to arrive low power state.
In the 13 example and in the further in-depth of any earlier examples, goods can comprise computer-readable recording medium, and medium comprises multiple instruction, instruction allows processor to wait for the specific timer of platform before interrupt handler assembly when performing during.
In the 14 example and in the further in-depth of any earlier examples, goods can comprise computer-readable recording medium, medium comprises multiple instruction, instruction allows processor determination platform special time phase or interim which of software ready time during when performing, interval, is longer, and wait for before interrupt handler assembly the platform special time phase or software ready time interim longer time interval.
In the 15 example and in the further in-depth of any earlier examples, software ready time phase instruction software process when can Processing tasks, and when platform special time phase instruction autonomic hardware process completes.
In the 16 example and in the further in-depth of any earlier examples, the event of definition comprises the interruption of definition and the cut-off of timer, and the event of definition occurs after platform special time phase and the cut-off of software ready time phase.
In the 17 example and in the further in-depth of any earlier examples, goods can comprise computer-readable recording medium, medium comprises multiple instruction, and instruction allows processor to wait for that one or more autonomic hardware process completes and when one or more autonomic hardware process completes, platform processes device is converted to more low power state when performing.
In the 18 example and in the further in-depth of any earlier examples, goods can comprise computer-readable recording medium, medium comprises multiple instruction, and instruction allows processor execution prevention system enter the process of more low power state and enter more low power state when process completes when performing.
In the 19 example and in the further in-depth of any earlier examples, goods can comprise computer-readable recording medium, medium comprises multiple instruction, instruction allows processor deterministic process, and when entry deterrence is when more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process complete when performing, and when system does not enter low power state.
In the 20 example and in the further in-depth of any earlier examples, method can comprise the transformation starting to more low power state, determine that certain device process stops platform processes device to be accomplished to the transformation of more low power state, and this process of execution pre-treatment of event from middle power rating interrupt processing assembly so that in definition.
In the 21 example and in the further in-depth of any earlier examples, method can comprise determines when software process or autonomic hardware process stop platform processes device to be converted to low power state.
In the 22 example and in the further in-depth of any earlier examples, it is longer that method can comprise interval when determining platform special time phase or software ready time interim which, and wait for before interrupt handler assembly the platform special time phase or software ready time interim longer time interval.
In the 23 example and in the further in-depth of any earlier examples, method can comprise waits for that one or more autonomic hardware process completes and when one or more autonomic hardware process completes, platform processes device is converted to low power state.
In the 24 example and in the further in-depth of any earlier examples, method can comprise execution prevention system and enters the process of more low power state and enter more low power state when process completes.
In the 25 example and in the further in-depth of any earlier examples, method can comprise deterministic process, and when entry deterrence is when more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process complete, and when system does not enter low power state.
In the 26 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, logic starts to the transformation of more low power state, and determine that certain device process stops platform processes device to be accomplished to the transformation of more low power state, and this process of execution pre-treatment of event from middle power rating interrupt handler assembly so that in definition.
In the 27 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, during logic waits for the specific timer of platform before interrupt handler assembly.
In the 28 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, when logic determination platform special time phase or software ready time interim which, interval, is longer, and logic wait for before interrupt handler assembly the platform special time phase or software ready time interim longer time interval.
In the 29 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, and one or more autonomic hardware process of logic waits completes and when one or more autonomic hardware process completes, platform processes device is converted to more low power state.
In the 30 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, logic performs the process that prevention equipment enters more low power state, and notification platform treating apparatus enters more low power state when complete.
In the 31 example and in the further in-depth of any earlier examples, it is logic within hardware at least partially that controller can comprise it, when entry deterrence is when more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process complete logic determination procedure, and when platform processes device does not enter low power state.
Some embodiments can use statement " embodiment " or " embodiment " and derivative thereof to be described.These terms represent that special characteristic, structure or the characteristic in conjunction with the embodiments described comprises at least one embodiment." in one embodiment " word that each position occurs in the description not necessarily all refers to same embodiment.In addition, some embodiments can use statement " coupling " to describe with " connection " and derivative thereof.These terms not necessarily synonym each other.Such as, some embodiments can use term " connection " and/or " coupling " to describe, with the direct physical indicating two or more elements mutual or electrical contact.But term " coupling " also can refer to that two or more elements directly do not contact mutually, but still to cooperate with each other or alternately.
It is emphasized that the summary part of present disclosure is provided for allowing reader to determine the essence of this technology disclosure fast.It is being submitted under the understanding being not used in explanation or restriction Claims scope or connotation.In addition, in above-mentioned embodiment, can see that various characteristic is combined to simplify disclosure in single embodiment.This open method may not be interpreted as reflecting requirement the embodiment of protection need clearer and more definite than each claim described in the purpose of more multiple features.On the contrary, as following claims reflect, subject matter of an invention relies on the feature more less than the single open all features of embodiment.Therefore, following claims is attached in embodiment at this, and it is that each claim itself remains independent embodiment.Enclosing in claim, term " comprise " and " wherein " be used separately as corresponding term " comprise " and " among " equivalent.In addition, term " first ", " second ", " the 3rd " etc. are only used as label, and force numerical requirements to its object unintentionally.
Foregoing comprises the example of disclosed architecture.Certainly, often kind of combination that can expect of assembly and/or method can not be described, but one skilled in the art will recognize that other combination and displacement are possible.Correspondingly, novel architecture is will this type of is alternative, modifications and variations are forgiven interior by all in following claims spirit and scope.

Claims (25)

1. an equipment, comprising:
Platform processes device, comprise processor module and power management component, described power management component starts to the transformation of more low power state, and determining device process stop platform processes device be accomplished to described in the described transformation of more low power state, described power management component interrupts described processor module to perform described device process before the execution of the event of definition from middle power rating.
2. equipment as claimed in claim 1, described device process comprises software process or autonomic hardware process, and described power management component determines when described software process or autonomic hardware process stop described platform processes device to be converted to described low power state.
3. equipment as claimed in claim 1, during described power management component waits for the specific timer of platform before the described processor module of interruption.
4. equipment as claimed in claim 1, when described power management component determination platform special time phase or software ready time interim which, interval, is longer, and wait for before interrupting described processor module the described platform special time phase or described software ready time interim described in longer time interval.
5. equipment as claimed in claim 4, the event of described definition comprises the interruption of definition or the cut-off of timer, and the event of described definition occurs after described platform special time phase and the cut-off of described software ready time phase.
6. equipment as claimed in claim 4, described software ready time phase instruction software process when can Processing tasks, and when instruction of described platform special time phase autonomic hardware process completes.
7. equipment as claimed in claim 1, described power management component waits for that one or more autonomic hardware process completes and more low power state described in being converted to by described platform processes device when one or more autonomic hardware process described completes.
8. equipment as claimed in claim 1, described processor module perform stop described equipment enter described in the described process of more low power state, and notify described platform processes device enter when complete described in more low power state.
9. equipment as claimed in claim 1, when described power management component is determined described process when described in entry deterrence, more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process are completed, when described platform processes device does not enter described low power state.
10. equipment as claimed in claim 1, comprising:
Storer;
Controller; And
I/O (I/O) device.
11. 1 kinds of computer implemented methods, comprising:
Start to the transformation of more low power state;
Determining device process stop described system be accomplished to described in the described transformation of more low power state; And
From middle power rating interrupt described processor in case definition event execution pre-treatment described in device process.
12. computer implemented methods as claimed in claim 11, described device process comprises software process or autonomic hardware process, and described method comprises and determines when described software process or autonomic hardware process stop described system transition to described low power state.
13., as claim 11 or computer implemented method according to claim 12, comprising:
Wait for the specific timer of platform before the described processor module of interruption during.
14., as claim 11 or computer implemented method according to claim 12, comprising:
When determining platform special time phase or software ready time interim which, interval, is longer; And
Interrupt waiting for before described processing components the described platform special time phase or described software ready time interim described in longer time interval.
15. computer implemented methods as claimed in claim 14, the described software ready time phase indicates described software process when can Processing tasks, and when instruction of described platform special time phase autonomic hardware process completes.
16. as claim 11 or computer implemented method according to claim 12, and the event of described definition comprises the interruption of definition or the cut-off of timer, and the event of described definition occurs after described platform special time phase and the cut-off of described software ready time phase.
17., as claim 11 or computer implemented method according to claim 12, comprising:
Wait for that one or more autonomic hardware process completes; And
More low power state described in described platform processes device being converted to when one or more autonomic hardware process described completes.
18., as claim 11 or computer implemented method according to claim 12, comprising:
Perform stop described system enter described in the described process of more low power state; And
More low power state described in entering when described process completes.
19., as claim 11 or computer implemented method according to claim 12, comprising:
When determining described process when described in entry deterrence, more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process complete, when described system does not enter described low power state.
20. 1 kinds of equipment, comprising:
For starting to the parts of the transformation of more low power state;
The parts of the more transformation of low power state described in being accomplished to for determining device process prevention platform processes device; And
For from middle power rating interrupt processing assembly in case described in the execution pre-treatment of the event of definition the parts of device process.
21. equipment as claimed in claim 20, comprise
For determining when described software process or autonomic hardware process stop described platform processes device to be converted to the parts of described low power state.
22., as claim 20 or equipment according to claim 21, comprising:
The parts that during for determining platform special time phase or software ready time interim which, interval is longer; And
For interrupt waiting for before described processing components the described platform special time phase or described software ready time interim described in longer time interval parts.
23., as claim 20 or equipment according to claim 21, comprising:
For waiting for the parts that one or more autonomic hardware process completes; And
For described platform processes device being converted to when one or more autonomic hardware process described completes the parts of described low power state.
24., as claim 20 or equipment according to claim 21, comprising:
For perform stop described system enter described in the parts of the more described process of low power state; And
For the parts of more low power state described in entering when described process completes.
25., as claim 20 or equipment according to claim 21, comprising:
During for determining described process when described in entry deterrence, more low power state and the process in the cut-off of platform special time phase or one or more autonomic hardware process completing, when described system does not enter the parts of described low power state.
CN201410502483.5A 2013-09-27 2014-09-26 Into the technology of low power state Active CN104516477B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/040118 2013-09-27
US14/040,118 US9459683B2 (en) 2013-09-27 2013-09-27 Techniques for entering a low power state

Publications (2)

Publication Number Publication Date
CN104516477A true CN104516477A (en) 2015-04-15
CN104516477B CN104516477B (en) 2018-03-27

Family

ID=52741364

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410502483.5A Active CN104516477B (en) 2013-09-27 2014-09-26 Into the technology of low power state

Country Status (3)

Country Link
US (2) US9459683B2 (en)
CN (1) CN104516477B (en)
TW (2) TW201738687A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI510910B (en) * 2013-11-11 2015-12-01 Wistron Corp Computer system and remote control method thereof
US20150355942A1 (en) * 2014-06-04 2015-12-10 Texas Instruments Incorporated Energy-efficient real-time task scheduler
US9746908B2 (en) * 2015-02-25 2017-08-29 Advanced Micro Devices, Inc. Pruning of low power state information for a processor
US20170300101A1 (en) * 2016-04-14 2017-10-19 Advanced Micro Devices, Inc. Redirecting messages from idle compute units of a processor
TWI596511B (en) * 2016-04-15 2017-08-21 致伸科技股份有限公司 Input module
CN107305439B (en) * 2016-04-21 2020-04-10 致伸科技股份有限公司 Input module
US11340683B2 (en) * 2020-03-27 2022-05-24 Intel Corporation Power management circuitry for controlling a power state transition based on a predetermined time limit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030061526A1 (en) * 2000-01-13 2003-03-27 Shinichi Hashimoto Computer system and power saving control method therefor
CN1493032A (en) * 2000-12-29 2004-04-28 ض� Method and apparatus for avoiding race condition with edge-triggered interupts
CN101002159A (en) * 2004-08-31 2007-07-18 英特尔公司 Method and apparatus for controlling power management state transitions
CN101676833A (en) * 2008-09-19 2010-03-24 英特尔公司 Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
US20100083387A1 (en) * 2008-09-26 2010-04-01 Stephane Rodgers Method and system for a secure power management scheme

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6785564B1 (en) * 1999-08-31 2004-08-31 Broadcom Corporation Method and apparatus for latency reduction in low power two way communications equipment applications in hybrid fiber coax plants
US6961859B2 (en) * 2002-01-30 2005-11-01 Hewlett Packard Development Company, L.P Computing device having programmable state transitions
US7197654B2 (en) * 2002-04-11 2007-03-27 International Business Machines Corporation Method and apparatus for managing low power processor states
US20050076254A1 (en) * 2003-10-01 2005-04-07 Robinson Michael A. Sleep recovery circuit and method
US20050239518A1 (en) * 2004-04-21 2005-10-27 D Agostino Anthony Systems and methods that provide enhanced state machine power management
EP1677175B1 (en) * 2004-12-31 2013-08-28 ST-Ericsson SA Dynamic power management in system on chips (SOC)
US7493505B2 (en) * 2005-12-13 2009-02-17 Silicon Laboratories Inc. MCU with low power mode of operation
TWI326817B (en) * 2006-07-07 2010-07-01 Via Tech Inc A power saving method and a system thereof applied to a cpu
JP4531020B2 (en) * 2006-08-01 2010-08-25 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
JP4517303B2 (en) * 2006-12-28 2010-08-04 ソニー株式会社 Information processing apparatus, activation method, and program
US8156362B2 (en) * 2008-03-11 2012-04-10 Globalfoundries Inc. Hardware monitoring and decision making for transitioning in and out of low-power state
US8762759B2 (en) * 2008-04-10 2014-06-24 Nvidia Corporation Responding to interrupts while in a reduced power state
US8112647B2 (en) * 2008-08-27 2012-02-07 Globalfoundries Inc. Protocol for power state determination and demotion
KR101607856B1 (en) * 2010-01-04 2016-04-11 삼성전자 주식회사 Optical disc playback device and control method thereof
JP5134022B2 (en) * 2010-01-17 2013-01-30 レノボ・シンガポール・プライベート・リミテッド Method for voltage control of a processor
JP2011170709A (en) * 2010-02-19 2011-09-01 Ricoh Co Ltd Network controller, image forming device, image forming system, energy-saving control method, and energy-saving control program
US8839006B2 (en) * 2010-05-28 2014-09-16 Nvidia Corporation Power consumption reduction systems and methods
US8700936B2 (en) * 2010-12-03 2014-04-15 Schneider Electric It Corporation Modular gating of microprocessor low-power mode
JP5731867B2 (en) * 2011-03-23 2015-06-10 キヤノン株式会社 Information processing apparatus, control method thereof, and program
EP2621127B1 (en) * 2011-12-09 2017-02-22 Huawei Technologies Co., Ltd. Method for achieving low power consumption of data exchange equipment and apparatus thereof, and data exchange equipment
US8775838B2 (en) * 2012-02-01 2014-07-08 Texas Instruments Incorporated Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data
US9329658B2 (en) * 2012-12-28 2016-05-03 Intel Corporation Block-level sleep logic
JP6127682B2 (en) * 2013-04-18 2017-05-17 富士ゼロックス株式会社 Processing control device, image processing device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030061526A1 (en) * 2000-01-13 2003-03-27 Shinichi Hashimoto Computer system and power saving control method therefor
CN1493032A (en) * 2000-12-29 2004-04-28 ض� Method and apparatus for avoiding race condition with edge-triggered interupts
CN101002159A (en) * 2004-08-31 2007-07-18 英特尔公司 Method and apparatus for controlling power management state transitions
CN101676833A (en) * 2008-09-19 2010-03-24 英特尔公司 Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
US20100083387A1 (en) * 2008-09-26 2010-04-01 Stephane Rodgers Method and system for a secure power management scheme

Also Published As

Publication number Publication date
US20170249008A1 (en) 2017-08-31
CN104516477B (en) 2018-03-27
US20150095676A1 (en) 2015-04-02
TWI578152B (en) 2017-04-11
US9459683B2 (en) 2016-10-04
TW201514680A (en) 2015-04-16
TW201738687A (en) 2017-11-01

Similar Documents

Publication Publication Date Title
CN104516477A (en) Techniques for entering a low power state
TWI599960B (en) Performing power management in a multicore processor
CN104981815B (en) Methods, devices and systems for limiting CPU affairs with security attribute
KR101683014B1 (en) A method, apparatus, system for continuous automatic tuning of code regions
US10560081B2 (en) Method, apparatus, system for centering in a high performance interconnect
CN107924380A (en) Use the methods, devices and systems of class of service distribution cache
CN108701109A (en) The methods, devices and systems of Plugin Mechanism for computer expansion bus
US10209911B2 (en) Techniques enabling low power states for a communications port
CN109634899A (en) System, the method and apparatus of SRIS model selection are carried out for PCIE
WO2016099750A1 (en) Method, apparatus and system for integrating devices in a root complex
CN108027785A (en) The method, apparatus and system of deflection are carried out for being split to link
TW201447580A (en) A method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
CN105009101A (en) Providing snoop filtering associated with a data buffer
KR20120096858A (en) Remote wakeup of application processor of mobile device
CN104813283A (en) Independent control of processor core retention states
CN102262434A (en) Method and apparatus for modifying a transition to an altered power state of an electronic device based on accelerometer output
JP2022138116A (en) Selection of communication protocol for management bus
TWI736559B (en) Controller to transmit data for components of a physical layer device
CN111381664A (en) Controlling power state degradation in a processor
CN103984543A (en) Method for implementing standby, hibernation and wake-up on domestic FeiTeng processor
US10394623B2 (en) Techniques for processing custom events
CN104777889A (en) Techniques for putting platform subsystems into a lower power state in parallel
Andrews et al. Keeping Always-On Systems On for Low-Energy Internet-of-Things Applications
CN203350878U (en) Embedded system function flattening design scheme
CN111033439A (en) Utilization metrics for processing engines

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant