CN104506201A - Code circuit designing method for (15, 5) BCH (Bose, Chaudhuri and Hocquenghem) code - Google Patents

Abstract

The invention provides a code circuit designing method for (15, 5) BCH (Bose, Chaudhuri and Hocquenghem) code. The method comprises the steps of constructing a serial code circuit according to a generator polynomial of the (15, 5) BCH code; acquiring stored redundant check bit after inputting the (i+1)th information bit, redundant check bits stored in registers after inputting the i th information bit, and a first relational expression of the input (i+1) information bits for each register in the serial code circuit; acquiring stored redundant check bit after inputting all five information bits, redundant check bit stored in each register when no information bit is input, and a second relational expression of all five information bits for each register in the serial code circuit; and according to the second relational expression, constructing a parallel code circuit. According to the code circuit designing method, a parallel circuit replaces a traditional serial code scheme, so that the coding time is greatly shortened.

Description

The coding circuit method for designing of (15,5) BCH code

Technical field

The present invention relates to error-correcting code technique field, particularly a kind of coding circuit method for designing of (15,5) BCH code.

Background technology

BCH (BoSe Ray-Chaudhuri Hocque5ghe15) is a kind of error correcting code efficiently, and its loop coding and decoding feature make it communicate, be widely used in the reliability etc. of control and memory automatically improving.

Usual Bose-Chaudhuri-Hocquenghem Code decoding adopts serial mode to realize, and needed for the coding and decoding of this scheme, circuit is very little, but the coding and decoding time but depends on clock cycle and code word size, therefore circuit speed is being required to high occasion seems inapplicable.

(15,5) BCH code can correct the mistake of 3, altogether needs the redundancy check bit of 10, at the GF (2 of m=4 ⁴) structure can correct three wrong BCH code on territory, therefore t=3.At GF (2 ⁴) on, basis α and α ³=α ^2t-1corresponding multinomial is respectively:

φ ₁(X)＝1+X+X ⁴，

φ ₃(X)＝1+X+X ²+X ³+X ⁴，

φ ₅(X)＝1+X+X ²，

The generator polynomial obtaining (15,5) BCH code is:

g(X)＝φ ₁(X)·φ ₃(X)·φ ₅(X)＝1+X+X ²+X ⁴+X ⁵+X ⁸+X ¹⁰

According to the expression-form of generator polynomial g (X), can design coding and decoding circuit as shown in Figure 1, wherein square represents register, the expression modular two addition device with plus sige inside circle, i.e. XOR gate.Can find out, traditional BCH code coding needs through 10 registers, and therefore in the synchronous digital circuit of clock control, need 5 clock cycle shift register all could be sent in 5 bit data positions and complete coding, speed is slower.And be not suitable for high speed Bose-Chaudhuri-Hocquenghem Code circuit.

Summary of the invention

The invention provides the coding circuit method for designing of one (15,5) BCH code, greatly can shorten the scramble time, not by the restriction of clock cycle, coding rate improves greatly.

According to one embodiment of present invention, provide the coding circuit method for designing of one (15,5) BCH code, this coding circuit method for designing comprises: according to this (15,5) generator polynomial of BCH code, there is the serial encoding circuitry of the register of 10 series connection; According to this serial encoding circuitry, be respectively each register in serial encoding circuitry, the first relational expression between the redundancy check bit that after redundancy check bit that after obtaining input the i-th+1 information bit, it stores and input i-th information bit, each register memory stores up, the i-th+1 information bit of input, i≤4 and be nonnegative integer; According to the first relational expression, be respectively each register in serial encoding circuitry, the redundancy check bit that when obtaining redundancy check bit of its storage after inputting whole 5 information bits and do not input any information bit, each register memory stores up, the second relational expression of whole 5 information bits; According to the second relational expression, construct with 5 information bits be input, 10 redundancy check bits are the parallel encoding circuit exported.

Alternatively, the redundancy check bit not inputting each register memory storage during any information bit is all set to 0.

Alternatively, the step obtaining the second relational expression according to the first relational expression comprises: by the first relational expression vectorization obtained for each register in serial encoding circuitry, thus obtain represent input the i-th+1 information bit after the vector of the redundancy check bit that 10 registers store, input after the vector of redundancy check bit that stores of 10 registers and input i-th information bit the i-th+1 information bit between the primary vector relational expression of relation; According to primary vector relational expression, obtain the secondary vector relational expression of the vector of the redundancy check bit that 10 registers store after representing whole 5 information bits of input and relation when not inputting any information bit between the vector of the redundancy check bit that 10 registers store, whole 5 information bits; From secondary vector relational expression, obtain the second relational expression of each register corresponded in serial encoding circuitry.

The redundancy check bit that after the present invention's redundancy check bit that first draw input the i-th+1 information bit from serial encoding circuitry after, each register stores and input i-th information bit, each register memory stores up, relation between the i-th+1 information bit of input, and then the redundancy check bit that the redundancy check bit that after drawing whole 5 information bits of input, each register stores stores up with each register memory when not inputting any information bit, the relation of whole 5 information bits, this relation is exactly the relation of 10 redundancy check bits and 5 information bits, thus can construct with 5 information bits as input, 10 redundancy check bits are the parallel encoding circuit exported.Compared with the serial encoding circuitry of prior art, parallel circuit is adopted to replace traditional tandem coding solution, can not by the restriction of clock cycle, greatly shorten the scramble time, coding rate improves greatly.

Accompanying drawing explanation

By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious.

Fig. 1 is the coding circuit of (15,5) BCH code of prior art;

Fig. 2 is the serial encoding circuitry first constructed of (15,5) BCH code of an example of coding circuit as the present invention (15,5) BCH code;

Fig. 3 is the parallel encoding circuit finally constructed of (15,5) BCH code of an example of coding circuit as the present invention (15,5) BCH code;

Fig. 4 is the flow chart of the coding circuit method for designing of (15,5) according to an embodiment of the invention BCH code.

Embodiment

Embodiments of the invention are described below in detail.

The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.

The invention provides the coding circuit method for designing of one (15,5) BCH code, wherein the figure place of information bit is 5, and the total bit after coding is 15, and the figure place of redundancy check bit is 10.As shown in Figure 4, the method comprises:

In step S1, according to the generator polynomial of this (15,5) BCH code, there is the serial encoding circuitry of the register of 10 series connection.

With (15,5) BCH code for example, Fig. 2 shows a serial encoding circuitry with the register of 10 series connection constructed, and it can construct by the mode of prior art.With the generator polynomial of (15,5) BCH code described above be:

g(X)＝φ ₁(X)·φ ₃(X)·φ ₅(X)＝1+X+X ²+X ⁴+X ⁵+X ⁸+X ¹⁰

Situation be example, construct the serial encoding circuitry shown in Fig. 2.In fact, Fig. 2 is the connection layout specialized of Fig. 1.This circuit comprises S ₀~ S ₉ten registers.

Concrete, during circuit working, clock signal c1k controls ten register S ₀~ S ₉.When rising edge clock arrives, the output of ten registers sends into next stage respectively, produces the output of next stage simultaneously.After information bit has inputted, the value of preserving in 10 registers has been exactly the value of 10 bit check positions.Together with the data of preserving in 10 registers input with the external world, cyclic shift.Understand according to algebraic method, ten bit check positions are exactly the information bit multinomial that information bit is formed, and are then multiplied by X ¹⁰(output of input information and rightmost register together computing is equivalent to be multiplied by X ¹⁰), then the coefficient of the residue obtained divided by the generator polynomial g (X) that BCH is corresponding.

In step S2, according to this serial encoding circuitry, be respectively each register in serial encoding circuitry, the first relational expression between the redundancy check bit that after redundancy check bit that after obtaining input the i-th+1 information bit, it stores and input i-th information bit, each register memory stores up, the i-th+1 information bit of input, i≤4 and be nonnegative integer.

Still for the example of Fig. 2, can be each register in 10 registers of Fig. 2, obtain the first relational expression as follows:

$\left\{\begin{array}{c}{S}_9^{i+1}=S_8^i\\ S_8^{i+1}=S_9^i+S_7^i\\ S_7^{i+1}=S_6^i\\ S_6^{i+1}=S_5^i\\ S_5^{i+1}=S_9^i+S_4^i\\ S_4^{i+1}=S_9^i+S_3^i\\ S_3^{i+1}=S_2^i\\ S_2^{i+1}=S_9^i+S_1^i\\ S_1^{i+1}=S_9^i+S_0^i\\ S_0^{i+1}=S_9^i+u_{i+1}\end{array}\right.---\left(1\right)$

Wherein, the redundancy check bit stored in each register S0 ~ S9 after representing input i-th information bit, each register S after inputting the i-th+1 information bit ₀~ S ₉the redundancy check bit of interior storage, u _i+1represent the i-th+1 information bit of input.As shown in Figure 2, register S ₉after input the i-th+1 information bit, its storing value is last register S ₈pass over, last register S should be equaled ₈storing value after input i-th information bit, therefore register S ₈after input the i-th+1 information bit, its storing value is last register S ₇the value passed over adds register S ₉the value fed back and, therefore adding here is all that finger print two adds.

In step s3, according to the first relational expression (1), be respectively each register in serial encoding circuitry, the redundancy check bit that when obtaining redundancy check bit of its storage after inputting whole 5 information bits and do not input any information bit, each register memory stores up, second relational expression (2) of whole 5 information bits.Particularly:

In sub-step S31, by the first relational expression vectorization obtained for each register in serial encoding circuitry, thus obtain represent input the i-th+1 information bit after the vector of the redundancy check bit that 10 registers store, input after the vector of redundancy check bit that stores of 10 registers and input i-th information bit the i-th+1 information bit between the primary vector relational expression of relation.

Still with above-mentioned (15,5) BCH code be example for example, the first relational expression (1) is rewritten into primary vector relational expression (I):

$S^{i+1}=A[S^i\⊕G_{,i+1}]---\left(I\right)$

S ⁱthe vector of the redundancy check bit of 10 register storages after expression input i-th information bit, S ⁱ⁺¹the vector of the redundancy check bit of 10 register storages after expression input the i-th+1 information bit.Still with aforementioned (15,5) BCH code for example:

$S^i=[S_9^i,S_8^i,......S_0^i]$

$S^{i+1}=[S_9^{i+1},S_8^{i+1},......S_0^{i+1}]$

The coefficient matrix of matrix A for being obtained by each coefficient in above formula (1).Matrix A is:

$A={\left[\begin{array}{cccccccccc}0& 1& 0& 0& 0& 0& 0& 0& 0& 0\\ 1& 0& 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 0\\ 1& 0& 0& 0& 0& 1& 0& 0& 0& 0\\ 1& 0& 0& 0& 0& 0& 1& 0& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 1& 0& 0\\ 1& 0& 0& 0& 0& 0& 0& 0& 1& 0\\ 1& 0& 0& 0& 0& 0& 0& 0& 0& 1\\ 1& 0& 0& 0& 0& 0& 0& 0& 0& 0\end{array}\right]}_{10\×10}$

G _i+1it is the vector of the i-th+1 information bit of reflection input.It is a column vector, and the first row is the vector of the i-th+1 information bit of input, all the other behaviors 0.If U is the vectorial U=[u of all information bits composition ₀, u ₁..., u ₄],

$G=\left[\begin{array}{c}1\\ 0\\ 0\\ 0\\ 0\\ 0\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right]\·U=\left[\begin{array}{ccccc}{u}_0& u_1& u_2& u_3& u_4\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\\ 0& 0& 0& 0& 0\end{array}\right]$

Wherein G _{, i+1}i-th+1 row of representing matrix.

In sub-step S32, according to primary vector relational expression (I), obtain the secondary vector relational expression of the vector of the redundancy check bit that 10 registers store after representing whole 5 information bits of input and relation when not inputting any information bit between the vector of the redundancy check bit that 10 registers store, whole 5 information bits.

With above-mentioned (15,5) BCH code for example, by primary vector relational expression (I), obtain secondary vector relational expression (II):

$S^5=A[S^4\⊕G_{,5}]=A\left[A\right[S^3\⊕G_{,4}]\⊕G_{,5}]=...=A^5{S}^0\⊕A^5{G}_{,1}\⊕...\⊕A^2{G}_{,4}\⊕{\mathrm{AG}}_{,5}---\left(\mathrm{II}\right)$

S ⁵for the vector of the redundancy check bit of 10 register storages after whole 5 information bits of expression input, S ⁰the vector of the redundancy check bit that 10 registers store during for not inputting any information bit.The redundancy check bit of register memory storage each when not inputting any information bit all can be set to 0, now S ⁰be 0, above formula (II) becomes:

$S^5=A^5{G}_{,1}\⊕\·\·\·\⊕A^2{G}_{,4}\⊕{\mathrm{AG}}_{,5}---(\mathrm{II}-1)$

In step S33, from secondary vector relational expression, obtain the second relational expression of each register corresponded in serial encoding circuitry.

With above-mentioned (15,5) BCH code for example, above formula (II-1) is launched to obtain following expression, namely corresponds to the second relational expression of each register in serial encoding circuitry:

$\left\{\begin{array}{c}{S}_9^4=u_1+u_3+u_4\\ S_8^5=u_0+u_2+u_3\\ S_7^5=u_2+u_3+u_4\\ S_6^5=u_1+u_2+u_3\\ S_5^5=u_0+u_1+u_2\\ S_4^5=u_0+u_3+u_4\\ S_3^5=u_1+u_2+u_4\\ S_2^5=u_0+u_1+u_3\\ S_1^5=u_0+u_1+u_2+u_3+u_4\\ S_0^5=u_0+u_2+u_4\end{array}\right.---\left(2\right)$

Step S3 also can perform not according to the mode of above-mentioned S31-S33.Such as, directly from the first relational expression (1), namely

$\left\{\begin{array}{c}{S}_9^{i+1}=S_8^i\\ S_8^{i+1}=S_9^i+S_7^i\\ S_7^{i+1}=S_6^i\\ S_6^{i+1}=S_5^i\\ S_5^{i+1}=S_9^i+S_4^i\\ S_4^{i+1}=S_9^i+S_3^i\\ S_3^{i+1}=S_2^i\\ S_2^{i+1}=S_9^i+S_1^i\\ S_1^{i+1}=S_9^i+S_0^i\\ S_0^{i+1}=S_9^i+u_{i+1}\end{array}\right.---\left(1\right)$

, by deriving, will be expressed as u ₀-u ₄function, namely obtain (2), only process is complicated a little.

Herein, plus sige all represents the addition on mould two, namely equals binary XOR

In step S4, according to the second relational expression, construct with 5 information bits be input, 10 redundancy check bits are the parallel encoding circuit exported.

With above-mentioned (15,5) BCH code for example, according to above-mentioned (2), construct parallel encoding circuit as shown in Figure 3.

Suppose that information bit to be encoded is for (11000), corresponding multinomial is U (X)=1+X, X ¹⁰u (X) is divided by generator polynomial g (X)=1+X+X ²+ X ⁴+ X ⁵+ X ⁸+ X ¹⁰obtain residue:

b(X)＝1+X ³+X ⁴+X ⁶+X ⁸+X ⁹

Therefore coding obtains (1001101011|11000), 10, the left side is redundancy check bit, and 5, the right is information bit,

Can be correct according to formula (2) checking derivation result.

Although with the generator polynomial of (15,5) BCH code be above:

g(X)＝φ ₁(X)·φ ₃(X)·φ ₅(X)＝1+X+X ²+X ⁴+X ⁵+X ⁸+X ¹⁰

For example describes the design process of coding circuit of the present invention, but those skilled in the art are known, if g (X) is other, the present invention is applicable equally.

The present invention proposes the coding circuit method for designing of one (15,5) BCH code, adopts parallel circuit to replace traditional tandem coding solution, can not by the restriction of clock cycle, and greatly shorten the scramble time, coding rate improves greatly.

Claims (3)

1. the coding circuit method for designing of one kind (15,5) BCH code, this coding circuit method for designing comprises:

According to the generator polynomial of this (15,5) BCH code, there is the serial encoding circuitry of the register of 10 series connection;

According to this serial encoding circuitry, be respectively each register in serial encoding circuitry, the first relational expression between the redundancy check bit that after redundancy check bit that after obtaining input the i-th+1 information bit, it stores and input i-th information bit, each register memory stores up, the i-th+1 information bit of input, i≤4 and be nonnegative integer;

According to the first relational expression, be respectively each register in serial encoding circuitry, the redundancy check bit that when obtaining redundancy check bit of its storage after inputting whole 5 information bits and do not input any information bit, each register memory stores up, the second relational expression of whole 5 information bits;

According to the second relational expression, construct with 5 information bits be input, 10 redundancy check bits are the parallel encoding circuit exported.

2. coding circuit method for designing according to claim 1, the redundancy check bit wherein not inputting each register memory storage during any information bit is all set to 0.

3. coding circuit method for designing according to claim 1, wherein comprises according to the step that the first relational expression obtains the second relational expression:

By the first relational expression vectorization obtained for each register in serial encoding circuitry, thus obtain represent input the i-th+1 information bit after the vector of the redundancy check bit that 10 registers store, input after the vector of redundancy check bit that stores of 10 registers and input i-th information bit the i-th+1 information bit between the primary vector relational expression of relation;

According to primary vector relational expression, obtain the secondary vector relational expression of the vector of the redundancy check bit that 10 registers store after representing whole 5 information bits of input and relation when not inputting any information bit between the vector of the redundancy check bit that 10 registers store, whole 5 information bits;

From secondary vector relational expression, obtain the second relational expression of each register corresponded in serial encoding circuitry.