CN104505125A - Multi-channel SRAM single-particle test method and device - Google Patents
Multi-channel SRAM single-particle test method and device Download PDFInfo
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Abstract
The invention provides a multi-channel SRAM single particle testing device, which comprises: the test board and the main control board; the test board is used for fixing and connecting a chip to be tested; the main control board is used for controlling the irradiation test system and reading and recording data in the chip to be tested. The device can simultaneously test the single event effect of a plurality of SRAM devices to obtain the characteristic parameters of the single event effect, and improve the accuracy of the estimation of the single event effect resistance of the tested device; the magnitude of the working current of the tested device can be detected in real time, and the latch-up effect is prevented.
Description
Technical field
The present invention relates to device reliability field, especially, relate to a kind of single-particle method of testing and device.
Background technology
Because SRAM memory has the advantages such as access speed is fast, in spacecraft development, a large amount of SRAM that uses comes store configuration information, test data etc.And spacecraft flies in space, be in the radiation environment of charged particle formation always, high energy proton in space radiation environment, heavy ion, neutron in atmospheric environment can cause the SRAM device generation single particle effect in spacecraft, make the data stored in SRAM that random change occur, affect the reliability of device, so the ability direct relation of SRAM device anti-single particle effect the stability of spacecraft in spacecraft.
Existing single-particle test macro, does not have the special test carried out for SRAM device, when testing SRAM device single particle effect, can not the latch-up of simultaneously chip monitoring, and also efficiency is not high.
Therefore, a kind of method that effectively can detect single particle effect in SRAM is needed badly.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of hyperchannel SRAM single-particle proving installation and method, multi-disc sram chip can be tested efficiently simultaneously, save the test duration, in the process of test, the latch-up of all right hardware detection chip, reduces electromagnetic interference (EMI).This device comprises:
Test board and master control borad; Wherein,
Test board is for fixing, connecting chip to be measured;
Master control borad for controlling irradiation test macro, and reads, the data recorded in chip to be measured.Wherein, described master control borad comprises:
Power module, for being converted into the different voltages of each module by input power;
Communication module, for receiving external signal;
Cache module, for readwrite tests data;
Main control module, for realizing the order of control signal, for each module provides sequential control; Level switch module, for changing chip under test interface level and FPGA interface level; First interface module, for connecting master control borad and test board.
Wherein, described test board comprises the second interface module and test fixture; Wherein,
Described second interface module, for connecting master control borad and test board;
Described test fixture provides fixing for SRAM to be measured.
The quantity of described test fixture is N, and wherein N is 1,2,3,4 ... Deng.
Wherein, described test board and control panel vertically parallel placement; Described test board and control panel dig dead slot, for placing data flat cable; The quantity of described dead slot is N, and wherein N is 0,1,2,3,4 ... Deng.
Accordingly, present invention also offers a kind of hyperchannel SRAM single-particle method of testing, comprising:
A. test data is write in chip to be measured, and read the data in chip to be measured, with the Data Comparison of write;
B. two groups of errorless rear unlatching irradiation of Data Comparison;
C., in irradiation process, the data recorded in chip to be measured are constantly read;
D. measurement data and the data preset are contrasted, record not identical data.
The invention provides a kind of hyperchannel SRAM device single particle effect test macro based on FPGA, this system can realize testing multiple SRAM device single particle effect simultaneously, obtain single particle effect characteristic parameter, improve the accuracy that measured device anti-single particle effect capability is estimated.This system also can detect the size of measured device working current in real time, prevents the generation of latch-up.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is hyperchannel SRAM single-particle test system hardware block diagram in the present invention;
Fig. 2 is hyperchannel SRAM single-particle testing system board position relationship schematic diagram in the present invention;
In figure, same or analogous Reference numeral represents same or analogous parts.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The invention provides a kind of hyperchannel SRAM single-particle proving installation, this device comprises: test board and master control borad; Wherein,
Test board is for fixing, connecting chip to be measured; Master control borad for controlling irradiation test macro, and reads, the data recorded in chip to be measured.
Wherein, described master control borad comprises:
Power module, for being converted into the different voltages of each module by input power; Communication module, for receiving external signal; Cache module, for readwrite tests data; Main control module, for realizing the order of control signal, for each module provides sequential control; Level switch module, for changing chip under test interface level and FPGA interface level; First interface module, for connecting master control borad and test board.
Wherein, described test board comprises the second interface module and test fixture; Wherein, described second interface module, for connecting master control borad and test board; Described test fixture provides fixing for SRAM to be measured.The quantity of described test fixture is N, and wherein N is 1,2,3,4 ... Deng.
Wherein, described test board and control panel vertically parallel placement; Described test board and control panel dig dead slot, for placing data flat cable; The quantity of described dead slot is N, and wherein N is 0,1,2,3,4 ... Deng.
Accordingly, present invention also offers a kind of hyperchannel SRAM single-particle method of testing, comprising:
A. test data is write in chip to be measured, and read the data in chip to be measured, with the Data Comparison of write;
B. two groups of errorless rear unlatching irradiation of Data Comparison;
C., in irradiation process, the data recorded in chip to be measured are constantly read;
D. measurement data and the data preset are contrasted, record not identical data.
The invention provides a kind of hyperchannel SRAM device single particle effect test macro based on FPGA, this system can realize testing multiple SRAM device single particle effect simultaneously, obtain single particle effect characteristic parameter, improve the accuracy that measured device anti-single particle effect capability is estimated.This system also can detect the size of measured device working current in real time, prevents the generation of latch-up.
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.In specific embodiment of the invention, power management chip selects TPS650532, differential amplifier chip adopts MAX4173, modulus conversion chip adopts ADS7886, USB control chip adopts CY68013A, buffer memory SRAM adopts IS61WV102416BLL, FPGA to adopt altera corp CycloneIII series EP3C40F484C7, and level transferring chip adopts SN74VC16T245.
In the present embodiment, input power is transformed into the voltages such as 3.3V, 2.5V, 1.2V for each module by the power module of master control borad through power management chip.Because interface module one needs to provide power supply to chip under test, so the power supply of supply interface module one need through a differential amplifier chip and relay.Differential amplifier chip is for extracting chip under test electric current used, and the current signal of extraction is converted into digital signal through analog-to-digital conversion chip, if this digital signal is larger than default maximum current value, then disconnects relay, cuts off the power supply of chip under test.
Communication module adopts USB control chip, makes to be communicated by USB interface between host computer with master control borad, controls the break-make of whole test.
Cache module is made up of two panels SRAM, due to USB control chip rate limit, cache module keeps in reading and writing data among tested sram chip, namely when starting to test, cache module keeps in the data that will write in tested sram chip, in test process, cache module keeps in the data read from tested sram chip.
Main control module is made up of FPGA and configuration circuit thereof, receives the control signal from host computer, and providing Control timing sequence for other each modules normally work, coordinate the work between each module, is the core component of whole system plate.
Level switch module is made up of multi-disc level transferring chip, chip under test interface level and FPGA interface level is changed.The interface module one of master control borad is connected with the interface module two of test board, makes to communicate between master control borad with test board, test signal is delivered to test board, and return the test data on test board.
Test fixture 1 for SRAM to be measured provides fixing, during test, selects chip to be measured by chip selection signal to test fixture 8, accelerates testing efficiency, convenient test.
In test process, the position relationship of master control borad and test board as shown in Figure 2.1 is master control borad, and 2 is test board, digs out dead slot 5 and dead slot 7 in test board 2 side, and data flat cable 6 and data flat cable 8 are passed two dead slot 5 and 7 connecting interfaces 4 and 9, interfaces 3 and 10, and radiation source 11 is got on the chip to be measured in test board 2 front.This kind of connected mode can avoid radiation source to the interference of chip data on master control borad, and data flat cable position in line process is relatively stable, facilitates wiring, the error in data that prevents winding displacement electromagnetic interference (EMI) from causing.
When starting to test, host computer is transmitted control signal to main control module by communication module, and to cache module stored in test data; Then test data writes in chip to be measured by main control module, has write the data in rear reading chip to be measured, with the Data Comparison of write, and errorless rear unlatching irradiation.In irradiation process, main control module constantly reads the data in chip to be measured, and by it stored in cache module, imports in host computer through communication module.In host computer, the data passed back and the data preset are contrasted, if not identical, then record.
Single-particle pick-up unit provided by the invention can utilize hardware detection chip to occur latch-up, and adopts hardware cut-off current, prevents chip damaged; And test macro can test many chips to be measured, raises the efficiency simultaneously; Meanwhile, the putting position relation of testing circuit board can avoid radiation source to the interference of chip data on master control borad, and data flat cable position in line process is relatively stable, facilitates wiring, the error in data that prevents winding displacement electromagnetic interference (EMI) from causing.
Above-described embodiment is the present invention's preferably embodiment; but embodiments of the present invention are not restricted to the described embodiments; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (8)
1. a hyperchannel SRAM single-particle proving installation, comprising: test board and master control borad;
Wherein,
Test board is for fixing, connecting chip to be measured;
Master control borad for controlling irradiation test macro, and reads, the data recorded in chip to be measured.
2. single-particle proving installation according to claim 1, is characterized in that, described master control borad comprises:
Power module, for being converted into the different voltages of each module by input power;
Communication module, for receiving external signal;
Cache module, for readwrite tests data;
Main control module, for realizing the order of control signal, for each module provides sequential control; Level switch module, for changing chip under test interface level and FPGA interface level; First interface module, for connecting master control borad and test board.
3. single-particle proving installation according to claim 1, is characterized in that, described test board comprises the second interface module and test fixture; Wherein,
Described second interface module, for connecting master control borad and test board;
Described test fixture provides fixing for SRAM to be measured.
4. single-particle proving installation according to claim 3, is characterized in that, the quantity of described test fixture is N, and wherein N is 1,2,3,4 ... Deng.
5. single-particle proving installation according to claim 1, is characterized in that, described test board and control panel be parallel placement vertically.
6. single-particle proving installation according to claim 1, is characterized in that, described test board and control panel have dug dead slot, for placing data flat cable.
7. single-particle proving installation according to claim 1, is characterized in that, the quantity of described dead slot is N, and wherein N is 0,1,2,3,4 ... Deng.
8. a hyperchannel SRAM single-particle method of testing, comprising:
A. test data is write in chip to be measured, and read the data in chip to be measured, with the Data Comparison of write;
B. two groups of errorless rear unlatching irradiation of Data Comparison;
C., in irradiation process, the data recorded in chip to be measured are constantly read;
D. measurement data and the data preset are contrasted, record not identical data.
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| CN105223494A (en) * | 2015-09-25 | 2016-01-06 | 中国人民解放军国防科学技术大学 | A kind of system single particle effect detection method based on parallel testing and system |
| CN106841845A (en) * | 2016-12-15 | 2017-06-13 | 华中师范大学 | A kind of electronic device radiation resistance method of testing and system |
| CN108982826A (en) * | 2018-09-28 | 2018-12-11 | 广东工业大学 | Test device and test method of a kind of zebra fish detection nano particle to embryotoxicity |
| CN109991531A (en) * | 2019-03-28 | 2019-07-09 | 西北核技术研究所 | Atmospheric neutron single particle effect section gauge system and method under the conditions of low probability |
| CN110888042A (en) * | 2019-12-09 | 2020-03-17 | 青岛歌尔微电子研究院有限公司 | Method and equipment for testing ASIC chip wafer and computer storage medium |
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