CN104503164A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN104503164A CN104503164A CN201410836490.9A CN201410836490A CN104503164A CN 104503164 A CN104503164 A CN 104503164A CN 201410836490 A CN201410836490 A CN 201410836490A CN 104503164 A CN104503164 A CN 104503164A
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- 229910004205 SiNX Inorganic materials 0.000 description 1
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- 229910003087 TiOx Inorganic materials 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses an array substrate, a manufacturing method of the array substrate and a display device. The embodiment of the invention provides an array substrate, wherein a plurality of pixel structures are arranged on a substrate of the array substrate; the shielding electrode, the lower pole plate of the storage capacitor and the lower pole plate of the scanning line are positioned on the same layer of the storage capacitor to multiplex part of the shielding electrode; the first insulating layer covers the layer where the lower electrode plate of the storage capacitor is located; the upper plate of the storage capacitor is arranged on the first insulating layer and is positioned on the same layer as the data line, and the upper plate of the storage capacitor at least has a part overlapped with the lower plate of the storage capacitor, and the overlapped part divides the pixel structure into at least two light-transmitting areas. According to the embodiment of the invention, the shape of the storage capacitor is changed, the light-transmitting area is divided into at least two light-transmitting areas, and the light-impermeable areas are dispersed, so that the problem of grid feeling caused by the large-area light-impermeable areas is effectively avoided.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
In the dot structure of general liquid crystal display, the time of pixel data to next update must be stored by configuration store electric capacity.Be illustrated in figure 1 dot structure schematic diagram in prior art, this dot structure comprises transmission region 101 and lightproof area 102, and lightproof area 102 is the zones of opacity formed by cabling and memory capacitance pole plate etc.Due to the normally two-layer lighttight metal level of memory capacitance pole plate, therefore the configuration of described memory capacitance makes the area of transmission region 101 in dot structure reduce, and then causes the aperture opening ratio of panel to reduce.
For existing a kind of total reflection display unit, when being used as electronic tag, owing to usually carrying out static state display, do not need to refresh at a high speed, therefore, general needs adopts lower driving frequency, as 20Hz, 1Hz etc., meanwhile, remain on set voltage in order to ensure pixel potential, generally take the method for the memory capacitance increased in dot structure to keep current potential.Under normal circumstances, the area of two metal levels will be increased for increasing memory capacitance, and then the area in light tight district is increased, cause the aperture opening ratio of panel lower, have a strong impact on the display effect of product.In addition, be illustrated in figure 2 the display view of viewing area in prior art, black region is lightproof area, white portion is transmission region, because the area of memory capacitance pole plate is larger, cause light tight region comparatively concentrated, make viewing area have obvious grid sense, reduce the visual experience of user.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, has the technical matters of obvious grid sense in order to solve viewing area in prior art.
A kind of array base palte that the embodiment of the present invention provides, comprising:
A kind of array base palte that the embodiment of the present invention provides, comprising:
Substrate, described substrate is provided with multi-strip scanning line and data line; Many described sweep traces and data line intersection limit multiple dot structure;
Guarded electrode, is positioned at least one lateral edges of described dot structure and is positioned at same layer with described sweep trace;
The bottom crown of memory capacitance, bottom crown and the described sweep trace of described memory capacitance are positioned at same layer, and the bottom crown of described memory capacitance at least guarded electrode described in multiplexing part;
First insulation course, covers the layer at described memory capacitance bottom crown place;
The top crown of memory capacitance, is arranged on described first insulation course, and with described data line bit in same layer;
The top crown of described memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance;
Described dot structure is divided at least two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
The embodiment of the present invention provides a kind of display device, comprises the array base palte described in the claims, and the subtend substrate be oppositely arranged with described array base palte.
The embodiment of the present invention provides a kind of method for making of array base palte, comprising:
One substrate is provided;
Form the bottom crown of sweep trace, guarded electrode and memory capacitance over the substrate, the bottom crown of described memory capacitance, guarded electrode and sweep trace are positioned at same layer, and the bottom crown of described memory capacitance at least guarded electrode described in multiplexing part;
Form the first insulation course, cover the layer at the bottom crown place of described memory capacitance;
Described first insulation course is formed top crown and the data line of memory capacitance, and the top crown of described memory capacitance and described data line bit are in same layer;
Described sweep trace intersects with described data line and limits multiple dot structure;
The top crown of described memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance; Described dot structure is divided at least two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
The embodiment of the present invention provides a kind of array base palte, and the substrate of this array base palte has multiple dot structure; The bottom crown of guarded electrode, memory capacitance and sweep trace are positioned at the bottom crown multiplexing part guarded electrode of same layer memory capacitance; First insulation course covers the layer at memory capacitance bottom crown place; The top crown of memory capacitance is arranged on described first insulation course, and with data line bit in same layer, the top crown of memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance, and dot structure is divided at least two photic zones by the part of this overlap.Photic zone, by changing by the shape of memory capacitance, is divided at least two photic zones by the embodiment of the present invention, has disperseed light tight district, thus effectively prevent the grid sense problem caused due to large-area light tight district.
Accompanying drawing explanation
Fig. 1 is dot structure schematic diagram in prior art;
Fig. 2 is the display view of viewing area in prior art;
A dot structure schematic diagram on the array base palte that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 is the sectional structure schematic diagram along AA ' cross section in Fig. 3;
The display view of the array base palte viewing area that Fig. 5 provides for the embodiment of the present invention;
A kind of display device schematic diagram that Fig. 6 provides for the embodiment of the present invention;
The schematic flow sheet of the method for making of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention;
The method for making particular flow sheet of the array base palte that Fig. 8 provides for the embodiment of the present invention;
Fig. 9 is the embodiment of the present invention first patterned metal layer schematic diagram;
Figure 10 is the dot structure schematic diagram that the embodiment of the present invention forms the second patterned metal layer;
Figure 11 is the embodiment of the present invention second patterned metal layer schematic diagram.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
The array base palte that the embodiment of the present invention provides comprises multiple dot structure, understands the present invention particularly for ease of clearer, below be mainly described for the dot structure of on array base palte.
A dot structure schematic diagram on the array base palte that Fig. 3 provides for the embodiment of the present invention, Fig. 4 is the sectional structure schematic diagram along AA ' cross section in Fig. 3.Set forth embodiments of the invention below in conjunction with shown in Fig. 3 and 4, because Fig. 4 is the sectional structure schematic diagram in AA ' cross section, therefore part-structure on array base palte is not shown in Figure 4.
The array base palte that the embodiment of the present invention provides comprises:
Substrate 301, substrate 301 is provided with multi-strip scanning line 302a and data line 305b; Multi-strip scanning line 302a and data line 305b intersection limits multiple dot structure;
Guarded electrode 302b, is positioned at least one lateral edges of dot structure and is positioned at same layer with sweep trace 302a;
The bottom crown 302c of memory capacitance, is positioned at same layer with sweep trace 302a, and the bottom crown 302c of memory capacitance at least multiplexing part guarded electrode 302b;
First insulation course 303, covers the layer at described memory capacitance bottom crown place;
The top crown 305a of memory capacitance, is arranged on described first insulation course 303, and is positioned at same layer with described data line 305b;
The top crown 305a of described memory capacitance at least has the part overlapping with the bottom crown 302c of described memory capacitance;
Described dot structure is divided at least two photic zones by the part that the top crown 305a of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
In conjunction with reference to figure 3 and Fig. 4, particularly, the array base palte that the embodiment of the present invention provides is made up of different Rotating fields, specifically can comprise: substrate 301, substrate 301 is provided with the first patterned metal layer 302, first patterned metal layer 302 to comprise: the bottom crown 302c of sweep trace 302a, guarded electrode 302b, memory capacitance; Guarded electrode 302b is positioned at the edge of dot structure, it should be noted that, in the present embodiment, show guarded electrode and be positioned at edge situation, but in other embodiments of the present invention, can not regard this as a limit, such as, guarded electrode also can be positioned at any at least one lateral edges of dot structure.The bottom crown 302c of memory capacitance comprises the part being positioned at dot structure edge and the part being positioned at dot structure zone line, wherein, be positioned at the fractional reuse partly shielding effect electrode 302b at dot structure edge, namely part is positioned at first patterned metal layer 302 at dot structure edge, both as guarded electrode, simultaneously also as the bottom crown of memory capacitance; First patterned metal layer 302 is provided with the first insulation course 303, first insulation course 303 is provided with semiconductor layer 304, semiconductor layer 304 is provided with the second patterned metal layer 305, second patterned metal layer 305 to comprise: the top crown 305a of memory capacitance and data line 305b; The top crown 305a of memory capacitance at least has the part overlapping with the bottom crown 302c of described memory capacitance, and dot structure is divided into photic zone p1 and photic zone p2 by the part of this overlap; Second patterned metal layer 305 is provided with on the second insulation course 306, second insulation course 306 and is provided with transparency conducting layer 307, this transparency conducting layer 307 comprises pixel electrode 307a, and the top crown 305a of pixel electrode 307a and memory capacitance is electrically connected.
As shown in Figure 3, the part that in the embodiment of the present invention, the top crown 305a of memory capacitance is overlapping with the bottom crown 302c of memory capacitance is " work " herringbone pattern; Described " work " herringbone pattern and data line 305b are arranged in the same way, and two horizontal lines and sweep trace 302a up and down namely in " work " herringbone pattern be arranged in parallel, and a middle vertical line and data line 305b be arranged in parallel.Because the top crown 305a of memory capacitance and data line 305b is positioned at same layer, adopt such " work " herringbone pattern design, can make to maintain suitable distance between the top crown 305a of memory capacitance and data line 305b, thus avoid the phenomenon of short circuit.
In the embodiment of the present invention, the part that the top crown 305a of memory capacitance is overlapping with the bottom crown 302c of memory capacitance is " work " herringbone pattern, thus the photic zone of dot structure is divided into photic zone p1 and photic zone p2, with only have compared with a photic zone in prior art, disperse light tight district in the embodiment of the present invention, thus effectively prevent the grid sense problem caused due to large-area light tight district.And, in the embodiment of the present invention, due to multiplexing guarded electrode 302b and memory capacitance bottom crown 302c, do not need to make separately guarded electrode and memory capacitance bottom crown, the area shared by the first patterned metal layer 302 on substrate can be reduced, decrease light tight region, increase the aperture opening ratio of pixel.As shown in Figure 5, black region is lightproof area, white portion is transmission region, because the upper bottom crown of memory capacitance becomes " work " herringbone pattern, disperseed lightproof area, the array base palte adopting the embodiment of the present invention to provide is in the process of display, and grid sense obviously makes moderate progress, and reduce the area in light tight region, add substrate transmitance.
In the embodiment of the present invention, size for photic zone p1 and photic zone p2 is not specifically limited, the two can be equal or unequal, and namely the area of photic zone p1 equals the area of photic zone p2, the area of photic zone p1 all can slightly larger than the area of photic zone p1 slightly larger than the area of photic zone p2 or the area of photic zone p2.Preferably, the area of photic zone p1 and the area equation of photic zone p2, be so just evenly distributed photic zone, while the sense of elimination grid, can improve the visual experience of user further.
In the embodiment of the present invention, the photic zone of dot structure is divided into the number of photic zone to be not specifically limited by the part overlapping with the bottom crown 302c of memory capacitance for the top crown 305a of memory capacitance.The part only specifically listing the top crown 305a of memory capacitance in above-described embodiment overlapping with the bottom crown 302c of memory capacitance becomes " work " herringbone pattern, and the photic zone of dot structure is divided into the situation of two photic zones.Alternatively, the part that the top crown 305a of memory capacitance is overlapping with the bottom crown 302c of memory capacitance also can become
now, the photic zone of dot structure is divided into three photic zones; Or the part that the top crown 305a of memory capacitance is overlapping with the bottom crown 302c of memory capacitance also can become
now, the photic zone of dot structure is divided into four photic zones.
Preferably, the dot structure in the embodiment of the present invention also comprises at least one grid be connected with described sweep trace, and with data line bit in the source electrode of same layer and drain electrode, memory capacitance top crown is electrically connected with drain electrode.As shown in Figure 3 and Figure 4, the first patterned metal layer 302 also comprises: two grids, is respectively first grid g1 and second grid g2, correspondingly with first grid g1 and second grid g2 on the first insulation course 303 is provided with two semiconductor layers be separated from each other 304.Second patterned metal layer 305 also comprises: the first source electrode s1, the second source electrode s2, the first drain electrode d1, the second drain electrode d2, wherein the first source electrode s1 is electrically connected with data line 305b, first drain electrode d1 is electrically connected with the second source electrode s1, and the second drain electrode is connected with pixel electrode point.Adopt this double-gate structure thin film transistor (TFT), the breadth length ratio of thin film transistor (TFT) can be reduced, reduce leakage current.The present invention does not limit gate data, namely in some embodiments of the invention, can adopt separately single grid structure, also can adopt multi-gate structure.
The embodiment of the present invention provides a kind of array base palte, the substrate of this array base palte is provided with multi-strip scanning line and data line; Multi-strip scanning line and data line intersection limit multiple dot structure; Bottom crown and the sweep trace of guarded electrode, memory capacitance are positioned at same layer, and guarded electrode is positioned at least one lateral edges of dot structure, the bottom crown of memory capacitance is positioned at the part zone line of dot structure edge and dot structure, is positioned at the bottom crown multiplexing part guarded electrode of the memory capacitance at dot structure edge; First insulation course covers the layer at memory capacitance bottom crown place; The top crown of memory capacitance is arranged on described first insulation course, and with data line bit in same layer, the top crown of memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance, and dot structure is divided at least two photic zones by the part of this overlap.The embodiment of the present invention is by changing by the shape of memory capacitance, photic zone is divided at least two photic zones, disperse light tight district, thus effectively prevent the grid sense problem caused due to large-area light tight district, and, in the embodiment of the present invention, due to multiplexing guarded electrode and memory capacitance bottom crown, do not need to make separately guarded electrode and memory capacitance bottom crown, the area shared by the first patterned metal layer on substrate can be reduced, decrease light tight region, increase the aperture opening ratio of pixel.。
A kind of display device schematic diagram that Fig. 6 provides for the embodiment of the present invention, comprises the array base palte 601 described in above-described embodiment, and the subtend substrate 602 be oppositely arranged with described array base palte.
Further, this display device also comprises the reflector plate 603 being arranged at described array base palte and deviating from described subtend substrate side.
Array base palte described in the embodiment of the present invention can be thin film transistor (TFT) (Thin Film Transistor, TFT) array base palte, the subtend substrate be oppositely arranged with described array base palte can be colored filter substrate (Color filter, CF), liquid crystal layer, alignment film etc. is provided with between colored filter substrate and thin-film transistor array base-plate.
The schematic flow sheet corresponding to method for making of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention, the method comprises the steps 701 to step 704:
Step 701, provides a substrate;
Step 702, forms the bottom crown of sweep trace, guarded electrode and memory capacitance over the substrate, and the bottom crown of described memory capacitance, guarded electrode and sweep trace are positioned at same layer, and the bottom crown of described memory capacitance at least guarded electrode described in multiplexing part;
Step 703, forms the first insulation course, covers the layer at the bottom crown place of described memory capacitance;
Step 704, described first insulation course is formed top crown and the data line of memory capacitance, and the top crown of described memory capacitance and described data line bit are in same layer; Described sweep trace intersects with described data line and limits multiple dot structure;
The top crown of described memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance; Described dot structure is divided at least two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
The method for making of the array base palte that the embodiment of the present invention provides also can be used in the making of the display of other types, in manufacturing process, by the bottom crown multiplexing part guarded electrode of memory capacitance, and make the top crown of the memory capacitance part overlapping with the bottom crown of memory capacitance that dot structure is divided at least two photic zones, make by the method the array base palte obtained and effectively prevent the light tight district of large area memory capacitance and the grid sense problem caused, and, in the embodiment of the present invention, due to multiplexing guarded electrode and memory capacitance bottom crown, do not need to make separately guarded electrode and memory capacitance bottom crown, the area shared by the first patterned metal layer on substrate can be reduced, decrease light tight region, increase the aperture opening ratio of pixel.
For understanding the embodiment of the present invention further, below in conjunction with Fig. 8, the method for making described in the embodiment of the present invention is specifically described.
Step 801, provides a substrate 301, and this substrate 301 forms the first metal layer; Described the first metal layer adopts the method for magnetron sputtering to prepare by gate metal film, electrode material can be selected according to different device architectures and technological requirement, usual adopted grid line metal has Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo builds up electrode, the Cu and metal titanium and titanium alloys etc. of structure.
Step 802, by the mode of wet etching, patterning processes is carried out to the first metal layer, form the first patterned metal layer 302, as shown in Figure 9, be the first patterned metal layer 302 schematic diagram, this first patterned metal layer 302 comprises: the bottom crown 302c of sweep trace 302a, guarded electrode 302b and memory capacitance; The bottom crown 302c at least guarded electrode 302b described in multiplexing part of described memory capacitance;
Step 803, first patterned metal layer 302 is formed the first insulation course 303, cleaning before technique film forming, by plasma reinforced chemical vapor deposition (PECVD) method, first patterned metal layer prepares insulation course, its materials application is more extensive, as silicon dioxide (SiO2) film, silicon nitride film (SiNx), silicon oxynitride film (SiOxNy), aluminium oxide (Al2O3) film, the film of the sandwich construction of TiOx film and compound.Then surface treatment is carried out to the first insulation course 303.
Step 804, the first insulation course 303 forms two semiconductor layers be separated from each other 304, and as shown in Figure 9, two semiconductor layers be separated from each other 304 are formed in the position corresponding with two grids.
Step 805, semiconductor layer 304 forms the second metal level by magnetron sputtering, and carries out wet etching patterning processes to the second metal level, forms the second patterned metal layer 305, as shown in Figure 10, for forming the dot structure schematic diagram of the second patterned metal layer 305.For more clearly understanding shape and the structure of the second patterned metal layer 305, can be the schematic diagram of the second patterned metal layer 305 see Figure 11, Figure 11, this second patterned metal layer 305 comprises top crown 305a and the data line 305b of memory capacitance.
On array base palte in the embodiment of the present invention, multi-strip scanning line 302a intersects with data line 305b and limits multiple dot structure; The top crown 305a of memory capacitance at least has the part overlapping with the bottom crown 302c of described memory capacitance; Described dot structure is divided at least two photic zones by the part that the top crown 305a of memory capacitance is overlapping with the bottom crown 302c of described memory capacitance.
Further, the method for making of array base palte also comprises:
Step 806, forms the second insulation course 306 at the second metal level, and carries out the etching technics of via hole, the via hole v1 formed, as shown in Figure 3, be the dot structure schematic diagram of embodiment of the present invention array base palte, via hole v1 is used for the pixel electrode 307a formed afterwards and drain electrode d2 to be electrically connected.
Step 807, form pixel electrode layer 908 over the second dielectric, and by the method for wet etching, patterning processes is carried out to it, the indium tin oxide that the material of pixel electrode layer 908 widely adopts now, the dot structure that final formation one is complete, as shown in Figure 3 above.
It should be noted that, the embodiment of the present invention is the manufacturing process that example illustrates array base palte by means of only a kind of array base palte of typical bottom-gate type configuration, and the array base palte of other structures also can be made by the method for embodiment of the present invention embodiment.The embodiment of the present invention is in manufacturing process, by the bottom crown multiplexing part guarded electrode of memory capacitance, and make the top crown of the memory capacitance part overlapping with the bottom crown of memory capacitance that dot structure is divided at least two photic zones, make by the method the array base palte obtained and effectively prevent the light tight district of large area memory capacitance and the grid sense problem caused, and, in the embodiment of the present invention, due to multiplexing guarded electrode and memory capacitance bottom crown, do not need to make separately guarded electrode and memory capacitance bottom crown, the area shared by the first patterned metal layer on substrate can be reduced, decrease light tight region, increase the aperture opening ratio of pixel.
It can be seen from the above: the embodiment of the present invention provides a kind of array base palte, the substrate of this array base palte is provided with multi-strip scanning line and data line; Multi-strip scanning line and data line intersection limit multiple dot structure; Bottom crown and the sweep trace of guarded electrode, memory capacitance are positioned at same layer, and guarded electrode is positioned at least one lateral edges of dot structure, the bottom crown of memory capacitance is positioned at the part zone line of dot structure edge and dot structure, is positioned at the bottom crown multiplexing part guarded electrode of the memory capacitance at dot structure edge; First insulation course covers the layer at memory capacitance bottom crown place; The top crown of memory capacitance is arranged on described first insulation course, and with data line bit in same layer, the top crown of memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance, and dot structure is divided at least two photic zones by the part of this overlap.Photic zone, by changing by the shape of memory capacitance, is divided at least two photic zones by the embodiment of the present invention, has disperseed light tight district, thus effectively prevent the grid sense problem caused due to large-area light tight district.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an array base palte, comprising:
Substrate, described substrate is provided with multi-strip scanning line and data line; Many described sweep traces and data line intersection limit multiple dot structure;
Guarded electrode, is positioned at least one lateral edges of described dot structure and is positioned at same layer with described sweep trace;
The bottom crown of memory capacitance, bottom crown and the described sweep trace of described memory capacitance are positioned at same layer, and the bottom crown of described memory capacitance at least guarded electrode described in multiplexing part;
First insulation course, covers the layer at described memory capacitance bottom crown place;
The top crown of memory capacitance, is arranged on described first insulation course, and with described data line bit in same layer;
The top crown of described memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance;
Described dot structure is divided at least two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
2. array base palte as claimed in claim 1, it is characterized in that, described dot structure is divided into two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
3. array base palte as claimed in claim 2, is characterized in that, the area equation of described two photic zones.
4. array base palte as claimed in claim 1, it is characterized in that, the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance is " work " herringbone pattern; Described " work " herringbone pattern and described data line are arranged in the same way.
5. array base palte as claimed in claim 1, is characterized in that, also comprise:
Second insulation course, covers the top crown of described memory capacitance;
Pixel electrode, covers described second insulation course; The top crown of described pixel electrode and described memory capacitance is electrically connected.
6. the array base palte according to any one of claim 1-5, it is characterized in that, described dot structure also comprises at least one grid be connected with described sweep trace, and with described data line bit in the source electrode of same layer and drain electrode, described memory capacitance top crown is electrically connected with described drain electrode.
7. array base palte as claimed in claim 6, it is characterized in that, the number of described grid is two, correspondingly with described two grids on described first insulation course is provided with two semiconductor layers be separated from each other.
8. a display device, is characterized in that, comprises the array base palte according to any one of the claims 1-7, and the subtend substrate be oppositely arranged with described array base palte.
9. display device as claimed in claim 8, is characterized in that, also comprise the reflector plate being arranged at described array base palte and deviating from described subtend substrate side.
10. a method for making for array base palte, is characterized in that, comprising:
One substrate is provided;
Form the bottom crown of sweep trace, guarded electrode and memory capacitance over the substrate, the bottom crown of described memory capacitance, guarded electrode and sweep trace are positioned at same layer, and the bottom crown of described memory capacitance at least guarded electrode described in multiplexing part;
Form the first insulation course, cover the layer at the bottom crown place of described memory capacitance;
Described first insulation course is formed top crown and the data line of memory capacitance, and the top crown of described memory capacitance and described data line bit are in same layer;
Described sweep trace intersects with described data line and limits multiple dot structure;
The top crown of described memory capacitance at least has the part overlapping with the bottom crown of described memory capacitance; Described dot structure is divided at least two photic zones by the part that the top crown of described memory capacitance is overlapping with the bottom crown of described memory capacitance.
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