CN104485284B - A kind of preparation method of controllable aligned nanowires and its field-effect transistor - Google Patents
A kind of preparation method of controllable aligned nanowires and its field-effect transistor Download PDFInfo
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- CN104485284B CN104485284B CN201410820866.7A CN201410820866A CN104485284B CN 104485284 B CN104485284 B CN 104485284B CN 201410820866 A CN201410820866 A CN 201410820866A CN 104485284 B CN104485284 B CN 104485284B
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- 239000002070 nanowire Substances 0.000 title claims abstract description 153
- 238000002360 preparation method Methods 0.000 title claims abstract description 44
- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 239000013078 crystal Substances 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000013461 design Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000737 periodic effect Effects 0.000 claims description 6
- 239000004744 fabric Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010923 batch production Methods 0.000 abstract description 2
- 238000000407 epitaxy Methods 0.000 abstract description 2
- 238000005389 semiconductor device fabrication Methods 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract description 2
- 125000004429 atom Chemical group 0.000 description 28
- 238000001451 molecular beam epitaxy Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910000238 buergerite Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000097 high energy electron diffraction Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 235000012149 noodles Nutrition 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 238000010792 warming Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses the preparation method and its preparation method of field-effect transistor of a kind of controllable aligned nanowires.Growth material is used as substrate along the anisotropic material of growth rate of different crystal orientations during the present invention is grown by selective epitaxy, so as to realize the growth of nano wire；Arrangement and diameter by design configuration substrate, can cycle of accuracy controlling aligned nanowires, quantity, length and diameter, meet different FET demands；The growth conditions of rich VI races or rich V group atom reaches the effect of surface suppression, reduces isotropism of the metallic atom on surface and migrates, and is conducive to the growth of nano wire；Preparing for controllable aligned nanowires FET can use traditional semiconductor device fabrication processes, and process is simple, Modulatory character is strong, with low cost, can realize batch production.
Description
Technical field
The present invention relates to the preparation method of field-effect transistor, more particularly to a kind of preparation method of controllable aligned nanowires
And the preparation method of controllable aligned nanowires field-effect transistor.
Background technology
One-dimensional nanometer semiconductor structure has crystal mass very high, excellent electrical and optical properties, makes it in nanometer
Device, such as fieldtron, photoelectric detector, high efficiency light-emitting device, senser element, Monoelectron memory device and monochromatic light
Sub- device etc., field has a wide range of applications.Field-effect transistor FET be it is a kind of by semi-conducting material be made by voltage control
The three-terminal element of electric current processed, there is extremely important effect in electronic circuit, and nano-wire fet is even more nano electron device and is answered
Foundation stone.
The development experience of FET is from flat FET to fin FETs again to the differentiation of nano-wire fet.Because fin FETs are
The Nanoscale channels obtained by micro-nano technology technology, can inevitably produce some extra defects and damage in the process
Wound, reduces effect of FET；However, nano wire is the nanostructured of primary length, with good surface topography and crystal very high
Quality, and nano-wire fet has the advantage of fin FETs concurrently.But, single nano-wire FET source leakage current is relatively small, it is difficult to
To practical application.Additionally, nano-wire fet can improve source-drain current and grid voltage pair by the quantity of nano wire in control passage
The ability of regulation and control of source-drain current, reaches the purpose of the mutual conductance, source-drain current and on-off ratio that improve FET, so, aligned nanowires
FET arises at the historic moment.
The method for preparing aligned nanowires FET at present mainly includes that extraneous method controls array arrangement and the side of nano wire
To growth nanowire approach.But, the former is difficult to obtain the aligned nanowires of large area, and the latter's controllability is very poor, so as to cause
Controllable aligned nanowires FET is difficult to.
The content of the invention
For the problem that above prior art is present, the present invention proposes a kind of controllable aligned nanowires and its field-effect is brilliant
The preparation method of body pipe, can prepare controllable aligned nanowires, and such as cycle of nano wire, diameter, length and quantity is adjustable
Control, and using traditional process for fabrication of semiconductor device prepare controllable aligned nanowires field-effect transistor on this basis
FET。
It is an object of the present invention to provide a kind of preparation method of controllable aligned nanowires.
The preparation method of controllable aligned nanowires of the invention, the array nanometer for preparing II-VI group or iii-v
Line, comprises the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；
4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；
5) cycle according to aligned nanowires and diameter, determine the atom line of II races or III atom；
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate.
Wherein, in step 1) in, select substrate material need consider, thereon institute's growth material along different crystal orientations life
Speed long is anisotropy.Crystal orientation is grown along override in the direction of the nano wire of Grown, growth material is along different
The growth rate anisotropy of crystal orientation is stronger, i.e. the ratio between the growth rate in the growth rate of override growth crystal orientation and other directions
Bigger, the single linear of nano wire is more notable.Override growth crystal orientation is located in substrate surface.
In step 2) in, the figure of design configuration substrate refers to that the preparation requirement of field-effect transistor FET determines array
The cycle of nano wire and diameter, cycle and diameter according to aligned nanowires, the arrangement of the figure of design configuration substrate and straight
Footpath.The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice.The row of figure
Cloth can be the two-dimensional lattice of equidistant arrangement, or the two-dimensional lattice of rectanglar arrangement.The row of two-dimensional lattice are to along optimal
The distance between first growth crystal orientation arrangement, adjacent two row (column pitch) is the cycle of aligned nanowires, and the length of column direction is determined
Determine the length of nano wire；The columns of two-dimensional lattice is the quantity of aligned nanowires.The diameter d in post or hole determines the straight of nano wire
, slightly larger than post or the diameter d in hole, the value of the ratio between the two D/d is between 1~3 for footpath D, the diameter D of nano wire.The system of patterned substrate
Preparation Method includes：Nanometer embossing, electron beam exposure EBL and focused ion beam FIB etc..
In step 3) in, the pretreatment to patterned substrate includes：Patterned substrate to having prepared carries out Chemical cleaning,
Then high-temperature baking is carried out, the foreign atom on surface is removed, so that the clean surface of patterned substrate.
In step 4) in, the growing method of aligned nanowires determines that override grows the growth rate ν of crystal orientation, override
The growth rate ν for growing crystal orientation determines the atom line F of VI races or V group atom1, meet relation F1=k1ν, wherein, k1To be
Number, the crystal structure with the material of aligned nanowires is relevant.
In step 5) in, the growth of aligned nanowires would generally select the growth conditions of rich VI races or rich V group atom, favorably
Migrated in isotropism of the metallic atom on surface is suppressed, so as to realize the growth of controllable aligned nanowires, specific II races or
III atom line F2Need according to designed by the cycle of aligned nanowires and diameter to determine, II races or III atom line
F2, the arrangement with the figure of the diameter D and patterned substrate of nano wire is relevant, meets relational expression：F2=k2D2/L1 2, or F2=
k2D2/(L2L3), wherein, k2It is coefficient, L relevant with the growing method that growth aligned nanowires are used1It is equidistant arrangement
In two-dimensional lattice, the distance between adjacent 2 points, L2And L3Between the line space and row respectively in the two-dimensional lattice of rectanglar arrangement
Away from.
In step 6) in, the method for growing controllable aligned nanowires includes：Molecular beam epitaxy MBE, metal organic-matter chemical
Vapour deposition MOCVD, chemical vapor deposition CVD, pulsed laser deposition PLD etc..With the increase of growth time, graphically serving as a contrast
The post or Kong Shanghui at bottom grow the nano wire segment that length gradually increases, until nano wire segment connect into one it is complete straight
Untill line, growth terminates.Before nano wire segment is combined with each other, the length of nano wire segment can be adjusted by growth time
Control, the length of growth time nano wire segment more long is more long.
It is another object of the present invention to provide a kind of preparation method of controllable aligned nanowires field-effect transistor.
The preparation method of controllable aligned nanowires field-effect transistor FET of the invention, for preparing II-VI group or III-
The aligned nanowires of V races, comprise the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；
4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；
5) cycle according to patterned substrate and diameter, determine the atom line of II races or III atom；
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate；
7) aligned nanowires that will have been grown on substrate as FET channel region, using traditional semiconductor devices
Preparation technology, sequentially forms source electrode, drain electrode, gate insulator and grid thereon.
Wherein, in step 7) in, when preparing aligned nanowires FET, can be according to institute in the preparation of FET requirement selection channel region
Quantity containing nano wire, to meet different FET demands.
Aligned nanowires refer to, one group of nano wire being arranged in array by equidirectional.Experiment finds semi-conducting material edge
The growth rate of different crystal orientations is presented obvious anisotropy, and the present invention utilizes this characteristic, chooses growth material along the not isomorphous
To the anisotropic substrate of growth rate, the consistent nano wire of orientation can be prepared, can enter one by patterned substrate
Cycle of step control aligned nanowires, diameter, length and quantity, so as to prepare controllable aligned nanowires FET.
Advantages of the present invention：
(1) arrangement by design configuration substrate and diameter, can accuracy controlling aligned nanowires cycle, quantity, length
Degree and diameter, meet different FET demands；
(2) selective epitaxy growth in growth material along the anisotropic material of growth rate of different crystal orientations as substrate,
So as to realize the growth of nano wire；
(3) growth conditions of richness VI races or rich V group atom reaches the effect of surface suppression, reduces metallic atom on surface
Isotropism migration, be conducive to the growth of nano wire；
(4) preparing for controllable aligned nanowires FET can use traditional semiconductor device fabrication processes, and process is simple can
Control is strong, with low cost, can realize batch production.
Brief description of the drawings
Fig. 1 be according to the embodiment one of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of GaN column patterned substrates, wherein, (a) is top view, and (b) is side view；
Fig. 2 be according to the embodiment one of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of nano wire segment in GaN column patterned substrates, wherein, (a) is top view, and (b) is side view；
Fig. 3 be according to the embodiment one of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of aligned nanowires in GaN column patterned substrates, wherein, (a) is top view, and (b) is side view；
Fig. 4 be according to the embodiment two of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of the poroid patterned substrates of 4H-SiC, wherein, (a) is top view, and (b) is the section of the A-A ' lines along figure (a)
Figure；
Fig. 5 be according to the embodiment two of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of nano wire segment in the poroid patterned substrates of 4H-SiC, wherein, (a) is top view, and (b) is along figure (a)
The profile of A-A ' lines；
Fig. 6 be according to the embodiment two of the preparation method of controllable aligned nanowires of the invention obtainFace
The partial schematic diagram of aligned nanowires in the poroid patterned substrates of 4H-SiC, wherein, (a) is top view, and (b) is along figure (a)
The profile of A-A ' lines；
Fig. 7 is that the controllable array obtained according to the preparation method of controllable aligned nanowires field-effect transistor of the invention is received
The schematic diagram of rice noodles FET, wherein, (a) is top view, and (b) is the profile of the B-B ' lines along figure (a), and (c) is side view.
Specific embodiment
Below in conjunction with the accompanying drawings, by embodiment, the present invention will be further described.
Embodiment one
In the present embodiment, the controllable aligned nanowires of GaN are prepared, substrate uses GaN；The figure of patterned substrate is for periodically
Column two-dimensional lattice；The growth material of aligned nanowires is GaN；The growing method of aligned nanowires uses molecular beam epitaxy
MBE existsGrown in the GaN patterned substrates of face；Growth course is carried out in ultrahigh vacuum growth chamber, high-purity (7N) gold
Category source is produced by K-Cell sources stove；Nitrogen source uses radio frequency plasma nitrogen source；Growth course reflected high energy electron diffraction
Instrument RHEED in-situ monitorings.
The preparation method of the controllable aligned nanowires of the present embodiment, comprises the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate：
Buergerite GaN is much larger than edge along [0001] direction growth rateWithThe growth rate in direction, choosing
SelectFace GaN is used as substrate so that [0001] andDirection is conducive to the growth of nano wire in substrate surface.
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate：
The figure of patterned substrate is the two-dimensional lattice of cylindric equidistant arrangement, and the distance between adjacent 2 points are
500nm, diameter d=350nm, without mask, then the column pitch of two-dimensional lattice is 60 ° of the distance between adjacent 2 points × sin, i.e.,
500 × sin, 60 °=433nm, prepare patterned substrate, as shown in Figure 1 using nano-imprinting method.
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate：
First, patterned substrate is chemically cleaned so that the surface cleaning of patterned substrate；Then, will be graphical
Substrate is warming up to about 600 DEG C, toasts 10~30min.
4) growth rate of crystal orientation is grown according to override, the atom line of V group atom is determined：
The growing method of molecular beam epitaxy MBE determines that override grows crystal orientation --- the growth rate in [0001] direction is
10nm/min, now the line of nitrogen-atoms be about FN=7.6 × 1014cm-2s-2。
5) cycle according to patterned substrate and diameter, determine the atom line of III atom：
Cycle and diameter according to figure, the atom line ratio of optimization is FN/FGa=5, then the line of Ga atoms be about FGa
=1.52 × 1014cm-2s-2。
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate, with growth time
Increase, the nano wire segment that length gradually increases can be grown on the post of patterned substrate, as shown in Fig. 2 until nanometer
Untill line segment connects into a complete straight line, aligned nanowires growth terminates, as shown in figure 3, the aligned nanowires for obtaining
Cycle P be column pitch 433nm, a diameter of D=400nm of nano wire of nano wire, for the two-dimensional points of equidistant arrangement
Battle array, the length L of nano wire is the points × the distance between adjacent 2 points of column, and the quantity of nano wire is the row of two-dimensional lattice
Number, the section of single nano-wire is shaped as regular hexagon.RHEED in-situ monitorings are used in growth course.
The controllable aligned nanowires of GaN of this method growth have good surface topography and crystal mass higher, scan
Electron microscope SEM tests show that nano wire orientation is consistent along [0001] direction, the growth rate in nano wire edge [0001] direction
Apparently higher thanDirection.
Embodiment two
In the present embodiment, the controllable aligned nanowires FET of GaN are prepared, substrate uses GaN；The figure of patterned substrate is week
The poroid two-dimensional lattice of phase property；The growth material of aligned nanowires is GaN；The growing method of aligned nanowires is using outside molecular beam
Prolong MBE to existGrown in the 4H-SiC patterned substrates of face；Growth course is carried out in ultrahigh vacuum chamber, high-purity (7N) gold
Category source is produced by K-Cell sources stove；Nitrogen source uses radio frequency plasma nitrogen source；Growth course reflected high energy electron diffraction
Instrument RHEED in-situ monitorings.
The preparation method of the controllable aligned nanowires FET of the present embodiment, comprises the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate：
Buergerite GaN is much larger than edge along [0001] direction growth rateWithThe growth rate in direction, choosing
SelectFace 4H-SiC is used as substrate so that [0001] andDirection is conducive to the growth of nano wire in substrate surface.
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate：
The figure of patterned substrate is the two-dimensional lattice of the circular hole four directions arrangement for having mask, is first existedFace 4H-SiC
With the SiO that plasma enhanced chemical vapor deposition PECVD methods growth 20nm is thick on substrate 12As mask 21, then adopt
Patterned substrate is prepared with focused ion beam FIB, figure is the two-dimensional lattice 2 of the four directions arrangement of circular hole, as shown in figure 4,
This is prepared for three different figures of column pitch respectively, and design parameter is as shown in the table：
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| Line space/μm | 1.0 | 2.0 | 3.0 |
| Diameter d/nm | 50 | 50 | 50 |
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate：
First, patterned substrate is chemically cleaned so that the surface cleaning of patterned substrate；Then, will be graphical
Substrate is warming up to about 600 DEG C, toasts 10~30min.
4) growth rate of crystal orientation is grown according to override, the atom line of V group atom is determined：
The growing method of molecular beam epitaxy MBE determines that override grows crystal orientation --- the growth rate in [0001] direction is
10nm/min, now the line of nitrogen-atoms be about FN=7.6 × 1014cm-2s-2。
5) cycle according to patterned substrate and diameter, determine the atom line of III atom：
The different figure of three column pitch, corresponding atom line is as shown in the table：
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| 5 | 10 | 15 | |
| 1.52 | 0.76 | 0.51 |
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate, with growth time
Increase, the nano wire segment 31 that length gradually increases is grown in the Kong Shanghui of patterned substrate, as shown in figure 5, until receive
Untill rice noodles segment connects into a complete straight line, aligned nanowires 3 growth terminate, as shown in fig. 6, single nano-wire cut
Face is shaped as regular hexagon, and for the two-dimensional lattice of rectanglar arrangement, the length L of nano wire is line space × line number, nano wire
Quantity be the columns of two-dimensional lattice, the relevant parameter of the aligned nanowires for obtaining see the table below：
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| P/ μm of the cycle of aligned nanowires | 1.0 | 2.0 | 3.0 |
| The diameter D/nm of nano wire | 150 | 120 | 100 |
RHEED in-situ monitorings are used in growth course.The controllable aligned nanowires of GaN of this method growth have good surface
Pattern and crystal mass higher, SEM tests show that nano wire orientation is consistent along [0001] direction, and nano wire is along [0001] direction
Growth rate apparently higher thanDirection, and length before nano wire segment is combined with each other can be by growth time
Regulated and controled.
7) aligned nanowires that will have been grown on substrate as FET channel region, according to FET preparation requirement selection
The quantity of contained nano wire in channel region, to meet the demand of prepared FET；Work is prepared using traditional semiconductor devices
Skill, sequentially forms source electrode 4, drain electrode 5, gate insulator 6 and grid 7 thereon, controllable aligned nanowires FET is obtained, such as Fig. 7 institutes
Show.
More than sets forth the embodiment for preparing aligned nanowires and aligned nanowires FET.Preparation method of the invention
II-VI group or iii-v and the controllable aligned nanowires FET of other semiconductors can be prepared, as long as the semi-conducting material being related to has
There is anisotropic growth rate, substrate can be chosen using the method for the present invention, design configuration is required according to FET, prepare
The atom line of each growth source of parameter determination such as patterned substrate, cycle and diameter according to figure, realizes controllable array nanometer
The growth of line, so as to prepare controllable aligned nanowires, and combines traditional process for fabrication of semiconductor device system on this basis
Standby controllable aligned nanowires FET.
It is finally noted that, the purpose for publicizing and implementing mode is that help further understands the present invention, but ability
The technical staff in domain is appreciated that：Without departing from the spirit and scope of the invention and the appended claims, it is various replacement and
Modification is all possible.Therefore, the present invention should not be limited to embodiment disclosure of that, the scope of protection of present invention with
The scope that claims are defined is defined.
Claims (8)
1. a kind of preparation method of controllable aligned nanowires, the aligned nanowires for preparing II-VI group or iii-v, it is special
Levy and be, the preparation method is comprised the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；
4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；
5) cycle according to aligned nanowires and diameter, determine the atom line of II races or III atom；
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate；
Wherein, in step 2) in, cycle and diameter according to aligned nanowires, the arrangement of the figure of design configuration substrate and straight
Footpath；The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice；The row of figure
Cloth is the two-dimensional lattice of equidistant arrangement, or rectanglar arrangement two-dimensional lattice；
In step 6) in, with the increase of growth time, grow length in the post or Kong Shanghui of patterned substrate and gradually increase
Nano wire segment, untill nano wire segment connects into a complete straight line, growth terminates；It is mutual in nano wire segment
With reference to before, the length of nano wire segment is regulated and controled by growth time, and the length of growth time nano wire segment more long is more
It is long.
2. preparation method as claimed in claim 1, it is characterised in that in step 1) in, in the nano wire of Grown
Direction grows crystal orientation along override, and growth material is stronger along the growth rate anisotropy of different crystal orientations, i.e. override growth
The growth rate of crystal orientation is bigger with the ratio between the growth rate in other directions, and the single linear of nano wire is more notable；Override growth is brilliant
To in substrate surface.
3. preparation method as claimed in claim 1, it is characterised in that the row of two-dimensional lattice are arranged to along override growth crystal orientation
The distance between row, adjacent two row are the cycle of aligned nanowires；The columns of two-dimensional lattice is the quantity of aligned nanowires.
4. preparation method as claimed in claim 1, it is characterised in that the diameter d in post or hole determines the diameter D of nano wire, two
The value of the ratio between person D/d is between 1~3.
5. preparation method as claimed in claim 1, it is characterised in that in step 4) in, the growing method of aligned nanowires is determined
The growth rate ν that override grows crystal orientation is determined, the growth rate ν of override growth crystal orientation determines the original of VI races or V group atom
Beamlet stream F1, meet relation F1=k1ν, wherein, k1It is coefficient, the crystal structure with the material of aligned nanowires is relevant.
6. preparation method as claimed in claim 1, it is characterised in that in step 5) in, the growth selection of aligned nanowires is rich
VI races or the growth conditions of rich V group atom, II races or III atom line F2, with the diameter D of nano wire and patterned substrate
The arrangement of figure is relevant, meets relational expression：F2=k2D2/L1 2, or F2=k2D2/(L2L3), wherein, k2It is coefficient, with growth battle array
The growing method for being used of row nano wire is relevant, L1For in the two-dimensional lattice of equidistant arrangement, the distance between adjacent 2 points,
L2And L3Line space and column pitch respectively in the two-dimensional lattice of rectanglar arrangement.
7. a kind of preparation method of controllable aligned nanowires field-effect transistor FET, for preparing II-VI group or iii-v
Aligned nanowires, it is characterised in that the preparation method is comprised the following steps：
1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；
2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；
3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；
4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；
5) cycle according to patterned substrate and diameter, determine the atom line of II races or III atom；
6) according to condition determined above, aligned nanowires are grown in clean patterned substrate；
7) aligned nanowires that will have been grown on substrate are prepared as the channel region of FET using traditional semiconductor devices
Technique, sequentially forms source electrode, drain electrode, gate insulator and grid thereon；
Wherein, in step 2) in, cycle and diameter according to aligned nanowires, the arrangement of the figure of design configuration substrate and straight
Footpath；The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice；The row of figure
Cloth is the two-dimensional lattice of equidistant arrangement, or rectanglar arrangement two-dimensional lattice；
In step 6) in, with the increase of growth time, grow length in the post or Kong Shanghui of patterned substrate and gradually increase
Nano wire segment, untill nano wire segment connects into a complete straight line, growth terminates；It is mutual in nano wire segment
With reference to before, the length of nano wire segment is regulated and controled by growth time, and the length of growth time nano wire segment more long is more
It is long.
8. preparation method as claimed in claim 7, it is characterised in that in step 7) in, the preparation requirement selection ditch according to FET
The quantity of contained nano wire in road area, to meet the demand of FET.
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