CN104465746A - HEMT device and manufacturing method of HEMT device - Google Patents

HEMT device and manufacturing method of HEMT device Download PDF

Info

Publication number
CN104465746A
CN104465746A CN201410509822.2A CN201410509822A CN104465746A CN 104465746 A CN104465746 A CN 104465746A CN 201410509822 A CN201410509822 A CN 201410509822A CN 104465746 A CN104465746 A CN 104465746A
Authority
CN
China
Prior art keywords
grid
region
barrier layer
resistance
hemt device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410509822.2A
Other languages
Chinese (zh)
Other versions
CN104465746B (en
Inventor
裴轶
张乃千
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dynax Semiconductor Inc
Original Assignee
Dynax Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dynax Semiconductor Inc filed Critical Dynax Semiconductor Inc
Priority to CN201410509822.2A priority Critical patent/CN104465746B/en
Publication of CN104465746A publication Critical patent/CN104465746A/en
Application granted granted Critical
Publication of CN104465746B publication Critical patent/CN104465746B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses an HEMT device and a manufacturing method of the HEMT device. The HEMT device comprises a substrate, an active region formed on the substrate, a barrier region formed on the active region, a blocking region formed on the barrier region, a grid formed on the blocking region, low-resistance regions formed on the two sides of the grid respectively, a source and a drain, wherein the grid is used in the low-resistance regions as masking, the low-resistance regions are formed according to a self-alignment process and are provided with doping particles, and the source and the drain are formed on the low-resistance regions on the two sides of the grid respectively. By means of the HEMT device and the manufacturing method, the grid-source distance and the grid-drain distance are effectively reduced, the grid-source series resistance and the grid-drain series resistance are reduced, and the high frequency characteristic of the device is improved. In addition, accurate alignment is not needed when the low-resistance regions are formed, the requirement for the alignment accuracy of the photolithography technique is reduced, the yield of the device is improved, and the production cost is reduced.

Description

A kind of HEMT device and manufacture method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of HEMT device and manufacture method thereof.
Background technology
Compared with other semi-conducting material, III-nitride material has the advantages such as energy gap is large, critical breakdown electric field is high, saturated electrons speed is high, thermal conductivity is high, stable chemical nature.III-nitride material has stronger piezoelectricity and spontaneous polarization effect in addition, such as, GaN can form two-dimensional electron gas (2DEG) conducting channel with high areal density and high mobility with materials such as aluminum gallium nitride (AlGaN), indium aluminium nitrogen (InAlN) and aluminium nitrogen (AlN).Therefore GaN base high electron mobility field-effect transistor (HEMT) has the features such as current density is large, power density is large, high frequency characteristics is good and high temperature resistant, has a wide range of applications in dual-use microwave power field.
In microwave applications field, the size of reduction of device is improve GaN base HEMT device current gain cutoff frequencies (f shorten grid to grow and to reduce source and drain resistance t) important measures.At present, the grid of GaN base HEMT device are long shortens to 30nm, the current gain cutoff frequencies of device has also reached 370GHz (see Yuanzheng Yue, et al, InAlN/AlN/GaN HEMTs With Regrown Ohmic Contacts and f tof 370GHz, IEEE Electron Device Letters, vol.33, no.7, pp.988-990.).
In GaN base HEMT device manufacture process, for the device size determined, ohmic contact resistance and grid source, grid leak series resistance are two important parameters affecting device high frequency characteristics, and therefore shortening grid spacing and grid leak distance and improving ohmic contact growth technique is two important measures improving device high frequency characteristics.
On the one hand, form the method for source-drain electrode area and grid in prior art, be limited to the restriction of photoetching alignment precision, the source and drain of device is apart from usually larger, make the grid source series resistance of HEMT device and grid leak series resistance comparatively large, thus reduce the high frequency characteristics of HEMT device.
On the other hand, low ohmic contact resistance needs good ohmic contact growth technique.The current usual employing high annealing of industry forms alloy ohmic contact, but high annealing can cause the degeneration of grid knot even to lose efficacy, and grid leakage current is increased, even makes grid schottky junction form ohmic contact.Larger grid leakage current can reduce high frequency performance and the breakdown performance of device, reduces reliability and the rate of finished products of device simultaneously.
Summary of the invention
In view of this, the present invention proposes a kind of HEMT device and manufacture method thereof, to solve one or more in problem involved in background technology.
On the one hand, embodiments provide a kind of HEMT device, comprising:
Substrate;
Active area, is formed on described substrate;
Barrier region, is formed on described active area;
Resistance, is formed on described barrier region;
Grid, is formed on described Resistance;
Low-resistance region, be respectively formed at described grid both sides, wherein, described low-resistance region is for sheltering with described grid, formed by self-registered technology, and described low-resistance region has doping particle, the concentration of described doping particle is positioned at the part corresponding with described active area or the part corresponding with described barrier region at the peak value of vertical direction; And
Source electrode and drain electrode, be respectively formed on the low-resistance region of described grid both sides.
Described substrate can be the material of the applicable growth III-V such as sapphire, silicon, carborundum, gallium nitride or rare earth oxide.
The material of described grid is refractory material, described refractory material be selected from following group one or more: tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride; Or be
The nitride of the material in described group; Or be
The alloy of the material in described group; Or be
The lamination of material in described group; Or be
The lamination of the alloy of the material in the nitride of the material in the material in described group or described group or described group; Or be
The alloy of material in the nitride of the material in the material in described group or described group or described group or the lamination of insulating material.
Described barrier region is the semiconductor material layer forming heterojunction with the material of described active area; Or be
The lamination of semi-conducting material and insulating material formed thereon.
In the material of described Resistance one or more when described grid etch by etch-rate lower than the etched speed of one or more materials in described grid material.
Preferably, described Resistance comprises:
Anti-etching district, is formed on described barrier region, the etching injury caused described barrier layer during for reducing described grid etch;
First medium district, is formed in described anti-etching district, for reducing the leakage current of described grid.
Described anti-etching district material by etch-rate preferably lower than the etched speed of one or more materials in described grid material.
Described first medium district material is insulating material.
The surface towards gate electrode side of described low-resistance region is lower than the surface towards gate electrode side of described Resistance.
Preferably, described HEMT device also comprises grid curb wall, is formed at described grid both sides or is formed on described grid both sides and described grid.Described grid curb wall can utilize photoetching technique to regulate at the width of described grid and source electrode and described grid and drain directions, and the width of grid leak side grid curb wall is not less than the width of side, grid source grid curb wall.The material of described grid curb wall is insulating material.
Preferably, described HEMT device also comprises gate medium, is formed between described Resistance and described grid.
Preferably, described HEMT device also comprises resilient coating, is formed between described substrate and described active area, for reducing the lattice mismatch between substrate and active area.
On the other hand, embodiments provide a kind of method manufacturing HEMT device, comprise step:
S1, on substrate, be formed with active layer;
S2, on described active layer, form barrier layer;
S3, on described barrier layer, form barrier layer;
S4, on described barrier layer, form grid;
S5, with described grid for sheltering, form Resistance, active area and barrier region by self-registered technology in formation low-resistance region, described grid both sides, wherein said low-resistance region has doping particle; And
S6, form source electrode and drain electrode respectively in the low-resistance region of described grid both sides.
Describedly a kind ofly manufacture step S5 in the method for HEMT device and comprise:
Adulterated in the region of grid both sides, wherein doping depth is in active area or barrier region, be doped formation low-resistance region, region, the barrier layer be not doped, barrier layer and active layer form described Resistance, barrier region and active area respectively, and the concentration of wherein said doping particle is positioned at the part corresponding with described active area or the part corresponding with described barrier region at the peak value of vertical direction.
Optionally, describedly a kind ofly manufacture step S5 in the method for HEMT device and also comprise:
Before being adulterated in the region of grid both sides, with grid for sheltering, remove the barrier layer of the whole thickness in grid both sides and the barrier layer of part thickness, or the barrier layer on the barrier layer and whole thickness of removing grid both sides whole thickness is to expose described active layer, or remove the barrier layer of the whole thickness in grid both sides and the barrier layer of whole thickness and the active layer of part thickness.
Optionally, describedly a kind ofly manufacture step S5 in the method for HEMT device and comprise:
With grid for sheltering, the barrier layer on the barrier layer and whole thickness of removing grid both sides whole thickness to expose described active layer, or removes the barrier layer of the whole thickness in grid both sides and the barrier layer of whole thickness and the active layer of part thickness; Not removed barrier layer, barrier layer and active layer form described Resistance, barrier region and active area respectively;
Region growing in grid both sides, with the semi-conducting material of doping particle, forms low-resistance region.
Preferential, a kind of described method manufacturing HEMT device also comprises between step S4 and S5: on described grid both sides or described grid both sides and grid, form grid curb wall, described side wall can utilize photoetching technique to regulate at the width in grid source and grid leak direction, and the width of grid leak side grid curb wall is not less than the width of side, grid source grid curb wall.
Further, when utilizing the region of ion injection method to grid both sides to adulterate, ion implantation direction and barrier layer and active layer interface vertical direction angle are along clockwise direction more than or equal to 0 degree, and are less than or equal to 40 degree.The present invention shortens grid spacing and grid leak distance effectively by source and drain self-registered technology, reduces grid source series resistance and grid leak series resistance, improves the high frequency characteristics of device; And do not need to carry out accurate alignment during the trivial formation of low resistance, reduce the requirement to photoetching process alignment precision, the rate of finished products that improve device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce the etch damage of barrier layer.Further, in a preferred embodiment of the invention, grid employing refractory material avoids the grid knot degeneration that ohmic contact high annealing causes, and improves rate of finished products and the reliability of device; Highly doped or the source and drain regrowth process of source and drain effectively improves the ohmic contact characteristic of source-drain electrode, reduces ohmic contact resistance, thus improves the high frequency performance of device.
Reading embodiment and after checking accompanying drawing, person of skill in the art will appreciate that other feature and advantage.
Accompanying drawing explanation
Now explain example with reference to the accompanying drawings.Accompanying drawing, for illustration of general principle, makes illustrate only and understands the necessary aspect of general principle.Accompanying drawing is not drawn to scale.Reference numeral identical in the accompanying drawings represents similar feature.
Fig. 1 shows the structural representation of the HEMT device that the embodiment of the present invention one provides;
Fig. 2 shows the manufacture method flow chart of the HEMT device that the embodiment of the present invention one provides;
Fig. 3 a-3f, 5a-5c show structural section figure corresponding to each step of manufacture method of the HEMT device provided according to the embodiment of the present invention one;
Fig. 4 shows the distribution schematic diagram of doping particle concentration in low-resistance region in the manufacture method of the HEMT device that the embodiment of the present invention one provides;
Fig. 6 is the profile of the structure of the HEMT device that the embodiment of the present invention two provides;
Fig. 7 shows the flow chart of the manufacture method of the HEMT device that the embodiment of the present invention two provides;
Fig. 8 is the section of structure of the HEMT device that the embodiment of the present invention three provides;
Fig. 9 shows the flow chart of the manufacture method of the HEMT device that the embodiment of the present invention three provides;
Figure 10 a-Figure 10 g, Figure 11 show structural section figure corresponding to each step of manufacture method of the HEMT device that the embodiment of the present invention three provides;
Figure 12 is that embodiment of the present invention intermediate ion injects schematic diagram.
Embodiment
Technical scheme of the present invention is further illustrated by embodiment below in conjunction with accompanying drawing.Such as " below ", " below ", " ... under ", " low ", " top ", " ... on ", the spatial relationship term of " height " etc. is used for making description convenient, to explain that an elements relative is in the location of the second element, represent except the orientation different from those orientations shown in figure, these terms are intended to the different orientation containing device.In addition, such as " element is in another element up/down " can represent that two elements directly contact, and also can represent also have other elements between two elements.In addition, such as the term of " first ", " second " etc. is also for describing each element, district, part etc., and should not be taken as restriction.Similar term is element like representation class in description in the whole text.
Embodiment one
Fig. 1 shows the structural representation of the HEMT device that the embodiment of the present invention one provides.As shown in Figure 1, the structure of shown HEMT device comprises: substrate 100; Active area 106, is formed on substrate 100; Barrier region 107, is formed on active area 106; Resistance 112, is formed on barrier region 107, grid 103, is formed on Resistance 112; Low-resistance region 104, be formed in grid 103 both sides, wherein low-resistance region 104 is for sheltering with grid 103, formed by self-registered technology, and described low-resistance region 104 has doping particle, the concentration of described doping particle is positioned at the part corresponding with described active area 106 or the part corresponding with described barrier region 107 at the peak value of vertical direction; And source electrode 108 and drain electrode 109, be respectively formed on the low-resistance region 104 of grid 103 both sides.
Wherein, the material of substrate 100 can be the material of the applicable growth III-V such as sapphire, silicon, carborundum, gallium nitride or rare earth oxide.Preferably, the material of substrate 100 is carborundum.
Wherein, active area 106 can by one deck aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1; ) or multilayer InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1, in each layer, x, y, z is incomplete same) lamination composition.Preferably, the material of active area 106 is GaN.
Wherein, the semi-conducting material that barrier region 107 can form heterojunction with described active area 106 by one or more layers forms, such as InxAlyGazN (0≤x, y, z≤1; X+y+z=1).
The etched speed of material of Resistance 112 is preferably lower than the etched speed of grid 103 material, or the etched speed of the material on barrier layer 111 is preferably lower than the lamination of grid 103 material and semi-conducting material or insulating material, wherein, described semi-conducting material can be InxAlyGazN (0≤x, y, z≤1; X+y+z=1) etc., described insulating material can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc., and the benefit of process is like this to protect described barrier layer 102 when etching grid 103 material, reduces the etching injury of barrier layer 102.
Wherein, grid 103 can be conductivity gate, also can be the grid that other and barrier region form non-ohmic contact.Grid 103 can comprise gate medium 1031 and refractory material 1032, described gate medium 1031 can reduce the leakage current of grid 103, described gate medium 1031 is formed between Resistance 112 and refractory material 1032, the fusing point of described refractory material 1032 higher than the impurity annealing activationary temperature when utilizing doping to form low-resistance region 104 and low-resistance region 104 and source electrode 108 and drain 109 form ohmic contact time annealing temperature.The optional material of refractory material 1032 be selected from following group one or more: tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride; Or be the nitride of the material in described group; Or be the alloy of the material in described group, or be the lamination of material in described group; Or be the lamination of the alloy of the material in the nitride of the material in material in described group or described group or described group; Or be the alloy of material in the nitride of the material in material in described group or described group or described group or the lamination of insulating material.
Because grid 103 have employed refractory material, forming low-resistance region 104 and source electrode 108 subsequently and draining in the process of 109, avoiding the grid knot degeneration that high annealing causes, thus improve rate of finished products and the reliability of device.
In order to reduce low-resistance region 104 and grid 103 short circuit possibility, and reduce the leakage current between low-resistance region 104 and grid 103, the peak value of the concentration in the vertical direction of the particle that adulterates in low-resistance region 104 is positioned at active area 106 or barrier region 107.Can adjust according to real needs for the width of low resistance region at vertical direction, this is that those skilled in the art can realize.
Preferably, in order to reduce low-resistance region 104 and grid 103 short circuit possibility further, and the leakage current reduced between low-resistance region 104 and grid 103, described low-resistance region 104 towards the surface of grid 103 side lower than the surface towards gate electrode side of described Resistance 112.
Wherein, source electrode 108 and drain electrode 109 are respectively formed on the low-resistance region 104 of grid 103 both sides, and contact type is ohmic contact, form the fusing point of annealing temperature lower than grid refractory material of ohmic contact.Wherein, the lateral separation of described source electrode and drain electrode distance grid can be greater than the lateral separation of source area and drain region distance grid respectively.
Below, the manufacture method that the present invention realizes above-mentioned HEMT device is elaborated.
Fig. 2 shows the manufacture method flow chart of the HEMT device that the embodiment of the present invention one provides, and as shown in Figure 2, the manufacture method of shown HEMT device comprises step:
Step S11, on substrate, be formed with active layer;
Step S12, on described active layer, form barrier layer;
Step S13, on described barrier layer, form barrier layer;
Step S14, on described barrier layer, form grid;
Step S15, with described grid for sheltering, form Resistance, active area and barrier region by self-registered technology in formation low-resistance region, described grid both sides, wherein said low-resistance region has doping particle; And
Step S16, on the low-resistance region of described grid both sides, form source electrode and drain electrode respectively.
Fig. 3 a-3f, 5a-5c show structural section figure corresponding to each step of manufacture method of the HEMT device provided according to the embodiment of the present invention one.
As shown in Figure 3 a, substrate 100 is provided.
The material of substrate 100 can be the material of the applicable growth III-V such as sapphire, silicon, carborundum, gallium nitride or rare earth oxide.Preferably, the material of substrate 100 is gallium nitride.
As shown in Figure 3 b, active layer 101 is formed on the substrate 100.
Active layer 101 can by some layers of aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1; ) or some layers of InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1, in each layer, x, y, z is different) form with the lamination of semi-conducting material.Preferably, the material of active layer 101 is GaN.The method being formed with active layer includes but not limited to chemical vapor deposition (CVD), hydride gas-phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc.
As shown in Figure 3 c, active layer 101 forms barrier layer 102.
The semi-conducting material that barrier layer 102 can form heterojunction with active layer 101 by one or more layers forms, such as InxAlyGazN (0≤x, y, z≤1; X+y+z=1).The method forming barrier layer 102 includes but not limited to chemical vapor deposition (CVD), hydride gas-phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc.
Preferably, barrier layer 102 can form semi-conducting material (such as InxAlyGazN (0≤x, y, z≤1 of heterojunction with described active area 101 by one or more layers; X+y+z=1)) form with the lamination of insulating material formed thereon.
As shown in Figure 3 d, barrier layer 102 forms barrier layer 111.
One or more materials in the material on barrier layer 111 by etch-rate preferably lower than the etched speed of one or more materials in grid 103 material.
Preferably, the material on described barrier layer 111 is non-crystalline material.
Preferred particularly, in embodiment one, the material on barrier layer 111 is aluminium nitride.
The benefit of such process is to protect described barrier layer 102 not to be etched when etching grid 103 material.When adopting the method for ion implantation to form low-resistance region 104 on the other hand, described barrier layer 102 material can weaken channeling effect during injection, thus can control more accurately to inject ion distribution.
As shown in Figure 3 e, barrier layer 111 forms grid 103, grid 103 can be conductivity gate, also can be the grid that other and barrier region form non-ohmic contact.
Wherein, described grid 103 material can be refractory conductive material, or refractory conductive material and some layers of InxAlyGazN (0≤x, y, z≤1; X+y+z=1) or the lamination of dielectric material, described dielectric material can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc.
The fusing point of described refractory conductive material is higher than impurity annealing activationary temperature when utilizing doping to form low-resistance region in step afterwards and in low-resistance region and source electrode and the annealing temperature that drains when forming ohmic contact.Optional material be selected from following group one or more: tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride; Or be the nitride of the material in described group; Or be the alloy of the material in described group; Or be the lamination of material in described group; Or be the lamination of the alloy of the material in the nitride of the material in material in described group or described group or described group; Or be the alloy of material in the nitride of the material in material in described group or described group or described group or the lamination of insulating material, described insulating material is for reducing the leakage current of grid.
Preferably, the described grid 103 that formed on barrier layer 111 can comprise: on barrier layer 111, form gate medium 1031, described gate medium 1031 forms refractory material 1032.The material of described gate medium 1031 can be silicon nitride (SiN), and the growing method of described refractory material 1032 can be sputtering etc.
Preferably, the minimizing technology of grid refractory material adopts etching technics.First on the gate medium 1031 on surface, barrier layer 111, grow refractory material 1032, then form mask at area of grid, and the refractory material 1032 removed outside masked areas and gate medium 1031, finally remove mask and form grid 103.The be etched speed etch rate lower than refractory material 1032 of described mask when refractory material 1032 etches.Described gate medium 1031 can reduce the leakage current of grid 103.
Optionally, the minimizing technology of grid refractory material can also be stripping technology.Adopt stripping technology can avoid in etching technics, etching the barrier layer damage caused.
In the present embodiment, because grid 103 have employed refractory material, forming low-resistance region 104 and source electrode 108 subsequently and draining in the process of 109, avoiding the grid knot degeneration that high annealing causes, thus improve rate of finished products and the reliability of device.
As illustrated in figure 3f, with described grid 103 for sheltering, by self-registered technology in formation low-resistance region, described grid 103 both sides 104, and form Resistance 112, active area 106 and barrier region 107.
Wherein, described low-resistance region 104 has doping particle, in order to reduce the possibility of low-resistance region 104 and grid 103 short circuit, and the leakage current reduced between low-resistance region 104 and grid 103, the concentration of the particle that adulterates in low-resistance region 104 is positioned at the part corresponding with described active area 106 or the part corresponding with described barrier region 107 at the peak value of vertical direction.
As shown in Figure 4, Fig. 4 shows the curve synoptic diagram of doping particle concentration in low-resistance region in the manufacture method of the HEMT device that the embodiment of the present invention one provides, in figure, dotted line 1 represents in low-resistance region 104 that the concentration of the particle that adulterates is positioned at the part corresponding with active area 106 at the peak value of vertical direction, and solid line 2 represents in low-resistance region 104 that the concentration of the particle that adulterates is positioned at the part corresponding with barrier region 107 at the peak value of vertical direction.Can adjust according to real needs for the width of low resistance region at vertical direction, this is that those skilled in the art can realize.
In order to form such low-resistance region 104, in one example, step S15 comprises:
Adulterate in step S151, the employing region of ion implantation to grid 103 both sides, wherein doped chemical can be Si, and overall doping content is 1 × 10 19cm -3magnitude.Wherein doping depth is in active area 106 or barrier region 107, be doped formation low-resistance region, region 104 (as illustrated in figure 3f), the barrier layer be not doped, barrier layer and active layer form Resistance 112 respectively, barrier region 107 and active area 106, and the concentration of wherein said doping particle is positioned at the part corresponding with described active area 106 or the part corresponding with described barrier region 107 at the peak value of vertical direction, this can realize by regulating the distribution of Doped ions, such as form Gaussian Profile, the corresponding active area 106 of peak value of Gaussian Profile or barrier region 107.
Because barrier layer 111 is non-crystalline material, when adopting the region of ion implantation to grid 103 both sides to carry out doping formation low-resistance region 104, barrier layer 111 reduces injects the channeling effect of ion at barrier layer and active layer, thus can control more accurately to inject ion distribution.
In this example, in order to reduce the possibility of low-resistance region 104 and grid 103 short circuit further, and reduce the leakage current between low-resistance region 104 and grid 103, before adulterating to the region of grid 103 both sides, described method also comprises:
Step S150, with grid 103 for sheltering, remove the barrier layer of the whole thickness in grid 103 both sides and the barrier layer (as shown in Figure 5 a) of part thickness, or remove the barrier layer 102 of whole thickness barrier layer, grid both sides 111 and whole thickness to expose described active layer 101 (as shown in Figure 5 b), or remove the barrier layer 111 of grid both sides whole thickness and the barrier layer 102 of whole thickness and the active layer 101 (as shown in Figure 5 c) of part thickness, not removed part forms Resistance 112, active area 106 and barrier region 107.Like this, low-resistance region 104 and grid 103 in the vertical direction of formation have segment distance, can realize above-mentioned purpose.
When adopting the region of ion injection method to grid 103 both sides to carry out doping formation low-resistance region 104, there is following obvious advantage: first, ion implantation technology is relatively ripe, and cost is lower; Secondly ion implantation technology does not need etching and regrowth, decreases processing step, reduces technology difficulty, improve the reliability and stability of technique.
In the present embodiment, utilizing grid as sheltering, forming low-resistance region by self-registered technology, effectively can shorten grid spacing and grid leak distance, and without the need to alignment, technique is simple.As shown in figure 3g, the low-resistance region 104 of grid 103 both sides is formed respectively source electrode 108 and drain electrode 109.
When adopting the region of ion implantation to grid 103 both sides to carry out doping formation source and drain low-resistance region 104, need in consideration two when annealing, be on the one hand the annealing conditions activating highly doped impurity thus formed required for low-resistance region 104, be low-resistance region 104 on the other hand with source electrode 108 and drain and 109 form annealing conditions required for good ohmic contact.Preferably, annealing temperature is lower than the fusing point of grid refractory material.
Wherein, described source electrode 108 and drain electrode 109 are formed the lateral separation being greater than source area and drain region distance grid apart from the lateral separation of grid respectively.
In the present embodiment, adopt ion implantation technology in formation low-resistance region, grid both sides, then form source electrode and drain electrode respectively on low-resistance region, effectively improve the ohmic contact characteristic of source-drain electrode, reduce ohmic contact resistance, thus improve the high frequency performance of device.
The manufacture method of the HEMT device that the embodiment of the present invention one provides and HEMT device, shortens grid spacing and grid leak distance effectively by source and drain self-registered technology, reduces grid source series resistance and grid leak series resistance, improves the high frequency characteristics of device; And low-resistance region does not need to carry out accurate alignment when being formed, reduce the requirement to photoetching process alignment precision, the rate of finished products that improve device reduces production cost, by increasing barrier layer between barrier layer and grid, the etch damage of barrier layer can be reduced, and channeling effect when can reduce ion implantation, thus control the distribution of injecting ion better.Further, in a preferred embodiment of the invention, grid employing refractory material avoids the grid knot degeneration that ohmic contact high annealing causes, and improves rate of finished products and the reliability of device; Highly doped or the source and drain regrowth process of source and drain effectively improves the ohmic contact characteristic of source-drain electrode, reduces ohmic contact resistance, thus improves the high frequency performance of device.
Embodiment two
Fig. 6 is the profile of the structure of the HEMT device that the embodiment of the present invention two provides, as shown in Figure 6.The identical Reference numeral of element identical in Fig. 6 and Fig. 3 g represents.
The structure of shown HEMT device comprises: substrate 100; Resilient coating 110, is formed on substrate 100; Active area 106, is formed on resilient coating 110; Barrier region 107, is formed on active area 106; Resistance 112, is formed on barrier region 107, grid 103, is formed on Resistance 112; Grid curb wall 113 and 114, lays respectively at grid 103 both sides; Low-resistance region 104, be formed in grid 103 both sides, wherein low-resistance region 104 is for sheltering with grid 103, formed by self-registered technology, and described low-resistance region 104 has doping particle, the concentration of described doping particle is positioned at the part corresponding with described active area 106 or the part corresponding with described barrier region 107 at the peak value of vertical direction; And source electrode 108 and drain electrode 109, be respectively formed on the low-resistance region 104 of grid 103 both sides.
Below, the manufacture method that the present invention realizes above-mentioned HEMT device is elaborated.
Fig. 7 shows the flow chart of the manufacture method of the HEMT device that the embodiment of the present invention two provides, and as shown in Figure 7, the manufacture method of described HEMT device comprises:
Step S21, on substrate, form resilient coating;
Step S22, on described resilient coating, be formed with active layer;
Step S23, on described active layer, form barrier layer;
Step S24, on described barrier layer, form barrier layer;
Step S25, on described barrier layer, form grid;
Step S26, on described grid both sides or described grid both sides and grid, form grid curb wall;
Step S27, with described grid for sheltering, form Resistance, active area and barrier region by self-registered technology in formation low-resistance region, described grid both sides, wherein said low-resistance region has doping particle; And
Step S28, on the low-resistance region of described grid both sides, form source electrode and drain electrode respectively.
The embodiment of the present invention two is based on above-described embodiment one, be with first difference of embodiment one, the embodiment of the present invention two defines resilient coating 110 between substrate 100 and active layer 101, the benefit of such process is to reduce the lattice mismatch between substrate 100 and active area 101, thus improves the lattice quality of active area 101.The material of resilient coating 110 can by one deck aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1; ) or multilayer InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1, in each layer, x, y, z is different) lamination composition or by some layers of InxAlyGazN (0≤x, y, z≤1; X+y+z=1) with the lamination of semi-conducting material.
Particularly, resilient coating 110 can comprise the nucleating layer 1101 of growth on substrate 100 and the transition zone 1102 grown on nucleating layer 1101.Nucleating layer 1101 is for reducing the lattice mismatch between substrate 100 and transition zone 1102.Transition zone 1102 is for improving the lattice quality of active area 106.The lattice quality of active area 106 is better than the lattice quality of resilient coating 110, and the carrier mobility of active area 106 material is higher than resilient coating 110 material.
Concrete preferred, resilient coating 110 also can comprise the transition zone 1102 of growth on substrate 100, and (the sectional view structure of HEMT device is identical with the structure in Fig. 6 in this case with the back of the body barrier layer 1103 grown on transition zone, not shown), the material of described transition zone 1102 can by one deck aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1; ) or multilayer InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1, in each layer, x, y, z is different) lamination composition or by some layers of InxAlyGazN (0≤x, y, z≤1; X+y+z=1) with the lamination of semi-conducting material, transition zone 1102 for improving the lattice quality of active area 106, material some layers of InxAlyGazN (0≤x, y, z≤1 of described back of the body barrier layer 1103; Or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of semi-conducting material, back of the body barrier layer 1103 is for improving the confinement of active area 106 charge carrier.
The embodiment of the present invention two, based on above-described embodiment one, is with second difference of embodiment one, after grid 103 is formed, forms grid curb wall 114 and 113 on grid 103 both sides or grid 103 both sides and grid 103.
The material of grid curb wall 113 and 114 is insulating material, can be silicon nitride, aluminium oxide or silica etc., can be used for avoiding low-resistance region 104 and grid 103 short circuit further, and the leakage current reduced between low-resistance region 104 and grid 103, grid curb wall 113 and 114 can improve the breakdown characteristics of device further and reduce gate leakage current.
Concrete preferred, form grid curb wall 114 and 113 in grid 103 both sides can comprise: the device after forming grid 103 forms second dielectric layer, then photoetching is carried out at device surface, with photoresist grid 103 and side wall 114 and 113 are covered, the horizontal width of side wall 114 and 113 can cover control by photoresist, then etch away not by second dielectric layer that photoresist is covered, finally remove photoresist and the second dielectric layer etched away above grid 103, then can form horizontal width can freely regulated side wall 114 and 113.Alternatively, after removing above-mentioned photoresist, can not second dielectric layer above etching grid 103, namely on side wall 114 and 113 both sides that can be formed at grid 103 and described grid 103.
Preferably, the lateral dimension of the side wall 114 of close drain electrode 109 sides is greater than the lateral dimension of the side wall 113 near source electrode 108 side.Increase side wall 114 lateral dimension can increased device grid leak apart from thus improve the puncture voltage of device, and the lateral dimension reducing side wall 113 can reduce the resistance between grid source, thus improves direct current and the microwave property of device.
The embodiment of the present invention two is based on above-described embodiment one, be with the 3rd difference of embodiment one, described step S26 adopt the region of ion injection method to grid 103/ grid 103 and grid curb wall 113 and 114 both sides carry out doping form source and drain low-resistance region 104 time, the incident direction of ion implantation is not vertical with the interface of active layer 101 with barrier layer 102, but has certain inclination angle.As shown in figure 12, the interface vertical direction angle along clockwise direction namely injecting ion incidence direction and barrier layer 102 and active layer 101 is that the scope of α, α is less than or equal to 40 degree for being more than or equal to 0 degree to schematic diagram.
Due to the stop of the shadow effect of ion implantation and grid 103/ grid curb wall 113 and 114 during injection, the lateral separation on the right side of the low-resistance region of 109 sides and grid 103/ grid curb wall 114 that drains is not 0, as length L in Figure 12, and this distance can be regulated by the inclination alpha of ion implantation.On the right side of the low-resistance region and the grid 103 that increase drain electrode 109 side, lateral separation increases grid leak distance, thus can improve the breakdown characteristics of device and reduction gate leakage current.
The manufacture method of the HEMT device that the embodiment of the present invention two provides and HEMT device, shortens grid spacing and grid leak distance effectively by source and drain self-registered technology, reduces grid source series resistance and grid leak series resistance, improves the high frequency characteristics of device; And low-resistance region does not need to carry out accurate alignment when being formed, reduce the requirement to photoetching process alignment precision, the rate of finished products that improve device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce the etch damage of barrier layer.Further, in a preferred embodiment of the invention, grid employing refractory material avoids the grid knot degeneration that ohmic contact high annealing causes, and improves rate of finished products and the reliability of device; The highly doped technique of source and drain effectively improves the ohmic contact characteristic of source-drain electrode, reduce ohmic contact resistance, in addition, by increasing resilient coating between substrate and active layer, the lattice mismatch between substrate and active layer can be reduced, thus improve the high frequency performance of device.Grid curb wall and angle-tilt ion are injected and can be regulated grid spacing and grid leak distance, the low gate leakage current of a step-down thus the breakdown characteristics improving device is gone forward side by side.
Embodiment three
Fig. 8 is the section of structure of the HEMT device that the embodiment of the present invention three provides, and as shown in Figure 8, the HEMT device that the present embodiment three provides comprises: substrate 201; Resilient coating 202, this resilient coating 202 is formed on substrate 201; Active area 210, this active area 210 is formed on resilient coating 202; Barrier region 211, this barrier region 211 is formed on active area 210; Resistance 212, this Resistance 212 is formed on barrier region 211; Grid 206, this grid 206 is formed on Resistance 212; Grid curb wall 215 and 216, this grid curb wall 215 and 216 is formed at grid 206 both sides or is formed on grid 206 both sides and grid 206; Low-resistance region 207, is formed in grid 203 both sides, wherein, low-resistance region 207 be with grid 206 for sheltering, formed by self-registered technology, and described low-resistance region 207 has doping particle; Source electrode 208 and drain electrode 209, be respectively formed on the low-resistance region 207 of grid 206 both sides.
Wherein, described substrate 201 can be the material of the applicable growth III-V such as sapphire (Sapphire), SiC, GaN, Si or rare earth oxide, and specifically preferably, the material of substrate 201 is GaN.
Wherein, described resilient coating 202 material is some layers of InxAlyGazN (0≤x, y, z≤1; Or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of other semi-conducting material.Specifically preferably, resilient coating 202 comprises the transition zone 2021 of growth on substrate 201 and the back of the body barrier layer 2022 grown on transition zone 2021; Transition zone 2021 is some layers of InxAlyGazN (0≤x, y, z≤1; Or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of other semi-conducting material; Back of the body barrier layer 2022 is some layers of InxAlyGazN (0≤x, y, z≤1; Or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of other semi-conducting material, for improving the confinement of channel carrier, other dielectric material described can be semi-conducting material or insulating material.
Described active area 210 is formed on resilient coating 202, and the material of active area 210 can be some layers of aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1; ) or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of other semi-conducting material, particularly, the material of active area 210 is GaN, and the lattice quality of active area 210 is better than resilient coating 202 material, and the carrier mobility of active area 210 material is higher than resilient coating 202 material.
Described barrier region 211 is formed on active area 210, barrier region 211 is that some layers can form the semi-conducting material of heterojunction with described active area 210 or some layers can form the semi-conducting material of heterojunction and the lamination of insulating material with described active area materials, described semi-conducting material is as InxAlyGazN (0≤x, y, z≤1; X+y+z=1) etc., described insulating material is as silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc.
Described Resistance 212 is formed on barrier region 211, and when the material of Resistance 212 is etching grid refractory material, etch rate is lower than the material of etch rate far below grid refractory material when the material of grid refractory material or etching grid refractory material and the lamination of other semi-conducting material or insulating material; Described grid 206 refractory material refers to the material of the fusing point of this material higher than source and drain annealing temperature in manufacturing process of the present invention, during described etching grid refractory material, etch rate can be InxAlyGazN (0≤x far below the material of grid refractory material, y, z≤1; X+y+z=1) etc., other semi-conducting material described can be InxAlyGazN (0≤x, y, z≤1; X+y+z=1) etc., described insulating material can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc.
Particularly, in the embodiment of the present invention three, Resistance 212 comprises the anti-etching district 2121 of growth on barrier region 211 and the first medium district 2122 of growth in anti-etching district 2121; The material in anti-etching district 2121 etch rate when etching grid material, lower than one or more in grid material, does not affect by etching for the protection barrier region 211 when etching grid material; First medium district 2122 is insulating material, can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc., for reducing the leakage current of grid 206.
Wherein, described grid 206 is formed on Resistance 212, and grid 206 can be conductivity gate, also can be the grid that other and barrier region form non-ohmic contact, and described grid 206 material is refractory material.
Described grid 206 material can be refractory material, or refractory conductive material and some layers of InxAlyGazN (0≤x, y, z≤1; Or the lamination of dielectric material x+y+z=1).Annealing temperature when described refractory material refers to that fusing point forms ohmic contact higher than low-resistance region 207 and drain electrode 209 and source electrode 208.Described dielectric material can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc., the optional material of grid 206 refractory material be selected from following group one or more: tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride; Or be the nitride of the material in described group; Or be the alloy of the material in described group, or be the lamination of material in described group; Or be the lamination of the alloy of the material in the nitride of the material in material in described group or described group or described group; Or be the alloy of material in the nitride of the material in material in described group or described group or described group or the lamination of insulating material, described insulating material is for reducing the leakage current of grid.Particularly, in the present embodiment, grid 206 material can be the lamination of tungsten (W) and molybdenum (Mo).
In the present embodiment, because grid 206 have employed refractory material, forming low-resistance region 207 and source electrode 208 subsequently and draining in the process of 209, avoiding the grid knot degeneration that high annealing causes, thus improve rate of finished products and the reliability of device.
Described grid curb wall 215 and 216 material is insulating material, can be SiN, SiO2, Al2O3 or HfO 2deng, for preventing grid 206 and source electrode 208 or 209 short circuits that drain, and reduce the leakage current of grid 206.Particularly, in the present embodiment, the material of grid curb wall 215 and 216 can be SiN.
Wherein, described low-resistance region 207 is formed by self-registered technology and regrowth techniques, and low-resistance region 207 is containing doping particle.
Described source electrode 208 and drain electrode 209 are formed on the low-resistance region 207 of grid 206 both sides respectively, and the contact type of source electrode 208 and drain electrode 209 is ohmic contact.Form the fusing point of annealing temperature lower than grid 206 refractory material of ohmic contact.Wherein, the lateral separation of described source electrode 208 and drain electrode 209 distance grid 206 can be greater than the lateral separation of low-resistance region 207 apart from grid 206 respectively.
Below, the manufacture method that the present invention realizes above-mentioned HEMT device is elaborated.
Fig. 9 shows the flow chart of the manufacture method of the HEMT device that the embodiment of the present invention three provides, and as shown in Fig. 9, the manufacture method of described HEMT device comprises:
Step S31, on the substrate 201 formation resilient coating 202;
Step S32, on resilient coating 202, be formed with active layer 203;
Step S33, on active layer 203, form barrier layer 204;
Step S34, on barrier layer 204, form barrier layer 205;
Step S35, on barrier layer 205, form grid 206;
Step S36, on grid 206 both sides or grid 206 both sides and grid 206, form grid curb wall 215 and 216;
Step S37, with grid 206 for sheltering, the region of grid 206 both sides is etched, the barrier layer 204 on the barrier layer 205 and whole thickness of removing the whole thickness in grid 206 both sides is to expose active layer 203, or remove the barrier layer 205 of grid 206 both sides whole thickness and the barrier layer 204 of whole thickness and the active layer 203 of part layer thickness, not removed barrier layer 205, barrier layer 204 and active layer 203 form Resistance 212, barrier region 211 and active area 210 respectively;
Step S38, employing regrowth techniques have the semi-conducting material of doping particle at the new region of growth of Regional Gravity of grid 206 both sides etched, form low-resistance region 207;
Step S39, formed respectively on the low-resistance region 207 of grid 206 both sides source electrode 208 and drain electrode 209.
Figure 10 a-Figure 10 g shows structural section figure corresponding to each step of manufacture method of the HEMT device that the embodiment of the present invention three provides.
As shown in Figure 10 a, illustrated in Figure 10 a that in the embodiment of the present invention three, step S31 is to step S34, be namely formed with active layer 203, barrier layer 204 and barrier layer 205 on the substrate 201 successively.
Described resilient coating 202 is some layers of InxAlyGazN (0≤x, y, z≤1; Or InxAlyGazN (0≤x, y, z≤1 x+y+z=1); X+y+z=1) with the lamination of other semi-conducting material.
Particularly, in the present embodiment, step S31 forms resilient coating 202 on the substrate 201 can comprise growth transition zone 2021 on the substrate 201, and transition zone 2021 is formed back of the body barrier layer 2022.Transition zone 2021 is for improving the crystal mass of active layer 203; Back of the body barrier layer is for improving the confinement of channel carrier.
The method that resilient coating 202 is formed active layer 203 includes but not limited to chemical vapor deposition (CVD), hydride gas-phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc.
Described barrier layer 204 is that some layers can form the semi-conducting material of heterojunction with described active layer 203 or some layers can form the semi-conducting material of heterojunction and the lamination of insulating material with described active layer 203 material, described semi-conducting material is as InxAlyGazN (0≤x, y, z≤1; X+y+z=1) etc., described insulating material is as silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc.The method forming barrier layer includes but not limited to chemical vapor deposition (CVD), hydride gas-phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc.
Particularly, in the present embodiment, barrier layer 204 is formed barrier layer 205 can be comprised: on barrier layer 204, form etch-resistant layer 2051, and etch-resistant layer 2051 is formed first medium layer 2052.The material of etch-resistant layer 2051 etch rate when etching grid material, lower than one or more in grid material, does not affect by etching for the protection barrier layer 204 when etching grid material; The material of first medium layer 2052 is insulating material, can be silicon nitride, aluminium oxide or silicon dioxide or hafnium oxide etc., for reducing gate leakage current.Preferred particularly, barrier layer 205 material is aluminium nitride in the present embodiment.The benefit of such process is to protect when etching grid 206 material described barrier layer 204 not to be etched impact.
As shown in fig. lob, barrier layer 205 grows refractory material and form grid 206.Grid 206 can be conductivity gate, also can be the grid that other and barrier region form non-ohmic contact.
The fusing point of described refractory conductive material is higher than impurity annealing activationary temperature when utilizing regrowth process to form low-resistance region in step afterwards and in low-resistance region and source electrode and the annealing temperature that drains when forming ohmic contact.
Preferably, the minimizing technology of grid refractory material is for adopting etching technics.First at barrier layer 205 superficial growth one deck tungsten/molybdenum lamination, then form mask at area of grid, use sulphur hexafluoride (SF 6) get rid of tungsten/molybdenum lamination outside masked areas, thus form grid 206.Due to SF 6to the etch rate of tungsten/molybdenum much larger than the etch rate to barrier layer 205AlN, barrier layer 204 is protected not by SF in barrier layer 205 6etching impact.
Optionally, the minimizing technology of grid refractory material can also be stripping technology.Adopt stripping technology can avoid in etching technics, etching the barrier layer damage caused.
As shown in Figure 10 c and Figure 10 d, after grid 206 is formed, in the superficial growth second dielectric layer 213 of barrier layer 205 and grid 206, then the second dielectric layer except gate edge is removed, thus form grid curb wall 215 and 216, second dielectric layer is insulating material, can be SiN, SiO2, Al2O3 or HfO2 etc.Grid curb wall 215 and 216 for preventing grid 206 and source electrode 209 or 210 short circuits that drain, and reduces the leakage current of grid 206.
As illustrated in figure 10e, with grid 206 and grid curb wall 215 and 216 for sheltering, the region of grid 206 both sides is etched, the barrier layer 204 on the barrier layer 205 and whole thickness of removing the whole thickness in grid 206 both sides is to expose active layer 203, or remove the barrier layer 205 of grid 206 both sides whole thickness and the barrier layer 204 of whole thickness and the active layer 203 of part layer thickness, not removed barrier layer 205, barrier layer 204 and active layer 203 form Resistance 212, barrier region 211 and active area 210 respectively.
As shown in figure 10f, adopt regrowth techniques to have the semi-conducting material of doping particle at the new region of growth of Regional Gravity of grid 206 both sides etched, form low-resistance region 207.
The described semi-conducting material with doping particle can be InxAlyGazN (0≤x, y, z≤1; Or the lamination of other semi-conducting material or these semi-conducting materials x+y+z=1).Wherein doped chemical can be Si, and overall doping content is 1 × 10 19cm -3magnitude.
In this example, in order to reduce low-resistance region 207 and grid 206 short circuit possibility further, and the leakage current reduced between low-resistance region 207 and grid 206, when carrying out the semi-conducting material of regrowth with doping particle to low-resistance region 207, make them towards the surface A of grid 206 side lower than the surperficial B (as shown in figure 11) towards gate electrode side of described Resistance 212.
As shown in Figure 10 g, the low-resistance region 207 of grid 206 both sides forms source electrode 208 and drain electrode 209 respectively.
The contact type of source electrode 208 and drain electrode 209 is ohmic contact, forms the fusing point of the annealing temperature needed for ohmic contact lower than grid 206 refractory material.
The manufacture method of the HEMT device that the embodiment of the present invention three provides and HEMT device, shortens grid spacing and grid leak distance effectively by source and drain self-registered technology, reduces grid source series resistance and grid leak series resistance, improves the high frequency characteristics of device; And low-resistance region does not need to carry out accurate alignment when being formed, reduce the requirement to photoetching process alignment precision, the rate of finished products that improve device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce the etch damage of barrier layer.Further, in a preferred embodiment of the invention, grid employing refractory material avoids the grid knot degeneration that ohmic contact high annealing causes, improve the ohmic contact characteristic that the rate of finished products of device and reliability source and drain regrowth process effectively improve source-drain electrode, reduce ohmic contact resistance, thus improve the high frequency performance of device.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.Each embodiment of the present invention all can mutually combine on the basis of not violating logic.All do within spirit of the present invention and principle any amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (17)

1. a HEMT device, is characterized in that, comprising:
Substrate;
Active area, is formed on described substrate;
Barrier region, is formed on described active area;
Resistance, is formed on described barrier region;
Grid, is formed on described Resistance;
Low-resistance region, be respectively formed at described grid both sides, wherein, described low-resistance region is for sheltering with described grid, formed by self-registered technology, and described low-resistance region has doping particle, the concentration of described doping particle is positioned at the part corresponding with described active area or the part corresponding with described barrier region at the peak value of vertical direction; And
Source electrode and drain electrode, be respectively formed on the low-resistance region of described grid both sides.
2. HEMT device according to claim 1, is characterized in that, the material of described grid is refractory material.
3. HEMT device according to claim 1, is characterized in that, the surface towards gate electrode side of described low-resistance region is lower than the surface towards gate electrode side of described Resistance.
4. HEMT device according to claim 1, is characterized in that, described HEMT device also comprises grid curb wall, is formed at described grid both sides or is formed on described grid both sides and described grid.
5. HEMT device according to claim 1, is characterized in that, described HEMT device also comprises gate medium, is formed between described Resistance and described grid.
6. HEMT device according to claim 1, is characterized in that, described barrier region is the semiconductor material layer forming heterojunction with the material of described active area; Or be
The lamination of semi-conducting material and insulating material formed thereon.
7. HEMT device according to claim 1, is characterized in that, described HEMT device also comprises resilient coating, is formed between described substrate and described active area, for reducing the lattice mismatch between substrate and active area.
8. HEMT device according to claim 2, is characterized in that, described refractory material be selected from following group one or more: tungsten, molybdenum, tantalum, titanium, chromium and tantalum nitride; Or be
The nitride of the material in described group; Or be
The alloy of the material in described group; Or be
The lamination of material in described group; Or be
The lamination of the alloy of the material in the nitride of the material in the material in described group or described group or described group; Or be
The alloy of material in the nitride of the material in the material in described group or described group or described group or the lamination of insulating material.
9. HEMT device according to claim 1, is characterized in that, in the material of described Resistance one or more when described grid etch by etch-rate lower than the etched speed of one or more materials in described grid material.
10. HEMT device according to claim 1, described Resistance comprises:
Anti-etching district, is formed on described barrier region, for reducing the etching injury etching and cause described barrier layer;
First medium district, is formed in described anti-etching district;
Described anti-etching district material by etch-rate preferably lower than the etched speed of one or more materials in described grid material;
The material in described first medium district is insulating material.
11. HEMT device according to claim 4, described grid curb wall regulates at the width in grid source and grid leak direction, and the width of grid leak side grid curb wall is not less than the width of side, grid source grid curb wall.
12. 1 kinds of methods manufacturing HEMT device, is characterized in that, comprise step:
S1, on substrate, be formed with active layer;
S2, on described active layer, form barrier layer;
S3, on described barrier layer, form barrier layer;
S4, on described barrier layer, form grid;
S5, with described grid for sheltering, form Resistance, active area and barrier region by self-registered technology in formation low-resistance region, described grid both sides, wherein said low-resistance region has doping particle; And
S6, form source electrode and drain electrode respectively in the low-resistance region of described grid both sides.
The method of 13. manufacture HEMT device according to claim 12, it is characterized in that, step S5 comprises:
Adulterated in the region of grid both sides, wherein doping depth is in active area or barrier region, be doped formation low-resistance region, region, the barrier layer be not doped, barrier layer and active layer form described Resistance, barrier region and active area respectively, and the concentration of wherein said doping particle is positioned at the part corresponding with described active area or the part corresponding with described barrier region at the peak value of vertical direction.
The method of 14. manufacture HEMT device according to claim 13, is characterized in that, before adulterating to the region of grid both sides, described method also comprises:
With grid for sheltering, remove the barrier layer of the whole thickness in grid both sides and the barrier layer of part thickness, or the barrier layer on the barrier layer and whole thickness of removing grid both sides whole thickness is to expose described active layer, or remove the barrier layer of the whole thickness in grid both sides and the barrier layer of whole thickness and the active layer of part thickness.
The method of 15. manufacture HEMT device according to claim 12, it is characterized in that, step S5 comprises:
With grid for sheltering, the barrier layer on the barrier layer and whole thickness of removing grid both sides whole thickness to expose described active layer, or removes the barrier layer of the whole thickness in grid both sides and the barrier layer of whole thickness and the active layer of part thickness; Not removed barrier layer, barrier layer and active layer form described Resistance, barrier region and active area respectively;
Region growing in grid both sides, with the semi-conducting material of doping particle, forms low-resistance region.
The method of 16. manufacture HEMT device according to claim 12, it is characterized in that, described method also comprises between step S4 and S5: on described grid both sides or described grid both sides and grid, form grid curb wall, described grid curb wall regulates at the width in grid source and grid leak direction, and the width of grid leak side grid curb wall is not less than the width of side, grid source grid curb wall.
The method of 17. manufacture HEMT device according to claim 13, it is characterized in that, when utilizing the region of ion injection method to grid both sides to adulterate, ion implantation direction and barrier layer and active layer interface vertical direction angle are along clockwise direction more than or equal to 0 degree, and are less than or equal to 40 degree.
CN201410509822.2A 2014-09-28 2014-09-28 A kind of HEMT device and its manufacturing method Active CN104465746B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410509822.2A CN104465746B (en) 2014-09-28 2014-09-28 A kind of HEMT device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410509822.2A CN104465746B (en) 2014-09-28 2014-09-28 A kind of HEMT device and its manufacturing method

Publications (2)

Publication Number Publication Date
CN104465746A true CN104465746A (en) 2015-03-25
CN104465746B CN104465746B (en) 2018-08-10

Family

ID=52911510

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410509822.2A Active CN104465746B (en) 2014-09-28 2014-09-28 A kind of HEMT device and its manufacturing method

Country Status (1)

Country Link
CN (1) CN104465746B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107104142A (en) * 2017-05-25 2017-08-29 中国电子科技集团公司第十三研究所 GaNHEMT tube core structures on High resistivity substrate
CN109817710A (en) * 2018-12-29 2019-05-28 英诺赛科（珠海）科技有限公司 High electron mobility transistor and its manufacturing method
CN111081764A (en) * 2019-12-30 2020-04-28 深圳第三代半导体研究院 Transistor with embedded source and drain and preparation method thereof
CN111415987A (en) * 2020-04-09 2020-07-14 浙江大学 Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof
JP7099255B2 (en) 2018-11-01 2022-07-12 富士通株式会社 Compound semiconductor equipment, high frequency amplifier and power supply equipment
WO2024047783A1 (en) * 2022-08-31 2024-03-07 ソニーセミコンダクタソリューションズ株式会社 High electron mobility transistor

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274370A (en) * 1985-05-29 1986-12-04 Fujitsu Ltd Junction type field effect transistor
US5821577A (en) * 1991-01-10 1998-10-13 International Business Machines Corporation Graded channel field effect transistor
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
CN1700414A (en) * 2004-05-21 2005-11-23 株式会社半导体能源研究所 Semiconductor device and electronic device
US20070018199A1 (en) * 2005-07-20 2007-01-25 Cree, Inc. Nitride-based transistors and fabrication methods with an etch stop layer
CN101107713A (en) * 2004-11-23 2008-01-16 克里公司 Cap layers and/or passivation layers for nitride-based transistors, transistor structures and methods of fabricating same
US7556976B2 (en) * 2002-10-25 2009-07-07 The University Of Connecticut Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
CN101663759A (en) * 2007-03-30 2010-03-03 皮科吉加国际公司 Electronic device with improved ohmic contact
CN101853880A (en) * 2010-03-09 2010-10-06 西安电子科技大学 AlGaN/GaN high-electron-mobility transistor and manufacturing method thereof
CN102652363A (en) * 2009-12-23 2012-08-29 英特尔公司 Conductivity improvements for iii-v semiconductor devices
CN102945859A (en) * 2012-11-07 2013-02-27 电子科技大学 GaN heterojunction HEMT (High Electron Mobility Transistor) device
CN103296078A (en) * 2012-02-23 2013-09-11 宜普电源转换公司 Enhancement mode GaN HEMT device having grid spacer and method for fabricating GaN HEMT device
US20140097470A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. High-electron mobility transistor and method of manufacturing the same
CN103797581A (en) * 2011-07-18 2014-05-14 埃皮根股份有限公司 Method for growing iii-v epitaxial layers and semiconductor structure
US20140264379A1 (en) * 2013-03-15 2014-09-18 The Government Of The United States Of America, As Represented By The Secretary Of The Navy III-Nitride P-Channel Field Effect Transistor with Hole Carriers in the Channel

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274370A (en) * 1985-05-29 1986-12-04 Fujitsu Ltd Junction type field effect transistor
US5821577A (en) * 1991-01-10 1998-10-13 International Business Machines Corporation Graded channel field effect transistor
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
US7556976B2 (en) * 2002-10-25 2009-07-07 The University Of Connecticut Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
CN1700414A (en) * 2004-05-21 2005-11-23 株式会社半导体能源研究所 Semiconductor device and electronic device
CN101107713A (en) * 2004-11-23 2008-01-16 克里公司 Cap layers and/or passivation layers for nitride-based transistors, transistor structures and methods of fabricating same
US20070018199A1 (en) * 2005-07-20 2007-01-25 Cree, Inc. Nitride-based transistors and fabrication methods with an etch stop layer
CN101663759A (en) * 2007-03-30 2010-03-03 皮科吉加国际公司 Electronic device with improved ohmic contact
CN102652363A (en) * 2009-12-23 2012-08-29 英特尔公司 Conductivity improvements for iii-v semiconductor devices
CN101853880A (en) * 2010-03-09 2010-10-06 西安电子科技大学 AlGaN/GaN high-electron-mobility transistor and manufacturing method thereof
CN103797581A (en) * 2011-07-18 2014-05-14 埃皮根股份有限公司 Method for growing iii-v epitaxial layers and semiconductor structure
CN103296078A (en) * 2012-02-23 2013-09-11 宜普电源转换公司 Enhancement mode GaN HEMT device having grid spacer and method for fabricating GaN HEMT device
US20140097470A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. High-electron mobility transistor and method of manufacturing the same
CN102945859A (en) * 2012-11-07 2013-02-27 电子科技大学 GaN heterojunction HEMT (High Electron Mobility Transistor) device
US20140264379A1 (en) * 2013-03-15 2014-09-18 The Government Of The United States Of America, As Represented By The Secretary Of The Navy III-Nitride P-Channel Field Effect Transistor with Hole Carriers in the Channel

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107104142A (en) * 2017-05-25 2017-08-29 中国电子科技集团公司第十三研究所 GaNHEMT tube core structures on High resistivity substrate
CN107104142B (en) * 2017-05-25 2023-06-13 中国电子科技集团公司第十三研究所 GaNHEMT die structure on high resistance substrate
JP7099255B2 (en) 2018-11-01 2022-07-12 富士通株式会社 Compound semiconductor equipment, high frequency amplifier and power supply equipment
CN109817710A (en) * 2018-12-29 2019-05-28 英诺赛科（珠海）科技有限公司 High electron mobility transistor and its manufacturing method
CN111081764A (en) * 2019-12-30 2020-04-28 深圳第三代半导体研究院 Transistor with embedded source and drain and preparation method thereof
CN111415987A (en) * 2020-04-09 2020-07-14 浙江大学 Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof
WO2024047783A1 (en) * 2022-08-31 2024-03-07 ソニーセミコンダクタソリューションズ株式会社 High electron mobility transistor

Also Published As

Publication number Publication date
CN104465746B (en) 2018-08-10

Similar Documents

Publication Publication Date Title
US10756207B2 (en) Lateral III-nitride devices including a vertical gate module
US10991819B2 (en) High electron mobility transistors
US10749021B2 (en) Semiconductor device and method for manufacturing the same
US9685525B2 (en) Sidewall passivation for HEMT devices
US8809987B2 (en) Normally-off III-nitride metal-2DEG tunnel junction field-effect transistors
US9130026B2 (en) Crystalline layer for passivation of III-N surface
CN1998085B (en) Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions
US8723226B2 (en) Manufacturable enhancement-mode group III-N HEMT with a reverse polarization cap
CN110392929A (en) Gallium nitride transistor
US8962461B2 (en) GaN HEMTs and GaN diodes
US20050173728A1 (en) Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same
US20070164321A1 (en) Methods of fabricating transistors including supported gate electrodes and related devices
CN104465746A (en) HEMT device and manufacturing method of HEMT device
US10388753B1 (en) Regrowth method for fabricating wide-bandgap transistors, and devices made thereby
KR20140042871A (en) Current aperture vertical electron transistors
US9076763B2 (en) High breakdown voltage III-nitride device
US20150060861A1 (en) GaN Misfets with Hybrid AI203 As Gate Dielectric
TWI675480B (en) Heterojunction field effect transistor and manufacturing method thereof
CN103426914A (en) Heterojunction semiconductor device and manufacturing method
CN104638010A (en) Transversely turned-on GaN normally closed MISFET (Metal-insulator-semiconductor Field Effect Transistor) device and manufacturing method thereof
Kim et al. Normally-off GaN MOSFETs on insulating substrate
CN104201199A (en) Enhanced semiconductor device and semiconductor integrated circuit device
KR101103774B1 (en) Nitride based semiconductor device employing recessed gate edge structure and method for fabricating the same
KR20110058332A (en) Enhancement nitride based semiconductor device employing floating gate structure
JP2016521460A (en) Method for forming an implantation region normally disturbed in a heterojunction transistor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant