CN104465736A - Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor - Google Patents
Folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and manufacturing method of folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor Download PDFInfo
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- 238000006243 chemical reaction Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
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- 238000009826 distribution Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
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- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The invention relates to a folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor. Compared with MOSFETs or TFETs devices in the same size, the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor has the advantages of low stray capacitance and low reverse leakage current. The excellent switching characteristic is achieved through the quite-sensitive mutual relation between impedance of a tunneling insulating layer and the internal field intensity of the tunneling insulating layer; tunneling signals are enhanced through an emitting electrode to achieve the excellent forward-direction breakover characteristic. In addition, the invention further provides a specific manufacturing method for the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor and an array of the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor. By means of the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor, the operating characteristic of a nanometer-grade integrated circuit unit is obviously improved; the folding-grating-embedded saddle-shaped insulation tunneling strengthening transistor is suitable for application and popularization.
Description
Technical field:
The present invention relates to very lagre scale integrated circuit (VLSIC) and manufacture field, relate to structure and manufacture method thereof that a kind of embedded folding grid shape of a saddle insulation tunnelling being applicable to high-performance superelevation integrated level IC manufacturing strengthens transistor.
Background technology:
Current, along with constantly the reducing of elementary cell mos field effect transistor (MOSFETs) device size of integrated circuit, distance between drain electrode and gate electrode or the distance between source electrode and gate electrode also constantly reduce thereupon, this just makes the grid source of device, source grid, grid leak and drain-gate parasitic capacitance enlarge markedly, the power consumption of integrated circuit is increased, the propagation delay of signal and negative feedback are increased, and affects gain band width product.
On the other hand, the continuous shortening of MOSFETs device channel length result in the obvious decline of devices switch characteristic.Be embodied in that subthreshold swing increases along with the reduction of channel length, quiescent dissipation obviously increases.Although the degeneration of this device performance can be made to alleviate to some extent by the mode improving gate electrode structure, when device size reduces further, the switching characteristic of device can continue to worsen.
In contrast to MOSFETs device, the tunneling field-effect transistor (TFETs) proposed in recent years, although its average subthreshold swing promotes to some extent, but its forward conduction electric current is too small, and the parasitic capacitance characteristic produced under equidimension there is no improvement.
In addition, TFETs is generated as TFETs tunnelling part by introducing the narrower material of the energy gaps such as compound semiconductor, SiGe or germanium can increase tunnelling probability with lifting switch characteristic, but adds technology difficulty.Adopt high dielectric constant insulating material as the insulating medium layer between grid and substrate, although the control ability of grid to electric field distribution in channel can be improved, but inherently can not improve the tunnelling probability of silicon materials, the forward conduction characteristic therefore for TFETs is improved very limited.
In addition, because TFETs and MOSFETs device is all by the electric field of gate electrode field effect to gate insulator and semiconductor inside, electromotive force and Carrier Profile control, in order to promote the control ability of gate electrode double conductor, high-k and constantly thinning gate insulator need be adopted to strengthen the control ability of gate electrode, but also shorten gate electrode and drain region simultaneously, distance between gate electrode and source region, make grid and drain electrode overlapping region can produce larger grid when being in gate backbias and cause drain leakage (GIDL) electric current or grid causes source leakage (GISL) electric current.
Summary of the invention:
Goal of the invention
For compatibility existing based on the prerequisite of silicon process technology under thoroughly solve because device size constantly reduces the problem that caused parasitic capacitance obviously increases, the reverse leakage current of remarkable reduction device, the switching characteristic of remarkable lifting nanometer-grade IC basic unit device, and guarantee that device has good forward current on state characteristic while reduction subthreshold swing, the invention provides and be a kind ofly applicable to high-performance, the embedded folding grid shape of a saddle insulation tunnelling of high integration IC manufacturing strengthens the structure of transistor and the manufacture method of unit and array thereof.
Technical scheme
The present invention is achieved through the following technical solutions:
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, it is characterized in that: adopt the SOI wafer comprising monocrystalline substrate 1 and wafer insulating barrier 2 as the substrate of generating device; Emitter region 3, base 4 and collector region 5 are positioned at the top of the wafer insulating barrier 2 of SOI wafer, and base 4 has groove type structure; Between emitter region 3 and collector region 5; Emitter 9 is positioned at the top of emitter region 3; Collector electrode 10 is positioned at the top of collector region 5; Shape of a saddle conductive layer 6 is attached to upper surface and the both sides sidewall of base 4 groove inner wall and bottom portion of groove mid portion, has saddle-shaped configuration; Shape of a saddle tunneling insulation layer 7 is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle conductive layer 6 shape of a saddle inwall and the shape of a saddle, has saddle-shaped configuration; Folding gate electrode 8 is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle tunneling insulation layer 7 shape of a saddle inwall and the shape of a saddle; Barrier insulating layer 11 is dielectric.
For reaching device function of the present invention, the present invention proposes a kind of embedded folding grid shape of a saddle insulation tunnelling and strengthens transistor, and its core texture is characterized as:
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 are embedded in base 4 groove, and the upper surface of shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 is not higher than groove two ends, base 4 dome top surface.
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 constitute the tunnelling base stage that embedded folding grid shape of a saddle insulation tunnelling strengthens transistor jointly, when there is tunnelling in shape of a saddle tunneling insulation layer 7 under the control of folding gate electrode 8, electric current flow to shape of a saddle conductive layer 6 from folding gate electrode 8 through shape of a saddle tunneling insulation layer 7, and powers for base 4.
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 are all mutually isolated with emitter region 3, emitter 9, collector region 5 and collector electrode 10 by barrier insulating layer 11; Isolated by barrier insulating layer 11 between adjacent emitter region 3 and collector region 5, isolated by barrier insulating layer 11 between adjacent emitter 9 and collector electrode 10.
Shape of a saddle conductive layer 6 and base 4 form ohmic contact, and shape of a saddle conductive layer 6 is metal materials, or with base 4 have identical dopant type and doping content is greater than 10
19the semi-conducting material of every cubic centimetre.
Shape of a saddle tunneling insulation layer 7 is the insulation material layer for generation of tunnelling current.
Between emitter region 3 and base 4, between collector region 5 and base 4, there is opposite impurity type, and form ohmic contact between emitter region 3 and emitter 9, between collector region 5 and collector electrode 10, form ohmic contact.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, for N-type, emitter region 3, base 4 and collector region 5 are respectively N district, P district and N district, its concrete operation principle is: when collector electrode 10 positively biased, and folding gate electrode 8 is when being in electronegative potential, fold and do not form enough electrical potential differences between gate electrode 8 and shape of a saddle conductive layer 6, now shape of a saddle tunneling insulation layer 7 is in high-impedance state, similar to the gate insulator of MOSFET, obvious tunnelling current is not had to pass through, therefore make between base 4 and emitter region 3, to form enough large base electric current and strengthen transistor to drive embedded folding grid shape of a saddle insulation tunnelling, namely device is in off state, along with the rising gradually of folding gate electrode 8 voltage, folding electrical potential difference between gate electrode 8 and shape of a saddle conductive layer 6 increases gradually, electric field strength in shape of a saddle tunneling insulation layer 7 between folding gate electrode 8 and shape of a saddle conductive layer 6 is also increased thereupon gradually, when the electric field strength in shape of a saddle tunneling insulation layer 7 is positioned at below critical value, shape of a saddle tunneling insulation layer 7 remains good high-impedance state, folding electrical potential difference between gate electrode 8 and emitter 9 is almost fallen completely between the inner and outer wall both sides of shape of a saddle tunneling insulation layer 7, also just make the electrical potential difference between base 4 and emitter region 3 minimum, therefore base does not almost have electric current to flow through, therefore device also keeps good off state, and when the electric field strength in shape of a saddle tunneling insulation layer 7 reaches and exceedes critical value, the folding tunnelling that charge carrier can be occurred by shape of a saddle tunneling insulation layer 7 between gate electrode 8 and shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current can along with the increase precipitous rising at a terrific speed of folding gate electrode 8 electromotive force, this just makes shape of a saddle tunneling insulation layer 7 be converted to low resistance state rapidly by high-impedance state in the potential change interval that folding gate electrode 8 is extremely short, when shape of a saddle tunneling insulation layer 7 is in low resistance state, the resistance that now shape of a saddle tunneling insulation layer 7 is formed between folding gate electrode 8 and shape of a saddle conductive layer 6 will much smaller than the resistance formed between shape of a saddle conductive layer 6 and emitter 3, this just makes the electrical potential difference between folding gate electrode 8 and emitter 9 almost drop to completely between base 4 and emitter region 3, define enough large positive bias-voltage, and under the effect of tunneling effect, between the inner and outer wall of shape of a saddle tunneling insulation layer 7, produce a large amount of electronics move, for base 4 provides current source, base 4 electric current is flowed out by collector electrode after emitter region 3 strengthens, now device is in opening.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, in contrast to MOSFETs or TFETs device, the effect of emitter 9 and source electrode is suitable, the effect of collector electrode 10 and drain electrode is suitable, due to folding gate electrode 8, shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are all embedded in the inside of the groove that base 4 is formed, folding gate electrode 8, the embedded folding grid shape of a saddle insulation tunnelling that shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are formed jointly strengthens the tunnelling base stage of transistor and does not have between emitter 9 and collector electrode 10 to form the parallel capacitance structure be similar between MOSFETs or TFETs device gate electrode and drain electrode or between gate electrode and source electrode, avoiding problems the grid source caused because the distance between gate electrode and drain electrode or between gate electrode and source electrode constantly reduces as MOSFETs or TFETs, source grid, the obvious increase of parasitic capacitance between grid leak and drain-gate, namely MOSFETs or TFETs device is contrasted, under same dimension process, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low parasitic capacitance.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, owing to being embedded in the overlapping region between gate electrode and drain electrode or between gate electrode and source electrode do not existed between folding gate electrode 8 in base 4 groove and emitter region 3 or collector region 5 as MOSFETs or TFETs, potential change away from the folding gate electrode 8 of emitter region 3 or collector region 5 can not produce enough strong field effect to emitter region 3 or collector region 5, also the interband tunnelling current effect that emitter region 3 or collector region 5 are caused owing to there is strong band curvature would not be caused, therefore MOSFETs or TFETs device is contrasted, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low reverse leakage current.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, utilize correlation very responsive between shape of a saddle tunneling insulation layer 7 impedance and shape of a saddle tunneling insulation layer 7 electric field intensity inside high, by choosing suitable runnel insulator material to shape of a saddle tunneling insulation layer 7, and to forming the Sidewall Height of shape of a saddle tunneling insulation layer 7, sidewall thickness, in the shape of a saddle, upper surface thickness suitably regulates, just can make the conversion that shape of a saddle tunneling insulation layer 7 realizes between high-impedance state and low resistance state in the potential change interval that folding gate electrode 8 is minimum, more outstanding switching characteristic can be realized.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, the insulation tunnelling current produced flows to base 4 by shape of a saddle conductive layer 6, and carry out signal enhancing through emitter region 3, with general T FETs just utilize tunnelling current between a small amount of semiconductor tape as device On current compared with, there is better forward current on state characteristic, for these reasons, in contrast to general T FETs device, embedded folding grid shape of a saddle insulation tunnelling strengthens transistor and can realize higher forward conduction electric current.
Advantage and effect
Tool of the present invention has the following advantages and beneficial effect:
1. low parasitic capacitance characteristic
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, in contrast to MOSFETs or TFETs device, the effect of emitter 9 and source electrode is suitable, the effect of collector electrode 10 and drain electrode is suitable, due to folding gate electrode 8, shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are all embedded in the inside of the groove that base 4 is formed, folding gate electrode 8, the embedded folding grid shape of a saddle insulation tunnelling that shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are formed jointly strengthens the tunnelling base stage of transistor and does not have between emitter 9 and collector electrode 10 to form the parallel capacitance structure be similar between MOSFETs or TFETs device gate electrode and drain electrode or between gate electrode and source electrode, avoiding problems the grid source caused because the distance between gate electrode and drain electrode or between gate electrode and source electrode constantly reduces as MOSFETs or TFETs, source grid, the obvious increase of parasitic capacitance between grid leak and drain-gate, namely MOSFETs or TFETs device is contrasted, under same dimension process, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low parasitic capacitance.
2. low reverse leakage current
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, owing to being embedded in the overlapping region between gate electrode and drain electrode or between gate electrode and source electrode do not existed between folding gate electrode 8 in base 4 groove and emitter region 3 or collector region 5 as MOSFETs or TFETs, potential change away from the folding gate electrode 8 of emitter region 3 or collector region 5 can not produce enough strong field effect to emitter region 3 or collector region 5, also the interband tunnelling current effect that emitter region 3 or collector region 5 are caused owing to there is strong band curvature would not be caused, therefore MOSFETs or TFETs device is contrasted, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low reverse leakage current.
3. better switching characteristic
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, utilize correlation very responsive between shape of a saddle tunneling insulation layer 7 impedance and shape of a saddle tunneling insulation layer 7 electric field intensity inside high, by choosing suitable runnel insulator material to shape of a saddle tunneling insulation layer 7, and to forming the Sidewall Height of shape of a saddle tunneling insulation layer 7, sidewall thickness, in the shape of a saddle, upper surface thickness suitably regulates, just can make the conversion that shape of a saddle tunneling insulation layer 7 realizes between high-impedance state and low resistance state in the potential change interval that folding gate electrode 8 is minimum, more outstanding switching characteristic can be realized.
4. better forward conduction characteristic
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, the insulation tunnelling current produced flows to base 4 by shape of a saddle conductive layer 6, and carry out signal enhancing through emitter region 3, with general T FETs just utilize tunnelling current between a small amount of semiconductor tape as device On current compared with, there is better forward current on state characteristic, for these reasons, in contrast to general T FETs device, embedded folding grid shape of a saddle insulation tunnelling strengthens transistor and can realize higher forward conduction electric current.
Accompanying drawing explanation
Fig. 1 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10 and barrier insulating layer 11;
Fig. 2 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4 and collector region 5;
Fig. 3 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 and shape of a saddle conductive layer 6;
Fig. 4 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5, shape of a saddle conductive layer 6 and shape of a saddle tunneling insulation layer 7;
Fig. 5 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11 and folding gate electrode 8;
Fig. 6 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 and folding gate electrode 8;
Fig. 7 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 fold three-dimensional structure schematic diagram after gate electrode 8 and shape of a saddle conductive layer 6;
Fig. 8 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens transistor and peeled off emitter 9, collector electrode 10, barrier insulating layer 11, folding gate electrode 8 and the shape of a saddle and lead three-dimensional structure schematic diagram after tunneling insulation layer 7;
Fig. 9 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 fold gate electrode 8 and the shape of a saddle leads three-dimensional structure schematic diagram after tunneling insulation layer 7;
Figure 10 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, folding gate electrode 8, the shape of a saddle lead three-dimensional structure schematic diagram after tunneling insulation layer 7 and shape of a saddle conductive layer 6;
Figure 11 is the schematic top plan view of step one,
Figure 12 be Figure 11 tangentially A cut the generalized section obtained,
Figure 13 is the schematic top plan view of step 2,
Figure 14 be Figure 13 tangentially A cut the generalized section of the step 2 obtained,
Figure 15 is the schematic top plan view of step 3,
Figure 16 be Figure 15 tangentially A cut the generalized section of the step 3 obtained,
Figure 17 is the schematic top plan view of step 4,
Figure 18 be Figure 17 tangentially A cut the generalized section of the step 4 obtained,
Figure 19 is the schematic top plan view of step 5,
Figure 20 be Figure 19 tangentially B cut the generalized section of the step 5 obtained,
Figure 21 is the schematic top plan view of step 6,
Figure 22 be Figure 21 tangentially B cut the generalized section of the step 6 obtained,
Figure 23 is the schematic top plan view of step 7,
Figure 24 be Figure 23 tangentially A cut the generalized section of the step 7 obtained,
Figure 25 be Figure 23 tangentially B cut the generalized section of the step 7 obtained,
Figure 26 is the schematic top plan view of step 8,
Figure 27 be Figure 26 tangentially A cut the generalized section of the step 8 obtained,
Figure 28 be Figure 26 tangentially B cut the generalized section of the step 8 obtained,
Figure 29 is the schematic top plan view of step 9,
Figure 30 be Figure 29 tangentially B cut the generalized section of the step 9 obtained,
Figure 31 is the schematic top plan view of step 10,
Figure 32 be Figure 31 tangentially B cut the generalized section of the step 10 obtained,
Figure 33 is the schematic top plan view of step 11,
Figure 34 be Figure 33 tangentially A cut the generalized section of the step 11 obtained,
Figure 35 be Figure 33 tangentially B cut the generalized section of the step 11 obtained,
Figure 36 is the schematic top plan view of step 12,
Figure 37 be Figure 36 tangentially A cut the generalized section of the step 12 obtained,
Figure 38 be Figure 36 tangentially B cut the generalized section of the step 12 obtained,
Figure 39 is the schematic top plan view of step 13,
Figure 40 be Figure 39 tangentially B cut the generalized section of the step 13 obtained,
Figure 41 is the schematic top plan view of step 14,
Figure 42 be Figure 41 tangentially B cut the generalized section of the step 14 obtained,
Figure 43 is the schematic top plan view of step 15,
Figure 44 be Figure 43 tangentially A cut the generalized section of the step 15 obtained,
Figure 45 be Figure 43 tangentially B cut the generalized section of the step 15 obtained,
Figure 46 is the schematic top plan view of step 10 six,
Figure 47 be Figure 46 tangentially A cut the generalized section of the step 10 six obtained,
Figure 48 be Figure 46 tangentially B cut the generalized section of the step 10 six obtained,
Figure 49 is the schematic top plan view of step 10 seven,
Figure 50 be Figure 49 tangentially B cut the generalized section of the step 10 seven obtained,
Figure 51 is the schematic top plan view of step 10 eight,
Figure 52 be Figure 51 tangentially B cut the generalized section of the step 10 eight obtained,
Figure 53 is the schematic top plan view of step 10 nine,
Figure 54 be Figure 53 tangentially B cut the generalized section of the step 10 nine obtained,
Figure 55 is the schematic top plan view of step 2 ten,
Figure 56 be Figure 55 tangentially B cut the generalized section of the step 2 ten obtained,
Figure 57 is the schematic top plan view of step 2 11,
Figure 58 be Figure 57 tangentially A cut the generalized section of the step 2 11 obtained,
Figure 59 be Figure 57 tangentially B cut the generalized section of the step 2 11 obtained.
Figure 60 is the schematic top plan view of step 2 12,
Figure 61 be Figure 60 tangentially A cut the generalized section of the step 2 12 obtained,
Figure 62 is the schematic top plan view of step 2 13,
Figure 63 be Figure 62 tangentially A cut the generalized section of the step 2 13 obtained.
Description of reference numerals:
1, monocrystalline substrate; 2, wafer insulating barrier; 3, emitter region; 4, base; 5, collector region; 6, shape of a saddle conductive layer; 7, shape of a saddle tunneling insulation layer; 8, folding gate electrode; 9, emitter; 10, collector electrode; 11, barrier insulating layer.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described further: Fig. 1 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10 and barrier insulating layer 11; Fig. 2 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4 and collector region 5; Fig. 3 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 and shape of a saddle conductive layer 6; Fig. 4 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5, shape of a saddle conductive layer 6 and shape of a saddle tunneling insulation layer 7; Fig. 5 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11 and folding gate electrode 8; Fig. 6 is the three-dimensional structure schematic diagram that the embedded folding grid shape of a saddle insulation tunnelling enhancing transistor of the present invention has peeled off after emitter 9, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 and folding gate electrode 8; Fig. 7 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 fold three-dimensional structure schematic diagram after gate electrode 8 and shape of a saddle conductive layer 6; Fig. 8 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens transistor and peeled off emitter 9, collector electrode 10, barrier insulating layer 11, folding gate electrode 8 and the shape of a saddle and lead three-dimensional structure schematic diagram after tunneling insulation layer 7; Fig. 9 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, emitter region 3, base 4, collector region 5 fold gate electrode 8 and the shape of a saddle leads three-dimensional structure schematic diagram after tunneling insulation layer 7; Figure 10 is that the present invention's embedded folding grid shape of a saddle insulation tunnelling strengthens that emitter 9 peeled off by transistor, collector electrode 10, barrier insulating layer 11, folding gate electrode 8, the shape of a saddle lead three-dimensional structure schematic diagram after tunneling insulation layer 7 and shape of a saddle conductive layer 6;
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, it is characterized in that: adopt the SOI wafer comprising monocrystalline substrate 1 and wafer insulating barrier 2 as the substrate of generating device; Emitter region 3, base 4 and collector region 5 are positioned at the top of the wafer insulating barrier 2 of SOI wafer, and base 4 has groove type structure; Between emitter region 3 and collector region 5; Emitter 9 is positioned at the top of emitter region 3; Collector electrode 10 is positioned at the top of collector region 5; Shape of a saddle conductive layer 6 is attached to upper surface and the both sides sidewall of base 4 groove inner wall and bottom portion of groove mid portion, has saddle-shaped configuration; Shape of a saddle tunneling insulation layer 7 is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle conductive layer 6 shape of a saddle inwall and the shape of a saddle, has saddle-shaped configuration; Folding gate electrode 8 is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle tunneling insulation layer 7 shape of a saddle inwall and the shape of a saddle; Barrier insulating layer 11 is dielectric.
For reaching device function of the present invention, the present invention proposes a kind of embedded folding grid shape of a saddle insulation tunnelling and strengthens transistor, and its core texture is characterized as:
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 are embedded in base 4 groove, and the upper surface of shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 is not higher than groove two ends, base 4 dome top surface;
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 constitute the tunnelling base stage that embedded folding grid shape of a saddle insulation tunnelling strengthens transistor jointly, when there is tunnelling in shape of a saddle tunneling insulation layer 7 under the control of folding gate electrode 8, electric current flow to shape of a saddle conductive layer 6 from folding gate electrode 8 through shape of a saddle tunneling insulation layer 7, and powers for base 4.
Shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 and folding gate electrode 8 are all mutually isolated with emitter region 3, emitter 9, collector region 5 and collector electrode 10 by barrier insulating layer 11; Isolated by barrier insulating layer 11 between adjacent emitter region 3 and collector region 5, isolated by barrier insulating layer 11 between adjacent emitter 9 and collector electrode 10.
Shape of a saddle conductive layer 6 and base 4 form ohmic contact, and shape of a saddle conductive layer 6 is metal materials, or with base 4 have identical dopant type and doping content is greater than 10
19the semi-conducting material of every cubic centimetre.
Shape of a saddle tunneling insulation layer 7 is the insulation material layer for generation of tunnelling current.
Between emitter region 3 and base 4, between collector region 5 and base 4, there is opposite impurity type, and form ohmic contact between emitter region 3 and emitter 9, between collector region 5 and collector electrode 10, form ohmic contact.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, for N-type, emitter region 3, base 4 and collector region 5 are respectively N district, P district and N district, its concrete operation principle is: when collector electrode 10 positively biased, and folding gate electrode 8 is when being in electronegative potential, fold and do not form enough electrical potential differences between gate electrode 8 and shape of a saddle conductive layer 6, now shape of a saddle tunneling insulation layer 7 is in high-impedance state, similar to the gate insulator of MOSFET, obvious tunnelling current is not had to pass through, therefore make between base 4 and emitter region 3, to form enough large base electric current and strengthen transistor to drive embedded folding grid shape of a saddle insulation tunnelling, namely device is in off state, along with the rising gradually of folding gate electrode 8 voltage, folding electrical potential difference between gate electrode 8 and shape of a saddle conductive layer 6 increases gradually, electric field strength in shape of a saddle tunneling insulation layer 7 between folding gate electrode 8 and shape of a saddle conductive layer 6 is also increased thereupon gradually, when the electric field strength in shape of a saddle tunneling insulation layer 7 is positioned at below critical value, shape of a saddle tunneling insulation layer 7 remains good high-impedance state, folding electrical potential difference between gate electrode 8 and emitter 9 is almost fallen completely between the inner and outer wall both sides of shape of a saddle tunneling insulation layer 7, also just make the electrical potential difference between base 4 and emitter region 3 minimum, therefore base does not almost have electric current to flow through, therefore device also keeps good off state, and when the electric field strength in shape of a saddle tunneling insulation layer 7 reaches and exceedes critical value, the folding tunnelling that charge carrier can be occurred by shape of a saddle tunneling insulation layer 7 between gate electrode 8 and shape of a saddle conductive layer 6, shape of a saddle tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current can along with the increase precipitous rising at a terrific speed of folding gate electrode 8 electromotive force, this just makes shape of a saddle tunneling insulation layer 7 be converted to low resistance state rapidly by high-impedance state in the potential change interval that folding gate electrode 8 is extremely short, when shape of a saddle tunneling insulation layer 7 is in low resistance state, the resistance that now shape of a saddle tunneling insulation layer 7 is formed between folding gate electrode 8 and shape of a saddle conductive layer 6 will much smaller than the resistance formed between shape of a saddle conductive layer 6 and emitter 3, this just makes the electrical potential difference between folding gate electrode 8 and emitter 9 almost drop to completely between base 4 and emitter region 3, define enough large positive bias-voltage, and under the effect of tunneling effect, between the inner and outer wall of shape of a saddle tunneling insulation layer 7, produce a large amount of electronics move, for base 4 provides current source, base 4 electric current is flowed out by collector electrode after emitter region 3 strengthens, now device is in opening.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, in contrast to MOSFETs or TFETs device, the effect of emitter 9 and source electrode is suitable, the effect of collector electrode 10 and drain electrode is suitable, due to folding gate electrode 8, shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are all embedded in the inside of the groove that base 4 is formed, folding gate electrode 8, the embedded folding grid shape of a saddle insulation tunnelling that shape of a saddle tunneling insulation layer 7 and shape of a saddle conductive layer 6 are formed jointly strengthens the tunnelling base stage of transistor and does not have between emitter 9 and collector electrode 10 to form the parallel capacitance structure be similar between MOSFETs or TFETs device gate electrode and drain electrode or between gate electrode and source electrode, avoiding problems the grid source caused because the distance between gate electrode and drain electrode or between gate electrode and source electrode constantly reduces as MOSFETs or TFETs, source grid, the obvious increase of parasitic capacitance between grid leak and drain-gate, namely MOSFETs or TFETs device is contrasted, under same dimension process, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low parasitic capacitance.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, owing to being embedded in the overlapping region between gate electrode and drain electrode or between gate electrode and source electrode do not existed between folding gate electrode 8 in base 4 groove and emitter region 3 or collector region 5 as MOSFETs or TFETs, potential change away from the folding gate electrode 8 of emitter region 3 or collector region 5 can not produce enough strong field effect to emitter region 3 or collector region 5, also the interband tunnelling current effect that emitter region 3 or collector region 5 are caused owing to there is strong band curvature would not be caused, therefore MOSFETs or TFETs device is contrasted, embedded folding grid shape of a saddle insulation tunnelling strengthens the advantage that transistor has low reverse leakage current.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, utilize correlation very responsive between shape of a saddle tunneling insulation layer 7 impedance and shape of a saddle tunneling insulation layer 7 electric field intensity inside high, by choosing suitable runnel insulator material to shape of a saddle tunneling insulation layer 7, and to forming the Sidewall Height of shape of a saddle tunneling insulation layer 7, sidewall thickness, in the shape of a saddle, upper surface thickness suitably regulates, just can make the conversion that shape of a saddle tunneling insulation layer 7 realizes between high-impedance state and low resistance state in the potential change interval that folding gate electrode 8 is minimum, more outstanding switching characteristic can be realized.
Embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, the insulation tunnelling current produced flows to base 4 by shape of a saddle conductive layer 6, and carry out signal enhancing through emitter region 3, with general T FETs just utilize tunnelling current between a small amount of semiconductor tape as device On current compared with, there is better forward current on state characteristic, for these reasons, in contrast to general T FETs device, embedded folding grid shape of a saddle insulation tunnelling strengthens transistor and can realize higher forward conduction electric current.
Unit and the concrete manufacturing technology steps of array in SOI wafer thereof of embedded folding grid shape of a saddle insulation tunnelling enhancing transistor proposed by the invention are as follows:
Step one, as shown in Figure 11 to 12, provide a SOI wafer, the below of SOI wafer is the monocrystalline substrate 1 of SOI wafer, the centre of SOI wafer is wafer insulating barrier 2, by ion implantation or diffusion technology, the monocrystalline silicon thin film above SOI wafer is adulterated, begin to take shape base 4.
Step 2, as shown in Figure 13 to 14, again by ion implantation or diffusion technology, the monocrystalline silicon thin film above SOI wafer to be adulterated, form contrary with the dopant type in step one, concentration at wafer upper surface and be not less than 10
19the heavily doped region of every cubic centimetre.
Step 3, as shown in Figure 15 to 16, in provided SOI wafer, form the queue of rectangular-shaped monocrystalline silicon isolated island by photoetching, etching technics.
Step 4, as shown in Figure 17 to 18, above wafer, after deposit dielectric, planarized surface, to exposing monocrystalline silicon thin film, begins to take shape barrier insulating layer 11.
Step 5, as shown in Figure 19 to 20, in provided SOI wafer, form rectangular-shaped monocrystalline silicon isolated island array further by photoetching, etching technics.
Step 6, as shown in Figure 21 to 22, above wafer, after deposit dielectric, planarized surface, to exposing emitter region 3, base 4 and collector region 5, further forms barrier insulating layer 11.
Step 7, as shown in Figure 23 to 25, by etching technics, etch groove at the mid portion of base 4.
Step 8, as shown in Figure 26 to 28, depositing metal or there is the heavily doped polysilicon of dopant type identical with base 4 above wafer, the groove that the mid portion of the base 4 be etched away in step 7 is formed is filled completely, planarized surface, to the two ends of exposing the contiguous emitter region 3 in emitter region 3, collector region 4, barrier insulating layer 11 and base 4, collector region 5, begins to take shape shape of a saddle conductive layer 6.
Step 9, as shown in Figure 29 to 30, by etching technics, the barrier insulating layer 11 of both sides, crystal column surface base mid portion is etched to and exposes wafer insulating barrier 2.
Step 10, as shown in Figure 31 to 32, depositing metal or there is the heavily doped polysilicon of dopant type identical with base 4 above wafer, the part that in step 9, barrier insulating layer 11 is etched away is completely filled, the part beyond for the formation of shape of a saddle conductive layer 6 is etched away by etching technics again after planarized surface, expose the two ends of the contiguous emitter region 3 in emitter region 3, collector region 5, barrier insulating layer 11 and base 4, collector region 5, form shape of a saddle conductive layer 6 further.
Step 11, as shown in Figure 33 to 35, by etching technics, partial etching is carried out to the mid portion of the shape of a saddle conductive layer 6 formed in step 10, form shape of a saddle conductive layer 6 further.
Step 12, as shown in Figure 36 to 38, deposit tunnelling dielectric above wafer, make shape of a saddle conductive layer 6 in step 11 be etched away part to be filled completely, the part beyond for the formation of shape of a saddle tunneling insulation layer 7 is etched away by etching technics again after planarized surface, expose emitter region 3, collector region 5, barrier insulating layer 11, contiguous emitter region 3, base 4, the two ends of collector region 5 and the top of shape of a saddle conductive layer 6, begin to take shape shape of a saddle tunneling insulation layer 7.
Step 13, as shown in Figure 39 to 40, in the side away from base of shape of a saddle conductive layer 6 being positioned at both sides, base, barrier insulating layer 11 is etched to respectively and exposes wafer insulating barrier 2.
Step 14, as shown in Figure 41 to 42, deposit tunneling insulation layer medium above wafer, the barrier insulating layer 11 be etched away in step 13 is filled completely, etched away by etching technics again after planarized surface and to exposing emitter region 3, collector region 5, barrier insulating layer 11, contiguous emitter region 3, base 4, the two ends of collector region 5 and the top of shape of a saddle conductive layer 6, form shape of a saddle tunneling insulation layer 7 for generating part beyond shape of a saddle tunneling insulation layer 7 further.
Step 15, as shown in Figure 43 to 45, by etching technics, partial etching is carried out to the mid portion of the shape of a saddle tunneling insulation layer 7 formed in step 10, form shape of a saddle tunneling insulation layer 7 further.
Step 10 six, as shown in Figure 46 to 48, depositing metal or heavily doped polysilicon above wafer, make shape of a saddle tunneling insulation layer 7 in step 15 be etched away part to be filled completely, planarized surface, to the top of exposing emitter region 3, collector region 5, barrier insulating layer 11, contiguous emitter region 3, base 4, the two ends of collector region 5, the top of shape of a saddle conductive layer 6 and shape of a saddle tunneling insulation layer 7, begins to take shape folding gate electrode 8;
Step 10 seven, as shown in Figure 49 to 50, in the side away from base of shape of a saddle tunneling insulation layer 7 being positioned at both sides, base, barrier insulating layer 11 is etched to respectively and exposes wafer insulating barrier 2.
Step 10 eight, as shown in Figure 51 to 52, deposit depositing metal or heavily doped polysilicon above wafer, the barrier insulating layer 11 be etched away in step 10 seven is filled completely, to etch away for part beyond generating folding stacked gate electrode 8 to the top of exposing emitter region 3, collector region 5, barrier insulating layer 11, contiguous emitter region 3, base 4, the two ends of collector region 5, the top of shape of a saddle conductive layer 6 and shape of a saddle tunneling insulation layer 7 by etching technics again after planarized surface, form folding gate electrode 8 further.
Step 10 nine, as shown in Figure 53 to 54, in the side away from base of the folding gate electrode 8 being positioned at both sides, base, partial etching is carried out to barrier insulating layer 11 respectively.
Step 2 ten, as shown in Figure 55 to 56, deposit depositing metal or heavily doped polysilicon above wafer, the barrier insulating layer 11 be etched away in step 10 nine is filled completely, to etch away for part beyond generating folding stacked gate electrode 8 to the top of exposing emitter region 3, collector region 5, barrier insulating layer 11, contiguous emitter region 3, base 4, the two ends of collector region 5, the top of shape of a saddle conductive layer 6 and shape of a saddle tunneling insulation layer 7 by etching technics again after planarized surface, form folding gate electrode 8 further for the cabling between interface unit unit.
Step 2 11, as shown in Figure 57 to 59, deposit dielectric above wafer, further forms barrier insulating layer 11.
Step 2 12, as shown in Figure 60 to 61, etched away the barrier insulating layer 11 of the top being positioned at emitter region 3 and collector region 5 by etching technics, form the through hole of emitter 9 and collector electrode 10.
Step 2 13, as shown in Figure 62 to 63, depositing metal above wafer, makes the through hole of the emitter 9 and collector electrode 10 formed in step 10 six be completely filled, and forms emitter 9 and collector electrode 10 by etching technics.
Claims (8)
1. embedded folding grid shape of a saddle insulation tunnelling strengthens transistor, it is characterized in that: adopt the SOI wafer comprising monocrystalline substrate (1) and wafer insulating barrier (2) as the substrate of generating device; Emitter region (3), base (4) and collector region (5) are positioned at the top of the wafer insulating barrier (2) of SOI wafer; Base (4) has groove type structure, is positioned between emitter region (3) and collector region (5); Emitter (9) is positioned at the top of emitter region (3); Collector electrode (10) is positioned at the top of collector region (5); Shape of a saddle conductive layer (6) is attached to upper surface and the both sides sidewall of base (4) groove inner wall and bottom portion of groove mid portion, has saddle-shaped configuration; Shape of a saddle tunneling insulation layer (7) is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle conductive layer (6) shape of a saddle inwall and the shape of a saddle, has saddle-shaped configuration; Folding gate electrode (8) is attached to upper surface and the both sides sidewall of mid portion bottom shape of a saddle tunneling insulation layer (7) shape of a saddle inwall and the shape of a saddle; Barrier insulating layer (11) is dielectric.
2. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: shape of a saddle conductive layer (6), shape of a saddle tunneling insulation layer (7) and folding gate electrode (8) are embedded in base (4) groove, the upper surface of shape of a saddle conductive layer (6), shape of a saddle tunneling insulation layer (7) and folding gate electrode (8) is not higher than base (4) groove two ends dome top surface.
3. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: shape of a saddle conductive layer (6), shape of a saddle tunneling insulation layer (7) and folding gate electrode (8) constitute the tunnelling base stage that embedded folding grid shape of a saddle insulation tunnelling strengthens transistor jointly, when there is tunnelling in shape of a saddle tunneling insulation layer (7) under the control of folding gate electrode (8), electric current flow to shape of a saddle conductive layer (6) from folding gate electrode (8) through shape of a saddle tunneling insulation layer (7), and is base (4) power supply.
4. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: shape of a saddle conductive layer (6), shape of a saddle tunneling insulation layer (7) and folding gate electrode (8) are all mutually isolated with emitter region (3), emitter (9), collector region (5) and collector electrode (10) by barrier insulating layer (11); Isolated by barrier insulating layer (11) between adjacent emitter region (3) and collector region (5), isolated by barrier insulating layer (11) between adjacent emitter (9) and collector electrode (10).
5. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: shape of a saddle conductive layer (6) and base (4) form ohmic contact, shape of a saddle conductive layer (6) is metal material or same base (4) have identical dopant type and doping content is greater than 10
19the semi-conducting material of every cubic centimetre.
6. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: shape of a saddle tunneling insulation layer (7) is the insulation material layer for generation of tunnelling current.
7. embedded folding grid shape of a saddle insulation tunnelling according to claim 1 strengthens transistor, it is characterized in that: between emitter region (3) and base (4), between collector region (5) and base (4), there is opposite impurity type, and form ohmic contact between emitter region (3) and emitter (9), form ohmic contact between collector region (5) and collector electrode (10).
8. embedded folding grid shape of a saddle insulation tunnelling as claimed in claim 1 strengthens the unit of transistor and a manufacture method for array thereof, it is characterized in that: this processing step is as follows:
Step one, provide a SOI wafer, the below of SOI wafer is the monocrystalline substrate (1) of SOI wafer, the centre of SOI wafer is wafer insulating barrier (2), by ion implantation or diffusion technology, monocrystalline silicon thin film above SOI wafer is adulterated, begins to take shape base (4);
Step 2, again by ion implantation or diffusion technology, the monocrystalline silicon thin film above SOI wafer to be adulterated, form contrary with the dopant type in step one, concentration at wafer upper surface and be not less than 10
19the heavily doped region of every cubic centimetre;
Step 3, in provided SOI wafer, form the queue of rectangular-shaped monocrystalline silicon isolated island by photoetching, etching technics;
Step 4, above wafer, after deposit dielectric, planarized surface, to exposing monocrystalline silicon thin film, begins to take shape barrier insulating layer (11);
Step 5, in provided SOI wafer, form rectangular-shaped monocrystalline silicon isolated island array further by photoetching, etching technics;
Step 6, above wafer, after deposit dielectric, planarized surface, to exposing emitter region (3), base (4) and collector region (5), forms barrier insulating layer (11) further;
Step 7, by etching technics, etch groove at the mid portion of base (4);
Step 8, above wafer depositing metal or there is the heavily doped polysilicon with base (4) identical dopant type, the groove that the mid portion of the base (4) be etched away in step 7 is formed is filled completely, planarized surface, to the two ends of exposing emitter region (3), collector region (4), the contiguous emitter region (3) in barrier insulating layer (11) and base (4), collector region (5), begins to take shape shape of a saddle conductive layer (6);
Step 9, by etching technics, the barrier insulating layer (11) of both sides, crystal column surface base mid portion is etched to and exposes wafer insulating barrier (2);
Step 10, above wafer depositing metal or there is the heavily doped polysilicon with base (4) identical dopant type, the part that barrier insulating layer in step 9 (11) is etched away is completely filled, the part beyond for the formation of shape of a saddle conductive layer (6) is etched away by etching technics again after planarized surface, expose the two ends of emitter region (3), collector region (5), the contiguous emitter region (3) in barrier insulating layer (11) and base (4), collector region (5), form shape of a saddle conductive layer (6) further;
Step 11, by etching technics, partial etching is carried out to the mid portion of the shape of a saddle conductive layer (6) formed in step 10, form shape of a saddle conductive layer (6) further;
Step 12, above wafer deposit tunnelling dielectric, make shape of a saddle conductive layer (6) in step 11 be etched away part to be filled completely, the part beyond for the formation of shape of a saddle tunneling insulation layer (7) is etched away by etching technics again after planarized surface, expose emitter region (3), collector region (5), barrier insulating layer (11), base (4) contiguous emitter region (3), the two ends of collector region (5) and the top of shape of a saddle conductive layer (6), begin to take shape shape of a saddle tunneling insulation layer (7);
Step 13, in the side away from base of shape of a saddle conductive layer (6) being positioned at both sides, base, barrier insulating layer (11) is etched to and exposes wafer insulating barrier (2) respectively;
Step 14, above wafer deposit tunneling insulation layer medium, the barrier insulating layer (11) be etched away in step 13 is filled completely, etched away by etching technics again after planarized surface and to exposing emitter region (3), collector region (5), barrier insulating layer (11), base (4) contiguous emitter region (3), the two ends of collector region (5) and the top of shape of a saddle conductive layer (6), form shape of a saddle tunneling insulation layer (7) for generating part beyond shape of a saddle tunneling insulation layer (7) further;
Step 15, by etching technics, partial etching is carried out to the mid portion of the shape of a saddle tunneling insulation layer (7) formed in step 10, form shape of a saddle tunneling insulation layer (7) further;
Step 10 six, above wafer depositing metal or heavily doped polysilicon, make shape of a saddle tunneling insulation layer (7) in step 15 be etched away part to be filled completely, planarized surface, to the top of exposing emitter region (3), collector region (5), barrier insulating layer (11), base (4) contiguous emitter region (3), the two ends of collector region (5), the top of shape of a saddle conductive layer (6) and shape of a saddle tunneling insulation layer (7), begins to take shape folding gate electrode (8);
Step 10 seven, in the side away from base of shape of a saddle tunneling insulation layer (7) being positioned at both sides, base, barrier insulating layer (11) is etched to and exposes wafer insulating barrier (2) respectively;
Step 10 eight, deposit depositing metal or heavily doped polysilicon above wafer, the barrier insulating layer (11) be etched away in step 10 seven is filled completely, etched away for part beyond generating folding stacked gate electrode (8) to exposing emitter region (3) by etching technics again after planarized surface, collector region (5), barrier insulating layer (11), the contiguous emitter region (3) in base (4), the two ends of collector region (5), the top of shape of a saddle conductive layer (6) and the top of shape of a saddle tunneling insulation layer (7), further formation folds gate electrode (8),
Step 10 nine, in the side away from base of the folding gate electrode (8) being positioned at both sides, base, partial etching is carried out to barrier insulating layer (11) respectively;
Step 2 ten, deposit depositing metal or heavily doped polysilicon above wafer, the barrier insulating layer (11) be etched away in step 10 nine is filled completely, etched away for part beyond generating folding stacked gate electrode (8) to exposing emitter region (3) by etching technics again after planarized surface, collector region (5), barrier insulating layer (11), the contiguous emitter region (3) in base (4), the two ends of collector region (5), the top of shape of a saddle conductive layer (6) and the top of shape of a saddle tunneling insulation layer (7), further formation folds gate electrode (8) for the cabling between interface unit unit,
Step 2 11, above wafer deposit dielectric, form barrier insulating layer (11) further;
Step 2 12, etched away the barrier insulating layer (11) of the top being positioned at emitter region (3) and collector region (5) by etching technics, form the through hole of emitter (9) and collector electrode (10);
Step 2 13, above wafer depositing metal, the through hole of emitter (9) and the collector electrode (10) formed in step 10 six is completely filled, and forms emitter (9) and collector electrode (10) by etching technics.
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| CN1606170A (en) * | 2004-09-24 | 2005-04-13 | 中国科学院物理研究所 | Transistor based on double barrier tunnel junction resonant tunneling effect |
| US20060046388A1 (en) * | 2004-08-27 | 2006-03-02 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor device and method of fabricating the same |
| US20120267700A1 (en) * | 2011-04-20 | 2012-10-25 | Peking University | Tunneling current amplification transistor |
| US20130149824A1 (en) * | 2011-12-12 | 2013-06-13 | Fudan University | Method for manufacturing a tunneling field effect transistor with a u-shaped channel |
| CN103730357A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | NPN transistor and forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060046388A1 (en) * | 2004-08-27 | 2006-03-02 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor device and method of fabricating the same |
| CN1606170A (en) * | 2004-09-24 | 2005-04-13 | 中国科学院物理研究所 | Transistor based on double barrier tunnel junction resonant tunneling effect |
| US20120267700A1 (en) * | 2011-04-20 | 2012-10-25 | Peking University | Tunneling current amplification transistor |
| US20130149824A1 (en) * | 2011-12-12 | 2013-06-13 | Fudan University | Method for manufacturing a tunneling field effect transistor with a u-shaped channel |
| CN103730357A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | NPN transistor and forming method |
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