CN104465499A - Method for improving electromigration character - Google Patents
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- CN104465499A CN104465499A CN201410692972.1A CN201410692972A CN104465499A CN 104465499 A CN104465499 A CN 104465499A CN 201410692972 A CN201410692972 A CN 201410692972A CN 104465499 A CN104465499 A CN 104465499A
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Abstract
The invention provides a method for improving the electromigration character, and belongs to the technical field of semiconductor manufacturing. The method specifically comprises the steps that firstly, a dielectric barrier layer, a dielectric layer and a hard mask layer are formed on a copper wire from bottom to top in sequence; secondly, a seed layer with a groove structure is formed with the hard mask layer as the basis in an etching mode and is doped with metal elements; thirdly, the hard mask layer is removed through the chemical-mechanical polishing method; fourthly, oxidization annealing is carried out on the seed layer through the oxidization gas; fifthly, diffusivity annealing is carried out on the seed layer through the inert gas; sixthly, reductibility annealing is carried out on the seed layer through the reductibility gas; seventhly, a dielectric barrier layer is additionally arranged on the seed layer. By means of the technical scheme, the method has the advantages that alloying elements in the seed layer are diffused to the upper surface of the copper wire, the electromigration character is improved, the resistance of the copper wire is reduced, the structure manufacturing technology is simple, it is not needed to add too many technology steps, and the manufacturing cost is low.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method improving electromigration characteristic.
Background technology
The ELECTROMIGRATION PHENOMENON produced in semiconductor fabrication mainly refers to that conductive ion motion causes the phenomenon of element or circuit malfunction under the effect of electric field, namely when devices function, certain electric current is had to pass through in metal interconnecting wires, metal ion can produce transporting of quality along conductor, its result can make some position of conductor produce cavity or whisker (hillock), specifically comprise occur in adjacent conductor surface as common silver ion migration and the metallization electron transfer occurring in metallic conductor inside.ELECTROMIGRATION PHENOMENON easily causes component failure, such as, cause the parameter degradation etc. of shorted devices, open circuit or device.
In prior art, in 45/40nm and 32/28nm manufacturing process, generally adopt the method for copper alloy Seed Layer to improve ELECTROMIGRATION PHENOMENON, the advantage of this method is that manufacture craft is simple, without the need to increasing extra processing step, and whole technological process is not affected.But adopt the method for copper alloy Seed Layer to improve ELECTROMIGRATION PHENOMENON, due to adding of wherein alloying element, thus the reallocation of alloying element in copper conductor can be affected, cause the resistance of whole copper conductor to increase.
Chinese patent (CN1438362) discloses a kind of Ni―Ti anode with meticulous Seed Layer being applicable to electrochemical industry; seed deposition is on titanium base material; seed is noble metal or the precious metal chemical complex with nanoscale, Seed Layer can be the protective layer containing precious metal element or activation top layer.At least containing Seed Layer between titanium basic unit and active coating.According to the result of study improving electrode material activity, the activity of electrode material is relevant with the activated centre on surface, and under a certain amount of active material condition, activated centre density is higher, then electrode activity is higher.Technique scheme does not relate to the infiltration element how processed in Seed Layer, therefore cannot solve problems of the prior art.
Chinese patent (CN101911264A) discloses a kind of electronic component, be hold concurrently the electronic component of alloy firm of tungsten that Seed Layer uses and noble metal in the barrier layer be formed on base material as the fine copper wiring of ULSI, the composition of this alloy firm is tungsten is 60 more than atom %, noble metal is 5 atom % ~ 40 atom %.As described noble metal, be preferably selected from the one kind or two or more metal in platinum, gold, silver, palladium.Technique scheme only discloses barrier layer and to hold concurrently the part of electronic component that Seed Layer uses, and can not solve problems of the prior art.
Summary of the invention
In view of the above problems, the invention provides a kind of method improving electromigration characteristic
The technical scheme that technical solution problem of the present invention adopts is:
Improve a method for electromigration characteristic, be applicable to make in the copper wiring technique of copper conductor, wherein, specifically comprise:
Step 1, described copper conductor forms dielectric barrier layer, dielectric layer and hard mask layer from bottom to top successively;
Step 2, etches the Seed Layer that formation one has groove structure, doped with metallic element in described Seed Layer based on described hard mask layer;
Step 3, removes described hard mask layer by chemico-mechanical polishing;
Step 4, adopts oxidizing gas to carry out oxidizability annealing in process to described Seed Layer;
Step 5, adopts inert gas to carry out diffusivity annealing in process to described Seed Layer;
Step 6, adopts reducibility gas to carry out reproducibility annealing in process to described Seed Layer;
Step 7, described Seed Layer adds one deck dielectric barrier layer.
Preferably, the method for this improvement electromigration characteristic, wherein, described Seed Layer is copper alloy Seed Layer.
Preferably, the method for this improvement electromigration characteristic, wherein, described step 2 comprises further:
Step 21, forms a groove structure by chemical etching;
Step 22, by physical gas-phase deposition, described groove structure forms a barrier layer;
Step 23, forms described Seed Layer by physical gas-phase deposition on described barrier layer;
Step 24, carries out electro-coppering to described Seed Layer.
Preferably, the method for this improvement electromigration characteristic, wherein, in described step 5, carries out plasma treatment to described Seed Layer simultaneously.
Preferably, the method for this improvement electromigration characteristic, wherein, the annealing in process temperature of described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process is not all higher than 400 DEG C.
Preferably, the method for this improvement electromigration characteristic, wherein, the treatment temperature of described plasma treatment is identical with room temperature.
Preferably, the method for this improvement electromigration characteristic, is characterized in that, in described step 6, after completing described reproducibility annealing in process, returns described step 4; Until driven when being greater than a default value to the described metallic element of the upper surface of described copper conductor and the ratio of all described metallic elements, go to described step 7.
Preferably, the method for this improvement electromigration characteristic, is characterized in that, described default value is 50%.
Preferably, the method for this improvement electromigration characteristic, wherein, completes described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process in same semiconductor equipment;
Described semiconductor equipment comprises multiple first reaction chamber, and described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process are carried out respectively in described first reaction chamber of correspondence.
Preferably, the method for this improvement electromigration characteristic, wherein, completes described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process in same semiconductor equipment;
Described semiconductor equipment comprises one second reaction chamber, is provided with an air transporting arrangement in described second reaction chamber, and the gas switching device shifter be connected with described air transporting arrangement:
When carrying out described oxidizability annealing in process, described air transporting arrangement is switched to the operating state of carrying oxidizing gas in described second reaction chamber by described gas switching device shifter;
When carrying out described diffusivity annealing in process, described air transporting arrangement is switched to the operating state of carrying inert gas in described second reaction chamber by described gas switching device shifter;
When carrying out described reproducibility annealing in process, described air transporting arrangement is switched to the operating state of carrying reducibility gas in described second reaction chamber by described gas switching device shifter.
Technique scheme tool has the following advantages or beneficial effect:
Can by the upper surface of the diffusion of alloy elements in Seed Layer to copper conductor by method of the present invention, thus improve electromigratory characteristic, significantly reduce the resistance of copper conductor itself, total manufacture craft is simple, without the need to increasing processing step extra too much, cost of manufacture is lower.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is in preferred embodiment of the present invention, a kind of schematic flow sheet improving the method for electromigration characteristic;
Fig. 2-3 is in preferred embodiment of the present invention, the copper interconnection structure that a kind of method that application improves electromigration characteristic makes;
Fig. 4 is in preferred embodiment of the present invention, based on the basis of Fig. 1 to the schematic flow sheet that its groove sections processes.
Embodiment
The invention provides a kind of method that TEM sample is prepared again, can be applicable to technology node is in the technique of 45/40nm and 32/28nm.
The method improving electromigration characteristic of the present invention is mainly applicable to adopt copper alloy Seed Layer to improve the situation of copper conductor electromigration characteristic.
Core concept of the present invention is the content on purpose being increased oxygen element by the upper surface at copper conductor, think the driving-energy of alloying element in Seed Layer, abundant driving diffusion of alloy elements to the upper surface of copper conductor, thus reaches the object reducing copper conductor resistance.
Below in conjunction with accompanying drawing, the inventive method is described in detail.
In preferred embodiment of the present invention, a kind of method improving electromigration characteristic, its step as shown in Figure 1, specifically comprises:
Step 1, copper conductor forms dielectric barrier layer, dielectric layer and hard mask layer from bottom to top successively;
In preferred embodiment of the present invention, as Figure 2-3, first deposit one deck dielectric barrier layer 1 (Dielectric Barrier, DB), on dielectric barrier layer 1, form a dielectric layer 2 subsequently.In preferred embodiment of the present invention, this dielectric layer 2 is ultralow dielectric coefficient layer (UltraLow K, ULK).In preferred embodiment of the present invention, dielectric layer 2 forms one deck hard mask layer again, due at follow-up CMP (Chemical Mechanical Polishing) process (Chemical MechanicalPolishing, CMP) in, hard mask layer is removed, and therefore in final structure chart (as Figure 2-3), does not show above-mentioned hard mask layer.
Step 2, etches the Seed Layer that formation one has groove structure, doped with metallic element in Seed Layer based on hard mask layer;
In preferred embodiment of the present invention, be specially: according to above-mentioned hard mask layer etching formation one groove structure, and above groove structure, form Seed Layer 4.Further, in preferred embodiment of the present invention, above-mentioned Seed Layer 4 is copper alloy Seed Layer.
Form the above-mentioned idiographic flow with the Seed Layer 4 of groove structure can describe in detail hereinafter.
Step 3, removes hard mask layer by chemico-mechanical polishing;
In preferred embodiment of the present invention, after formation Seed Layer 4, by CMP (Chemical Mechanical Polishing) process (Chemical Mechanical Polishing, CMP), hard mask layer is removed.
Step 4, adopts oxidizing gas to carry out oxidizability annealing in process to Seed Layer;
In preferred embodiment of the present invention, as described in above-mentioned steps 2, barrier layer 3 forms a Seed Layer 4, be a copper alloy Seed Layer further, but doped with many metallic elements 4 in this Seed Layer 4, the reallocation of metallic element in copper conductor can be affected, thus increase the resistance of copper conductor.
And find through research, by increasing certain oxygen element content on copper conductor surface, metallic element 5 wherein can be driven to move (as shown in Figure 3) to the upper surface of copper conductor, and metallic element 5 is all driven to the upper surface of copper conductor the most at last, thus the Resistance Influence of metallic element 5 pairs of copper conductors is made to drop to minimum.
Further, in preferred embodiment of the present invention, oxygen can be adopted to realize above-mentioned oxidizability annealing in process, or adopt other oxidizing gas to realize above-mentioned oxidizability annealing in process.
Further, in preferred embodiment of the present invention, the annealing in process temperature of above-mentioned oxidizability annealing in process is not higher than 400 DEG C.
In preferred embodiment of the present invention, in above-mentioned steps 4, except carrying out except oxidizability annealing in process to Seed Layer 4, plasma treatment can also be carried out to it.Further, in preferred embodiment of the present invention, the temperature of plasma treatment is preferably room temperature, thus can reduce heat budget (thermal budget).
Step 5, adopts inert gas to carry out diffusivity annealing in process to Seed Layer;
In preferred embodiment of the present invention, carry out to Seed Layer 4 distribution uniformity that diffusivity annealing in process can make metallic element 5 wherein, the dendritic segregation that elimination Seed Layer 4 produces in process of setting and regional segregation, make composition and microstructure homogenization.
Further, in preferred embodiment of the present invention, nitrogen or other inert gases can be adopted to realize above-mentioned diffusivity annealing in process.
Further, in preferred embodiment of the present invention, the annealing in process temperature of above-mentioned diffusivity annealing in process is no more than 400 DEG C.
Step 6, adopts reducibility gas to carry out reproducibility annealing in process to Seed Layer;
In preferred embodiment of the present invention, due to copper conductor, this self does not have the ability of metal passivation under the state of oxidation, therefore needs to carry out reproducibility annealing in process to copper conductor, to prevent the excessive oxidation of copper conductor.
Further, in preferred embodiment of the present invention, hydrogen or other reducibility gas can be adopted to realize above-mentioned reproducibility annealing in process.
Further, in preferred embodiment of the present invention, the annealing in process temperature of above-mentioned reproducibility annealing in process is no more than 400 DEG C.
Step 7, adds one deck dielectric barrier layer on the seed layer.
In preferred embodiment of the present invention, after above-mentioned annealing in process is all carried out, namely after completing the process of Seed Layer 4, another layer of dielectric barrier layer (not shown) is adopted to cover above above-mentioned Seed Layer 4, with transad sublayer 4 and extraneous contact.
Further, in preferred embodiment of the present invention, all metallic elements 5 all might not be driven to the upper surface of copper conductor by the annealing process due to once oxidation-diffusion-reduction, therefore in above-mentioned steps 6, after completing reproducibility annealing in process, return step 4, between step 4-step 6, namely form the annealing process of a circulation.And driven to the metallic element 5 (namely as shown in Figure 3) of the upper surface of copper conductor and the ratio of all metallic elements 5 more than a default value when detect, namely more than the ratio of a default value metallic element 5 by drive to copper conductor upper surface time, go to step 7 again, namely above Seed Layer 4, cover dielectric barrier layer.
In preferred embodiment of the present invention, above-mentioned default value is 50%, namely when the metallic element 5 had more than 50% by drive to copper conductor upper surface time, go to above-mentioned steps 7.
In preferred embodiment of the present invention, above-mentioned three annealing processes, actual can being integrated in same semiconductor equipment is carried out.Multiple first reaction chamber can be provided with in this semiconductor equipment, in each first reaction chamber, correspondence carries out an annealing process, namely oxidizability annealing in process can be carried out in first the first reaction chamber, diffusivity annealing in process can be carried out in second the first reaction chamber, and reproducibility annealing in process can be carried out in the 3rd the first reaction chamber.Manufacturing cost can be saved like this.
Further, in preferred embodiment of the present invention, one second reaction chamber can also be comprised in above-mentioned semiconductor equipment, and above-mentioned three kinds of annealing processes can be carried out in same second reaction chamber.Be specially: an air transporting arrangement and a gas switching device shifter are set in this second reaction chamber.This air transporting arrangement connects a gas generator, can produce the gas (oxidizing gas, inert gas and reducibility gas) being applicable to above-mentioned three kinds of annealing processes in gas generator, the gas that air transporting arrangement is responsible for gas generator produces inputs in the second reaction chamber.And gas switching device shifter connects air transporting arrangement, for switching the operating state of air transporting arrangement, such as: when needing in the second reaction chamber to carry out oxidizability annealing in process, air transporting arrangement is switched to the operating state of introduction of oxidative gas (such as oxygen) in the second reaction chamber by gas switching device shifter; When needing in the second reaction chamber to carry out diffusivity annealing in process, air transporting arrangement is switched to the operating state inputting inert gas (such as nitrogen) in the second reaction chamber by gas switching device shifter; And when needing in the second reaction chamber to carry out reproducibility annealing in process, gas switches shape and refers to air transporting arrangement be switched to the operating state inputting reducibility gas (such as hydrogen) in the second reaction chamber.By above-mentioned improvement, three kinds of different annealing processes can be carried out in the same reaction chamber of same semiconductor equipment, greatly save manufacturing cost.
In preferred embodiment of the present invention, further, as shown in Figure 4, on the basis of Fig. 1, above-mentioned steps 2 specifically comprises:
Step 21, forms a groove structure by chemical etching;
In preferred embodiment of the present invention, based on above-mentioned hard mask layer (not shown), form above-mentioned groove structure by photoetching (litho) and etching (etch).
Step 22, forms barrier layer on the groove structure by physical gas-phase deposition;
In preferred embodiment of the present invention, owing to needing the dielectric layer 2 intercepting Seed Layer 4 and below, to prevent the metallic element 5 of Seed Layer 4 inside from leaking, therefore form one deck barrier layer 3 (Barrier) first on the groove structure, for transad sublayer 4 and dielectric layer 2.
Step 22, forms Seed Layer over the barrier layer by physical gas-phase deposition;
In preferred embodiment of the present invention, by physical gas-phase deposition (PhysicalVapor Deposition, PVD), in the groove structure such as described in step 21, form above-mentioned barrier layer 3 and Seed Layer 4 successively, namely on barrier layer 3, form a Seed Layer 4 again.
Step 23, carries out electro-coppering to Seed Layer.
In preferred embodiment of the present invention, by electro-coppering, above-mentioned Seed Layer 4 becomes a copper alloy Seed Layer.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. improve a method for electromigration characteristic, be applicable to make in the copper wiring technique of copper conductor, it is characterized in that, specifically comprise:
Step 1, described copper conductor forms dielectric barrier layer, dielectric layer and hard mask layer from bottom to top successively;
Step 2, etches the Seed Layer that formation one has groove structure, doped with metallic element in described Seed Layer based on described hard mask layer;
Step 3, removes described hard mask layer by chemico-mechanical polishing;
Step 4, adopts oxidizing gas to carry out oxidizability annealing in process to described Seed Layer;
Step 5, adopts inert gas to carry out diffusivity annealing in process to described Seed Layer;
Step 6, adopts reducibility gas to carry out reproducibility annealing in process to described Seed Layer;
Step 7, described Seed Layer adds one deck dielectric barrier layer.
2. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, described Seed Layer is copper alloy Seed Layer.
3. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, described step 2 comprises further:
Step 21, forms a groove structure by chemical etching;
Step 22, forms a barrier layer by physical gas-phase deposition on described groove structure;
Step 23, forms described Seed Layer by physical gas-phase deposition on described barrier layer;
Step 24, carries out electro-coppering to described Seed Layer.
4. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, in described step 5, plasma treatment is carried out to described Seed Layer simultaneously.
5. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, the annealing in process temperature of described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process is not all higher than 400 DEG C.
6. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, the treatment temperature of described plasma treatment is identical with room temperature.
7. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, in described step 6, after completing described reproducibility annealing in process, return described step 4; Until driven when being greater than a default value to the described metallic element of the upper surface of described copper conductor and the ratio of all described metallic elements, go to described step 7.
8. improve the method for electromigration characteristic as claimed in claim 7, it is characterized in that, described default value is 50%.
9. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, in same semiconductor equipment, complete described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process;
Described semiconductor equipment comprises multiple first reaction chamber, and described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process are carried out respectively in described first reaction chamber of correspondence.
10. improve the method for electromigration characteristic as claimed in claim 1, it is characterized in that, in same semiconductor equipment, complete described oxidizability annealing in process, described diffusivity annealing in process and described reproducibility annealing in process;
Described semiconductor equipment comprises one second reaction chamber, is provided with an air transporting arrangement in described second reaction chamber, and the gas switching device shifter be connected with described air transporting arrangement;
When carrying out described oxidizability annealing in process, described air transporting arrangement is switched to the operating state of carrying oxidizing gas in described second reaction chamber by described gas switching device shifter;
When carrying out described diffusivity annealing in process, described air transporting arrangement is switched to the operating state of carrying inert gas in described second reaction chamber by described gas switching device shifter;
When carrying out described reproducibility annealing in process, described air transporting arrangement is switched to the operating state of carrying reducibility gas in described second reaction chamber by described gas switching device shifter.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107924868A (en) * | 2015-08-12 | 2018-04-17 | 盛美半导体设备（上海）有限公司 | Processing interconnection structure makes the method for the recessed minimum of barrier layer side wall |
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| CN1457095A (en) * | 2002-05-08 | 2003-11-19 | 日本电气株式会社 | Semiconductor device with siliceous metal wiring layer and manufacturing method thereof |
| US20100044864A1 (en) * | 2008-08-22 | 2010-02-25 | Renesas Technology Corp. | Method of manufacturing semiconductor device, and semiconductor device |
| CN103839920A (en) * | 2012-11-20 | 2014-06-04 | 意法半导体公司 | Copper seed layer for an interconnect structure having a doping concentration level gradient |
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- 2014-11-26 CN CN201410692972.1A patent/CN104465499A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1457095A (en) * | 2002-05-08 | 2003-11-19 | 日本电气株式会社 | Semiconductor device with siliceous metal wiring layer and manufacturing method thereof |
| US20100044864A1 (en) * | 2008-08-22 | 2010-02-25 | Renesas Technology Corp. | Method of manufacturing semiconductor device, and semiconductor device |
| CN103839920A (en) * | 2012-11-20 | 2014-06-04 | 意法半导体公司 | Copper seed layer for an interconnect structure having a doping concentration level gradient |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107924868A (en) * | 2015-08-12 | 2018-04-17 | 盛美半导体设备（上海）有限公司 | Processing interconnection structure makes the method for the recessed minimum of barrier layer side wall |
| CN107924868B (en) * | 2015-08-12 | 2021-12-03 | 盛美半导体设备(上海)股份有限公司 | Method of fabricating interconnect structures to minimize barrier sidewall recess |
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