CN104465411B - Wafer level package method - Google Patents
Wafer level package method Download PDFInfo
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- CN104465411B CN104465411B CN201310425771.0A CN201310425771A CN104465411B CN 104465411 B CN104465411 B CN 104465411B CN 201310425771 A CN201310425771 A CN 201310425771A CN 104465411 B CN104465411 B CN 104465411B
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- wafer
- isolation layer
- level packaging
- packaging method
- pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
A wafer level package method comprises the following steps: providing a wafer and a substrate, wherein a first surface of the wafer is bonded with the substrate; forming an isolation layer on a second surface of the wafer; carrying out laser thermal annealing treatment for the isolation layer; forming electrically connected a metal interconnecting line and a pad on the isolation layer; forming a passivation layer, exposing at least certain part of the pad, on the isolation layer and the pad; forming a boss lower metal layer on the pad; forming a solder ball on the boss lower metal layer. The method uses laser thermal annealing to process the isolation layer, so the isolation layer is strong in waterproof property, hard to absorb water, hard to be peeled off or broken, thus improving isolation performance of the isolation layer.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of wafer-level packaging method.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) is one kind of chip package mode, is full wafer wafer
After the completion of production, packaging and testing is directly carried out on wafer, single chip is just cut into after completion, be not necessary to by routing
Or filler.Wafer-level packaging have the advantages that package dimension is small and encapsulation after excellent electrical properties, wafer-level packaging is also easy to and crystalline substance
Circle manufacture and chip assemble compatibility, simplify the process that wafer is fabricated onto product turnout, reduce overall production cost.
During wafer-level packaging, it usually needs with adhesive by wafer together with substrate bonding, then in wafer table
Face makes isolation layer and keeps apart with the conductive structure being subsequently formed with by crystal column surface.In order to avoid adhesive loses because of high temperature
Effect, it usually needs use low temperature oxide（Low temperature oxide, LTO）To form isolation layer.
However, the density of low temperature oxide is low, heat endurance is poor, and waterproof ability is poor, also, increases over time, low temperature
The waterproof ability of oxide may proceed to decline.Fig. 1 shows the waterproof ability of low temperature oxide and the relation of time, wherein curve
1 representative is the when m- relative water-intake rate relation measured under the conditions of 25 DEG C, and what curve 2 was represented is measured under the conditions of 100 DEG C
When m- relative water-intake rate relation, there it can be seen that the time is more long, the relative water-intake rate of low temperature oxide is bigger, i.e. the time
More long, the water absorbing capacity of low temperature oxide is stronger, and waterproof ability is poorer.Because low temperature oxide waterproof ability is poor, therefore low temperature
Oxide easily absorbs water, once and low temperature oxide absorb water, may result in its internal stress increase, cause isolation layer cracking or
Person peels off, and influences isolation layer performance, causes whole isolation layer to lose buffer action when serious.
For this reason, it may be necessary to a kind of new wafer-level packaging method, to improve the waterproof ability of isolation layer, so as to prevent isolation layer
Generation is ftractureed or is peeled off.
The content of the invention
The problem that the present invention is solved is to provide a kind of wafer-level packaging method, to improve with the waterproof ability of isolation layer, prevents
Only there is cracking or peel off in isolation layer, so as to strengthen the buffer action of isolation layer.
To solve the above problems, the present invention provides a kind of wafer-level packaging method, including：
Wafer and substrate are provided, the wafer has first surface and the second surface relative with first surface；
By the first surface of the wafer together with the substrate bonding；
Isolation layer is formed in the second surface of the wafer；
Laser thermal anneal is carried out to the isolation layer（Laser Thermal Annealing, LTA）Treatment；
Metal interconnecting wires and pad are formed on the isolation layer, the metal interconnecting wires are electrically connected with the pad；
Passivation layer, the passivation layer exposure at least partly pad are formed on the isolation layer and the pad；
Underbump metallization layer is formed on the pad；
Soldered ball is formed on Underbump metallization layer.
Optionally, the material of the isolation layer includes low temperature oxide, and the thickness range of the low temperature oxide includes
Optionally, the low temperature oxide includes silica, and the laser that the laser thermal anneal treatment is used is near purple
Outer light, the energy of the black light is 9eV.
Optionally, the process time scope to the wafer of the laser thermal anneal treatment includes 1min~2min.
Optionally, when the laser thermal anneal treatment is carried out to the isolation layer, the temperature range of the isolation layer includes
600 DEG C~900 DEG C.
Optionally, when the laser thermal anneal treatment is carried out to the isolation layer, the temperature range control of the wafer exists
Less than 200 DEG C.
Optionally, using plasma enhancing chemical vapour deposition technique forms the isolation in the second surface of the wafer
Layer.
Optionally, the first surface of the wafer makes photosensitive array unit.
Optionally, the substrate is glass substrate.
Optionally, the adhesive is organic adhesion agent.
Compared with prior art, technical scheme has advantages below：
In technical scheme, when wafer-level packaging is carried out, after crystal column surface forms isolation layer, using sharp
Light thermal annealing makes annealing treatment to the isolation layer, so as to improve the density of isolation layer, the raising of density can both prevent every
Exhausted layer is peeling-off or cracking, can improve the waterproof ability of the isolation layer again, thus by the laser thermal anneal at
The isolation layer after reason is not hygroscopic, is not susceptible to peel off or ftractures, and the isolation performance of the whole isolation layer is improved, and
And only the isolation layer can be annealed using the laser thermal anneal, other structures are not by the shadow of the laser thermal anneal
Ring, therefore structural reliability packaged by the wafer-level packaging method is high.
Brief description of the drawings
M- relative water-intake rate graph of a relation when Fig. 1 is low temperature oxide；
Fig. 2 to Fig. 6 is wafer-level packaging method embodiment schematic diagram of the present invention.
Specific embodiment
In existing wafer-level packaging method, the isolation layer density of formation is smaller, loosely organized, thus easily it is peeling-off or
Cracking, and isolation layer waterproof ability is poor, it is hygroscopic, once after water suction, the negative stress inside isolation layer further increases,
Thus it is more prone to stripping occur or ftractures, causes isolation layer easily to fail.It is existing in order to remove the moisture of isolation layer absorption
Have in method and employ prolonged low-temperature bake（baking）Technique or except moisture（degas）Technique, but use these
Technique needs to increase substantial amounts of time and cost, is unfavorable for manufacturing.
Therefore, the present invention provides a kind of new wafer-level packaging method, methods described after isolation layer is formed, using swashing
Light thermal annealing makes annealing treatment to isolation layer, so as to improve the density of isolation layer, prevents isolation layer peeling-off or ftractures,
The waterproof ability of isolation layer is improve simultaneously, the isolation performance of isolation layer is mentioned raising.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of level packaging methods of wafer 100, refer to Fig. 2 to Fig. 6.
Refer to Fig. 2, there is provided wafer 100, wafer 100 has first surface 100A and second surface 100B.
Multiple chip units are could be formed with wafer 100, can have Cutting Road, each chip unit between chip unit
By one single chip can be formed after encapsulation and cutting.Specifically, having multiple images sensor in the present embodiment wafer 100
Chip unit.
In the present embodiment, first surface 100A is the active face of wafer 100, and second surface 100B is the back side of wafer 100.
But, in other embodiments of the invention, first surface 100A can be the back side of wafer 100, and second surface 100B can
Think the active face of wafer 100, now, the level packaging methods of wafer 100 are simultaneously a kind of flip-chips（flip chip）Encapsulation side
Method.
Please continue to refer to Fig. 2, the first surface 100A of wafer 100 and substrate 200 are bonded in one using adhesive 300
Rise.
In the present embodiment, adhesive 300 uses organic adhesion agent.Although organic adhesion agent is relative to inorganic adhesive 300
For, heat resisting temperature is relatively low, but organic adhesion agent has adhesion that speed is fast, do not influence bonded structure, it is readily removable remove, low cost and
The features such as adhesive strength is high, therefore the first surface 100A of wafer 100 and substrate 200 are bonded in one using organic adhesion agent
Rise.Specifically, organic adhesion agent can be epoxyn.
Due in the wafer 100 of the present embodiment, chip unit is image sensor chip unit, therefore, the of wafer 100
Being made on one surface 100A has photosensitive array unit.Now, substrate 200 is needed with light transmission, to ensure that light can shine
It is mapped to the photosensitive array unit in image sensor chip unit.So in the present embodiment, substrate 200 can select glass base
Plate, because glass substrate has good light transmission.But, in other embodiments of the invention, the core in wafer 100
When blade unit need not receive illumination, substrate 200 can use other materials.
Please continue to refer to Fig. 2, isolation layer 400a is formed in the second surface 100B of wafer 100.
Because the adhesive 300 of the present embodiment is organic adhesion agent, therefore, its heat resisting temperature is relatively low, is forming passivation layer
When, it is necessary to by temperature control below 200 DEG C, bonding effect be lost to prevent adhesive 300 to be heated too high.
In the present embodiment, the material of isolation layer 400a can select low temperature oxide.The formation temperature of low temperature oxide is relatively low,
It may therefore be assured that adhesive 300 be notheated it is too high.Further, in the present embodiment, low temperature oxide is specifically as follows two
Silica.
In the present embodiment, can using plasma enhancing chemical vapour deposition technique（Plasma Enhanced Chemical
Vapor Deposition, PECVD）The isolation layer 400a that formation is made up of silica.PECVD sinks
Area method makees energy source using low temperature plasma, and wafer 100 is placed under low pressure on the negative electrode of glow discharge, is put using aura
Electricity（Or separately add heater）Wafer 100 is warmed up to predetermined temperature, then pass to appropriate reacting gas, gas is through a series of
Chemical reaction and plasma reaction, solid film, i.e. isolation layer 400a are formed on the surface of wafer 100.
In the plasma enhanced chemical vapor deposition method that the present embodiment is used, a large amount of high-energy are contained in plasma
Electronics, they chemical vapor deposition processes can be provided needed for activation energy.Electronics can promote with the collision of gas molecule in space
The decomposition of gas molecule, chemical combination, excite and ionization process, generation activity various chemical groups very high, thus significantly reducing
Learn the temperature range of thin film deposition in vapour deposition so that originally need the chemical vapor deposition processes that can just carry out at high temperature
It is able to be realized in low temperature.In addition to it can realize thin film deposition under cryogenic, plasma enhanced chemical vapor deposition
Method also has passivation in itself, and the passivation can further improve the isolation performance of formed isolation layer 400a.
In the present embodiment, if the thickness of isolation layer 400a is too small, good buffer action can not be played, but such as
The thickness of fruit isolation layer 400a is too big, then can increase subsequent technique（For example needed in isolation layer when metal interconnecting wires are made
Perforate in 400a）Difficulty, and cause unnecessary waste, consider above-mentioned both sides factor, isolation layer 400a's
Thickness range can be
Fig. 3 is refer to, laser thermal anneal treatment is carried out to isolation layer 400a.
Fig. 4 is photon energy and the absorption coefficient of silica and the relation curve of absorption depth.From energy level principle,
Material absorbing photon has selectivity, and the only photon of particular energy can just be absorbed by silica.It can be seen from figure 4 that
When photon energy is 9eV, there is maximum simultaneously in the absorption coefficient and absorption depth of silica, thus, it can be known that titanium dioxide
Silicon energy-absorbing is the photon of 9eV, therefore, the present embodiment selects energy for the black light of 9eV carries out institute to silica
State laser thermal anneal treatment.
In the present embodiment, laser 500 is by laser emitting elements（Do not show）Produce.Laser emitting elements can be ultraviolet company
Continuous light laser, ultraviolet continuous light laser can produce ultraviolet continuous light using crystalline material nonlinear effect conversion method, and
The laser that corresponding parameter obtains required energy can as needed be set.
In the present embodiment, the laser beam that laser emitting elements are formed can swash with rectangular or circle, when for rectangle
The length of light light beam can be 15.13mm, and width can also be 15.13 millimeters.
During annealing, on the isolation layer 400a that laser emitting elements are located at, and form laser beam and be radiated at isolation layer 400a
On, then laser beam is irradiated to isolation layer 400a.
During annealing, can be projected using arc（shot）Mode (projected path that i.e. laser 500 is formed is arc) is right
Isolation layer 400a is irradiated, i.e., the laser beam as produced by laser emitting elements is projected to isolation layer 400a, can be according to certainly
Go up down, left and right treatment track back and forth is carried out, and projection time can be 150ns every time.
During annealing, can be by controlling the luminosity of the Power Control laser 500 of laser emitting elements（Luminosity refers to that luminous intensity exists
Density on assigned direction）.Also, homogenizer is also provided between laser emitting elements and isolation layer 400a surfaces,
To cause the equalizing light rays in laser beam.
In the present embodiment, if the time of annealing is oversize, the atom in isolation layer 400a does not carry out good weight
Row, the isolation layer 400a density after treatment is still smaller, and structure is still more loose, therefore, it is still easily peeling-off or open
Split, but, if the time of annealing is oversize, the temperature of isolation layer 400a may be caused to be delivered to wafer 100, cause crystalline substance
The temperature of circle 100 is higher, so that the adhesive 300 of adhesive wafer 100 is heated too high and loses bonding effect.Therefore, this reality
Apply in example, the process time scope control of laser thermal anneal treatment is carried out to whole wafer 100 in 1min~2min.
In the range of above-mentioned annealing time, the present embodiment can by the control of the temperature range of isolation layer 400a 600 DEG C~
900 DEG C, and due to projecting duration every time（150ns）It is very short, therefore during annealing, the temperature range of wafer 100
Can control below 200 DEG C, so that ensure the influence of other structures in wafer 100 not Stimulated Light thermal annealing, it is same to ensure
The influence of the not Stimulated Light thermal annealing of adhesive 300.
Fig. 5 is refer to, isolation layer 400b is formd after laser thermal anneal treatment, as shown in Figure 5.
After being processed by laser thermal anneal, the density of isolation layer 400b is improved, and density is improved and can both prevent isolation layer
400b is peeling-off or ftractures, and waterproof ability can be improved again, therefore isolation layer 400b is not hygroscopic, and isolation performance is significantly carried
It is high.Because isolation layer 400b isolation performances are improved, therefore it can play more preferable insulation blocking effect, and be swashed using described
Light thermal annealing only can anneal to isolation layer, other structures（Such as adhesive 300）Not by the shadow of the laser thermal anneal
Ring, therefore structural reliability packaged by the wafer-level packaging method is high.
Fig. 6 is refer to, metal interconnecting wires are formed on isolation layer 400b（Do not show）, then proceed on isolation layer 400b
The pad 610 that formation is electrically connected with the metal interconnecting wires.Passivation layer 620 is formed on isolation layer 400b and pad 610 afterwards,
Wherein passivation layer 620 exposes at least part of pad 610.Then formed under projection on the pad 610 that passivation layer 620 exposes
Metal level 630, finally forms soldered ball 640 on Underbump metallization layer 630.
In the present embodiment, the material of the metal interconnecting wires can be aluminium.The material of pad 610 can include aluminium, copper,
One or more any combination in silver, gold, nickel, tungsten.The material of passivation layer 620 both can be epoxy resin (Epoxy),
Polyimides（PI）, benzocyclobutene, the organic material, or silicon nitride, silicon oxynitride or silica etc. such as polyphenyl oxazole
Inorganic material.Underbump metallization layer 630 can include the sandwich constructions such as diffusion layer, barrier layer, wetting layer and anti oxidation layer, and
And Underbump metallization layer 630 can be by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method or sputter
(Sputtering) method is formed.The material of soldered ball 640 can for tin, Xi Yin, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium,
One or more any combination in the metals such as tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony, and in soldered ball 640
Activating agent can be included, soldered ball 640 can be formed by electroplating technology and reflow soldering process.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
1. a kind of wafer-level packaging method, it is characterised in that including：
Wafer and substrate are provided, the wafer has first surface and the second surface relative with first surface；
By the first surface of the wafer together with the substrate bonding；
Isolation layer is formed in the second surface of the wafer；
Laser thermal anneal treatment is carried out to the isolation layer；
Metal interconnecting wires and pad are formed on the isolation layer, the metal interconnecting wires are electrically connected with the pad；
Passivation layer, the passivation layer exposure at least partly pad are formed on the isolation layer and the pad；
Underbump metallization layer is formed on the pad；
Soldered ball is formed on Underbump metallization layer.
2. wafer-level packaging method as claimed in claim 1, it is characterised in that the material of the isolation layer includes low-temperature oxidation
Thing, the thickness range of the low temperature oxide includes
3. wafer-level packaging method as claimed in claim 2, it is characterised in that the low temperature oxide includes silica,
The laser that the laser thermal anneal treatment is used is black light, and the energy of the black light is 9eV.
4. wafer-level packaging method as claimed in claim 3, it is characterised in that the laser thermal anneal treatment to the crystalline substance
Round process time scope includes 1min~2min.
5. wafer-level packaging method as claimed in claim 4, it is characterised in that the LASER HEAT is carried out to the isolation layer and is moved back
During fire treatment, the temperature range of the isolation layer includes 600 DEG C~900 DEG C.
6. wafer-level packaging method as claimed in claim 5, it is characterised in that the LASER HEAT is carried out to the isolation layer and is moved back
During fire treatment, the temperature range of the wafer is controlled below 200 DEG C.
7. wafer-level packaging method as claimed in claim 2, it is characterised in that using plasma strengthens chemical vapor deposition
Method forms the isolation layer in the second surface of the wafer.
8. wafer-level packaging method as claimed in claim 1, it is characterised in that the first surface of the wafer makes photosensitive
Array element.
9. wafer-level packaging method as claimed in claim 1, it is characterised in that the substrate is glass substrate.
10. wafer-level packaging method as claimed in claim 1, it is characterised in that using adhesive by the first of the wafer
Together with the substrate bonding, the adhesive is organic adhesion agent on surface.
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| CN201310425771.0A CN104465411B (en) | 2013-09-17 | 2013-09-17 | Wafer level package method |
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| CN201310425771.0A CN104465411B (en) | 2013-09-17 | 2013-09-17 | Wafer level package method |
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| CN104465411B true CN104465411B (en) | 2017-05-17 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005187806A (en) * | 2004-11-29 | 2005-07-14 | Japan Science & Technology Agency | Light emitting thin film and optical device thereof |
| CN1933106A (en) * | 2005-09-12 | 2007-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for producing surface more smooth golden convex points |
| CN101000872A (en) * | 2006-01-11 | 2007-07-18 | 日月光半导体制造股份有限公司 | Wafer processing method |
| CN102959030A (en) * | 2011-03-03 | 2013-03-06 | 日东电工株式会社 | Heat-peelable adhesive sheet |
-
2013
- 2013-09-17 CN CN201310425771.0A patent/CN104465411B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005187806A (en) * | 2004-11-29 | 2005-07-14 | Japan Science & Technology Agency | Light emitting thin film and optical device thereof |
| CN1933106A (en) * | 2005-09-12 | 2007-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for producing surface more smooth golden convex points |
| CN101000872A (en) * | 2006-01-11 | 2007-07-18 | 日月光半导体制造股份有限公司 | Wafer processing method |
| CN102959030A (en) * | 2011-03-03 | 2013-03-06 | 日东电工株式会社 | Heat-peelable adhesive sheet |
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| CN104465411A (en) | 2015-03-25 |
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