CN104465402B - A kind of semiconductor device fabrication processes - Google Patents
A kind of semiconductor device fabrication processes Download PDFInfo
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- CN104465402B CN104465402B CN201410825942.3A CN201410825942A CN104465402B CN 104465402 B CN104465402 B CN 104465402B CN 201410825942 A CN201410825942 A CN 201410825942A CN 104465402 B CN104465402 B CN 104465402B
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 238000005389 semiconductor device fabrication Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 238000004380 ashing Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 31
- 230000002829 reductive effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 8
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- 238000002360 preparation method Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
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- 238000012986 modification Methods 0.000 description 3
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 238000000407 epitaxy Methods 0.000 description 2
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- 238000004519 manufacturing process Methods 0.000 description 2
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
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- 239000002800 charge carrier Substances 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a kind of semiconductor device fabrication processes with super-junction structure, comprise the following steps：The Semiconductor substrate of one first conduction type is provided, the sacrifice layer with some first grooves is prepared on the Semiconductor substrate；Prepare the side wall that a side wall is covered in first groove；First groove is filled by the first epitaxial layer for preparing the second conduction type；Sacrifice layer and side wall are removed, to form second groove in the first epitaxial layer；Second groove is filled by the second epitaxial layer for preparing the first conduction type.The present invention is by using advanced amorphous carbon technique so that the N-type semiconductor material of super-junction structure and p-type semiconductor material interface are vertically smooth, and N-type semiconductor material keeps accurate consistent with p-type semiconductor material width, improves superjunction devices performance.And due to using advanced amorphous carbon technique, P posts and N posts width can be reduced to below 40nm, so as to substantially reduce cell density.
Description
Technical field
The present invention relates to semiconductor preparation field, specifically, and in particular to a kind of semiconductor device with super-junction structure
Part preparation technology.
Background technology
At high-voltage MOSFET field (400V~1000V), superjunction (Super Junction) structure is as a kind of advanced
Drift region structure is increasingly paid attention to by industrial quarters.The drift region of super-junction structure is high using alternate PN junction structure substitution tradition
Single conduction type drift region in MOSFET is pressed, introduces transverse electric field in drift region so that device drift region is in less pass
Powering off pressure can be completely depleted, and breakdown voltage is only relevant with depletion layer thickness and critical electric field.Therefore, in identical resistance to pressure,
The doping concentration of super-junction structure drift region can improve an order of magnitude, can reduce by 5~10 times of conducting resistance.
Power MOSFET is typically applied in the device for needing power conversion and power amplification.Come for power conversion apparatus
Say, commercially available representational device for example electrical bilateral diffusion MOS FET (DMOSFET).It is brilliant in the power to routinize
In body pipe, most breakdown voltage BV is by drift area carrier, in order to provide higher breakdown voltage BV, drift region to device
Generally require and be lightly doped.But the drift region being lightly doped can produce high conducting resistance Rdson.For a typical transistor
Speech, what is simplified thinks conducting resistance and BV2.5It is directly proportional.Therefore, for traditional transistor, with breakdown voltage BV increase,
Conducting resistance also increased dramatically.
Super-junction device as shown in Figure 1 is a kind of well-known power semiconductor.Super junction transistor carries
Gone out it is a kind of can be while very high off-state breakdown voltage BV be maintained, the method that obtains very low conducting resistance.It is super
Level junction device contains alternate P-type and N-type the doping column to be formed in drift region.Off-state is switched in MOSFET
When, can be under the relatively low voltage that compares, column is with regard to completely depleted, so as to maintain very high breakdown voltage, because vertical
Post having lateral depletion, therefore whole P and N-type column all exhaust substantially.For super junction, increase and the breakdown voltage BV of conducting resistance
It is directly proportional, increase than traditional semiconductor structure slower.Therefore, for identical high-breakdown-voltage BV, super junction device
Part has lower conducting resistance than traditional MOSFET element.Or be said differently, conversely, for specific electric conduction
Resistance, super-junction device have higher BV than traditional MOSFET.On more related contents of super junction, such as Iwamoto,
Sato et al. is in 2002 in document 241- involved by " the 14th power semiconductor and integrated circuit seminar publication "
" the 24m Ω cm of the announcement of page 2442It is detailed in 680V silicon super junctions MOSFET " to propose super-junction device, it is complete that its is quoted hereby
Text is by reference.
The structure of super junction is mainly realized by two kinds of techniques at present：Multiple extension, deep trouth extension, the difficult point of manufacture are shape
Into the P-type semiconductor post and N-type semiconductor post of the feature of tool high-aspect-ratio.Multiple epitaxy method is in N+ type Semiconductor substrates
Need the drift region of thickness, to carry out p-type ion implanting after each extension, finally anneal and formed using multiple epitaxial growth
Continuous P-type semiconductor post.This method complex process, time-consuming and cost is high, and is difficult to reduce cell density.Deep trouth extension side
Method is to etch deep trouth on certain thickness N-type semiconductor epitaxial layer, and P-type semiconductor epitaxial growth is then carried out in deep trouth.
The relatively multiple epitaxy technique method of this method is simple, also reduces cost, but the filling that is delayed outside deep trouth is more difficult, etches depth-to-width ratio
Larger trench process difficulty is big and needs expensive equipment.
Therefore, some propose various new processes on the basis of based on deep trouth extension in the prior art, can
To reduce the technology difficulty for preparing super junction, but it is difficult to cause P-type semiconductor material in p-type semiconductor material epitaxial process is carried out
The vertical side of material is smooth, causes just to cause the also out-of-flatness of PN interfaces after extension N-type semiconductor material, so as to influence whether
It is reversely pressure-resistant.In addition, accurately control p-type semiconductor material difficulty consistent with N-type semiconductor material width larger by extension,
And it is difficult to reduce cell density.
The content of the invention
The invention provides a kind of new superjunction devices preparation method, not only effectively reduces superjunction technology difficulty, simultaneously
It ensure that PN interfaces are more vertical smooth, improve the reverse voltage endurance capability of device, in order to realize above technique effect, can use such as
Lower step prepares super-junction semiconductor device：Being prepared on the Semiconductor substrate of the first conduction type has some first grooves
Sacrifice layer；Prepare the side wall that a side wall is covered in first groove；The first epitaxial layer of the second conduction type is prepared by the first ditch
Groove is filled；Sacrifice layer and side wall are removed successively, to form some second grooves in the first epitaxial layer；It is conductive to prepare first
Second groove is filled by the second epitaxial layer of type.
Above-mentioned semiconductor device fabrication processes, wherein, Semiconductor substrate includes base substrate and is covered in bottom lining
Cushion on bottom；The ion doping concentration of cushion is less than the ion doping concentration of base substrate.
Above-mentioned semiconductor device fabrication processes, wherein, there is the step of sacrifice layer of some first grooves to include for preparation：
Sequentially form sacrifice layer, first medium layer, second dielectric layer and photoresist from bottom to top on Semiconductor substrate；Carry out photoetching
Technique, some openings are formed in photoresist and first medium layer, second dielectric layer；
Sacrifice layer is performed etching using opening, to form some first grooves in sacrifice layer.
Above-mentioned semiconductor device fabrication processes, wherein, first medium layer is darc layer, and second dielectric layer is BARC layer.
Above-mentioned semiconductor device fabrication processes, wherein, after some first grooves are formed in sacrifice layer, remove photoresist
And second dielectric layer, and retain the first medium layer at the top of sacrifice layer.
Above-mentioned semiconductor device fabrication processes, wherein, photoresist and second dielectric layer are removed using wet-etching technology,
But without the removal mode of ashing processing, sacrifice layer is avoided to be damaged.
Above-mentioned semiconductor device fabrication processes, wherein, after some first grooves are formed in sacrifice layer, remove photoetching
Glue, second dielectric layer and first medium layer.
Above-mentioned semiconductor device fabrication processes, wherein, using wet-etching technology remove photoresist, second dielectric layer and
First medium layer, but without the removal mode of ashing processing, avoid sacrifice layer from being damaged.
Above-mentioned semiconductor device fabrication processes, wherein, sacrifice layer is amorphous carbon；Handle to remove using ashing and sacrifice
Layer.
Above-mentioned semiconductor device fabrication processes, wherein, side wall is the oxide of silicon；Removing sacrifice layer and then adopting
Side wall is removed with hydrogen fluoride solution.
Above-mentioned semiconductor device fabrication processes, wherein, side wall is the nitride of silicon；Removing sacrifice layer and then adopting
Side wall is removed with hot phosphoric acid solution.
Above-mentioned semiconductor device fabrication processes, wherein, side wall thicknesses are 5-20 μm.
Above-mentioned semiconductor device fabrication processes, wherein, the thickness sum and first groove of sacrifice layer and first medium layer
The ratio of width is 5:1 to 1:Between 1.
Above-mentioned semiconductor device fabrication processes, wherein, the thickness of sacrifice layer and the ratio of first groove are 5:1 to 1:1
Between.
Above-mentioned semiconductor device fabrication processes, wherein, when preparing the first epitaxial layer, extension speed is not more than 1.5 μm/point
Clock.
Above-mentioned semiconductor device fabrication processes, wherein, when preparing the second epitaxial layer, extension speed is not more than 2 μm/point
Clock.
Above-mentioned semiconductor device fabrication processes, wherein, the first conduction type is N-type, and the second conduction type is p-type.
Above-mentioned semiconductor device fabrication processes, wherein, after removing sacrifice layer and side wall, the second groove of formation, which has, puts down
The vertical sidewall pattern in smooth face.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent upon.The identical mark instruction identical part in whole accompanying drawings.Not deliberately proportionally
Draw accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is a kind of super-junction semiconductor device sectional view for adding Schottky contacts；
Fig. 2A~2L is the main process figure that the present invention prepares superjunction devices in one embodiment；
Fig. 3 A~3C are the partial routine figure that the present invention prepares superjunction devices in one embodiment；
Three kinds of applications of the superjunction devices that Fig. 4~6 are prepared for the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
Embodiment one
There is provided one has the Semiconductor substrate of the first conduction type.Optionally, the Semiconductor substrate includes base substrate 110
With the cushion 120 being covered in base substrate 110, the ion doping concentration of cushion 120 be less than base substrate 110 from
Sub- doping concentration.Sequentially form sacrifice layer 130, first medium layer 140, second dielectric layer from bottom to top on Semiconductor substrate
150 and photoresist (PR) 160, the structure of formation can refer to shown in Fig. 2A.Optional but unrestricted, first medium layer 140 is DARC
(dielectric Anti-reflective coating, dielectric anti reflective layer) layer, second dielectric layer 150 are BARC
(Bottom Anti Reflective coating, bottom antireflective coating) layer.In some embodiments, CVD can be used
Technique deposits one layer of SiON and is used as above-mentioned darc layer.Optional but unrestricted, above-mentioned sacrifice layer 130 is amorphous carbon
(amorphous carbon, AC).Wherein the thickness of sacrifice layer 130 need to be more than or equal to the P/N type semiconductors needed for superjunction devices
Pillar height degree, and the thickness of first medium layer 140, second dielectric layer 150 and photoresist 160 is according to the thickness requirement of sacrifice layer 130 and exposure
Light requirement is optimized.
In the present invention, nationality lifts photoetching effect by the first medium layer 140 below photoresist 160, second dielectric layer 150
Fruit and precision.In the present invention, it is using amorphous carbon as the reason for sacrifice layer 130：1st, reflectivity is small, advantageously reduces
PR thickness, avoids PR from collapsing, while reduces photoetching cost；2nd, reflectivity is small, can be less than 0.5%, so as to carry significantly
High exposure accuracy；3rd, photoresistance edge roughness (LER, line edge roughness) after exposing is reduced, so as to improve graph edge
Boundary's flatness；4th, larger etch process window (etch process window) can be realized；5th, in different line density regions
Between there is less CD (critical size) micro loading effect (micro-loading effect)；6th, be advantageous to improve AEI
(After Etch Inspection, checked after etching) CDU (chemical dispense unit, chemical dispensing unit) is good
Good CD uniformity；7th, it is very easy to remove amorphous carbon by cineration technics (Ashing process), and it is non-to remove effect
Chang Hao, residual will not be produced.
Using photoetching process (including exposure, developing process) and etching technics, sacrifice layer 130 on cushion 120,
Form some grooves 210 in first medium layer 140, second dielectric layer 150 and photoresist 160, and in the bottom of groove 210, be located at
First groove 220 is then formed between adjacent remaining sacrifice layer 130, shown in reference picture 2B.Due to using advanced amorphous carbon
Technique, P posts and N posts width can be reduced to below 40nm, so as to substantially reduce cell density.
Photoresist 160, second dielectric layer 150 are removed using wet-etching technology, shown in reference picture 2C.In order to retain and protect
Protect amorphous carbon layer (i.e. sacrifice layer 130), it is impossible to which photoresist is removed using cineration technics (Ashing process).In this reality
Apply in example, it is optional that photoresist 160 and second dielectric layer 150 are removed using wet-etching technology, and retain and pushed up positioned at sacrifice layer 130
The first medium layer 140 in portion, to avoid sacrifice layer 130 by etching injury.
In order to ensure the quality of subsequent selective epitaxial, it is desirable to which the depth-width ratio of groove 210 is 5:1 to 1:Between 1, that is, sacrifice
Layer 130 thickness+the ratio between thickness of first medium layer 140 (if first medium layer 140 does not remove) and the width of first groove 220 is 5:
1 to 1:Between 1.
The side wall 171 for being covered the remaining side wall of sacrifice layer 130 is formed in first groove 220.Should specifically, preparing
The step of side wall 171, can refer to shown in Fig. 2 D to Fig. 2 E：After the structure shown in Fig. 2 C is formed, first deposit or grow one layer of side
The walling bed of material 170 is covered in the surface that sacrifice layer 130, first medium layer 140 and cushion 120 expose；It can use afterwards each
The dry etch process offside walling bed of material 170 of anisotropy performs etching, by first medium layer 140 and the top of cushion 120
Spacer material layer 170 is removed, and formation is covered in sacrifice layer 130 and the side wall 171 of the side wall of first medium layer 140.
It is follow-up without fixed in order to ensure because the grainiess of amorphous carbon is close to conventional semiconductor material (such as silicon, germanium)
The quality of (i.e. first groove 220) semiconductor epitaxial is, it is necessary to deposit or grow a layer crystal kernel structure and semiconductor in shape carbon groove
Larger material is differed, for example with oxide (such as SiO of silicon2) or silicon nitride (such as Si3N4) it is used as spacer material layer
170.Optional but unrestricted, in Fig. 2 E, the thickness of the side wall 171 of formation is preferably between 5-20 μm.It should be noted that should
Side wall 171 is preferably simultaneously covered sacrifice layer 130, the side wall of first medium layer 140, but in some other embodiment
In, can also be by adjusting etching reaction condition so that side wall 171 is only placed only in the side wall of sacrifice layer 130, and this is to the present invention
It can't impact.
The first epitaxial layer 180 with the second conduction type of Semiconductor substrate films of opposite conductivity is prepared, will be located at sacrificial
130 first groove 220 is filled in domestic animal layer, and nationality makes the first epitaxial layer 180 and the top surface of sacrifice layer 130 by planarization process
Flush, shown in reference picture 2F-2G.It is optional but unrestricted, selective epitaxial p-type semiconductor material, i.e. one side extension, one side soft quarter
(soft etch) trenched side-wall and first epitaxial layer 180 at top are lost, its extension upper surface is exceeded first medium layer
(if above-mentioned steps eliminate darc layer, the upper surface of the first epitaxial layer 180 exceedes the upper table of sacrifice layer 130 for 140 upper surface
Face).Wherein soft-etch can select the board of the insitu extensions+soft-etch with Siconi modules.In order to ensure
The quality of first epitaxial layer 180 in groove, it is desirable to which extension speed is not more than 1.5 μm/minute.Formed structure shown in Fig. 2 F it
Afterwards, can be ground using CMP, by the first epitaxial layer 180, side wall 171 and the first medium layer of the top surface of sacrifice layer 130
140 are removed, and flush the first epitaxial layer 180 and the top surface of sacrifice layer 130.
Sacrifice layer 130 and side wall 171 are removed successively, and second groove 230 is formed in the first epitaxial layer 180.Use first
Cineration technics, the sacrifice layer 130 of amorphous carbon is removed, to form second groove 230 in the first epitaxial layer 180, such as Fig. 2 H institutes
Show.Side wall 171 is removed using wet processing again afterwards, as shown in figure 2i.Before if oxide skin(coating) of the material of side wall 171 for silicon
Hydrogen fluoride dilution can be used to remove side wall 171, be gone before if nitride of the material of side wall 171 for silicon using hot phosphoric acid liquid
Except side wall 171.Because side wall 171 has selected the material to be differed greatly with the material of the first epitaxial layer 180, therefore carrying out wet method quarter
During erosion, etching liquid can peel off side wall 171 with higher etch rate, and the damage to the first epitaxial layer 180 then compared with
Small, at this moment p-type post is very vertical smooth.Please continue to refer to accompanying drawing 2J, it is expressed as Fig. 2 I stereogram.
The second epitaxial layer 190 for preparing the first conduction type is covered on the first epitaxial layer 180, by the first epitaxial layer
Second groove 230 in 180 is filled, and makes the upper surface of the second epitaxial layer 190 more than the upper surface of the first epitaxial layer 180,
As shown in figure 2k.It is optional but unrestricted, selective epitaxial process can be used to prepare the second epitaxial layer 190 of N-type, while in order to protect
P-type semiconductor intercolumniation is demonstrate,proved every middle N-type semiconductor epitaxial quality, it is desirable to which extension speed is not more than 2 μm/minute.Carry out afterwards flat
Change is handled, and is flushed the second epitaxial layer 190 and the top surface of the first epitaxial layer 180, is made annealing treatment afterwards, with a lateral direction
Overlapping N posts 191 and P posts 181 are formd, its P/N interface is very vertical smooth, and width keeps accurate consistent.Compared to tradition
Preparation method, cell density substantially reduce.
Meanwhile in other embodiments of the invention, also can be by sacrifice layer 130 after the structure shown in Fig. 2 B is formed
The first medium layer 140 at top, second dielectric layer 150 are removed, and are deposited spacer material layer 170 afterwards and are covered in sacrifice layer
130 and the surface that exposes of cushion 120, then optional, the thickness of sacrifice layer 130 preferably exists with the ratio of first groove 220
5:1 to 1:Between 1, it can refer to shown in Fig. 3 A；Afterwards using plasma etching industrial by the top of sacrifice layer 130 and cushion 120
Spacer material layer 170 remove, form the structure shown in Fig. 3 B；The first epitaxial layer 180 for preparing the first conduction type afterwards will
Groove in sacrifice layer is filled, as shown in Figure 3 C.Processing is ground afterwards so that the top of the first epitaxial layer 180
Face flushes with the top surface of sacrifice layer 130, and the process after Fig. 3 C and previously described process are essentially identical, can refer to accompanying drawing 2G~
2L and associated description, will not be described here.
Embodiment two
A kind of semiconductor device fabrication processes are present embodiments provided, are comprised the following steps：
Step S1：A sacrifice layer is etched first, and a plurality of spaced first groove is formed in sacrifice layer.It is optional but
Unrestricted, the sacrifice layer selects amorphous carbon, and the sacrifice layer is performed etching using photoetching and etching technics, with wherein
Form a plurality of spaced first groove.
Step S2：A side wall is prepared to be covered in the side wall of first groove.Optional but unrestricted, the material of the side wall can be with
For the nitride of the oxide of silicon, or silicon.The step of preparing the side wall mainly includes：The side walling bed of material is deposited first by device
Exposed surface is covered, and is performed etching afterwards using the anisotropic etch process offside walling bed of material, is covered in retaining
Side wall in the side wall of first groove.
Step S3：The first epitaxial layer of the conduction type of epitaxial growth first (such as p-type) in first groove, and afterwards
It is ground processing so that the top surface of the first epitaxial layer and sacrifice layer is flush.
Step S4：Sacrifice layer and side wall are removed successively, and a plurality of spaced second ditch is formed in the first epitaxial layer
Groove.It is optional but unrestricted, sacrifice layer (i.e. amorphous carbon) is first removed using cineration technics, moved afterwards using wet-etching technology
Except side wall.Wherein, when removing side wall, different wet etching liquid is selected according to the difference of material, such as when side wall is silicon
Oxide when, using hydrogen fluoride dilution remove side wall；And when side wall is the nitride of silicon, side is removed using hot phosphoric acid liquid
Wall.
Step S5：Epitaxial growth second conduction type (such as N-type) opposite with the first conduction type in second groove
The second epitaxial layer, and carry out milled processed so that the top surface of the second epitaxial layer and the first epitaxial layer is flush.Wherein, formerly
After removing side wall in preceding step S4, the vertical sidewall pattern with tabular surface of second groove is formed, ensures the second ditch
The PN junction of the second epitaxial layer of the second conduction type and the first epitaxial layer of the first conduction type in interface is that plane is put down in groove
Row knot.And nationality is had by having the column that the second epitaxial layer of the second conduction type is formed in second groove between second groove
The column that the first epitaxial layer for having the first conduction type is formed, alternates interval and is configured to super-junction structures.
In summary, due to present invention employs as above technical scheme, compared with prior art, by using advanced nothing
Shape carbon technique so that the N-type semiconductor material of super-junction structure and p-type semiconductor material interface are vertically smooth, and N-type is partly led
Body material keeps accurate consistent with p-type semiconductor material width, improves superjunction devices performance.And due to using advanced nothing
Shape carbon technique, and P posts and N posts width can be reduced to below 40nm, so as to substantially reduce cell density.Process variations of the present invention
Small, cost of implementation is relatively low, is adapted to promote production.
Fig. 4-6 is outlined using super-junction device, and the application of super junction improves power MOSFET Vbd and Rdson simultaneously
Concept.According to the initial invention for originating in the phase early 1980s, the drift region of super junction transistor device is
It is made up of multiple alternate n and p semiconductor stripeds.As long as striped is very narrow, and the charge carriers in neighbouring striped
The quantity of son is roughly equal, or reaches so-called charge balance, then is possible to consume striped under relatively low voltage
To the greatest extent.Once exhausting, it is an intrinsic silicon that striped, which just looks like, realizes the Electric Field Distribution of approaches uniformity, so as to obtain high breakdown potential
Pressure.It is prepared by the concept that lateral super junction device (Fig. 4) and vertical super-junction device (Fig. 5 and Fig. 6) may be by super junction.
But transversal device is more suitable for discrete device more suitable for integrated circuit, vertical super-junction device.Fig. 4 is represented in transversary
In, arranging situation of the striped in third dimension, referred to as 3D Resurf.Fig. 5 and Fig. 6 represents to be applied to vertical metal-oxidation
The layout of thing-semiconductor field (Cool MOS, MDMesh).All super-junction devices all have it is most prominent the characteristics of
In they have broken the limit on the silicon device of traditional non-super junction is carried in.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this has no effect on the substantive content of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of technical scheme protection.
Claims (15)
1. a kind of semiconductor device fabrication processes, it is characterised in that comprise the following steps：
The sacrifice layer with some first grooves is prepared on the Semiconductor substrate of the first conduction type；
Prepare the side wall that a side wall is covered in first groove；
First groove is filled by the first epitaxial layer for preparing the second conduction type；
Sacrifice layer and side wall are removed successively, to form some second grooves in the first epitaxial layer；
Second groove is filled by the second epitaxial layer for preparing the first conduction type；
Wherein,
Sacrifice layer is amorphous carbon, is handled using ashing and removes sacrifice layer；
Side wall is the oxide of silicon, is removing sacrifice layer and then is removing side using hydrogen fluoride solution and/or hot phosphoric acid solution
Wall.
2. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that Semiconductor substrate include base substrate and
The cushion being covered on the base substrate；
The ion doping concentration of cushion is less than the ion doping concentration of base substrate.
3. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that prepare sacrificial with some first grooves
The step of domestic animal layer, includes：
Sequentially form sacrifice layer, first medium layer, second dielectric layer and photoresist from bottom to top on Semiconductor substrate；
Photoetching process is carried out, some openings are formed in photoresist and first medium layer, second dielectric layer；
Sacrifice layer is performed etching using opening, to form some first grooves in sacrifice layer.
4. semiconductor device fabrication processes as claimed in claim 3, it is characterised in that first medium layer is darc layer, second
Dielectric layer is BARC layer.
5. semiconductor device fabrication processes as claimed in claim 3, it is characterised in that some first ditches are formed in sacrifice layer
After groove,
Photoresist and second dielectric layer are removed, and retains the first medium layer at the top of sacrifice layer.
6. semiconductor device fabrication processes as claimed in claim 5, it is characterised in that photoetching is removed using wet-etching technology
Glue and second dielectric layer, but without the removal mode of ashing processing, avoid sacrifice layer from being damaged.
7. semiconductor device fabrication processes as claimed in claim 3, it is characterised in that some first ditches are formed in sacrifice layer
After groove,
Remove photoresist, second dielectric layer and first medium layer.
8. semiconductor device fabrication processes as claimed in claim 7, it is characterised in that photoetching is removed using wet-etching technology
Glue, second dielectric layer and first medium layer, but without the removal mode of ashing processing, avoid sacrifice layer from being damaged.
9. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that side wall thicknesses are 5-20 μm.
10. semiconductor device fabrication processes as claimed in claim 5, it is characterised in that the thickness of sacrifice layer and first medium layer
Sum is spent with the ratio of first groove width 5:1 to 1:Between 1.
11. semiconductor device fabrication processes as claimed in claim 7, it is characterised in that the thickness and first groove of sacrifice layer
The ratio of width is 5:1 to 1:Between 1.
12. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that when preparing the first epitaxial layer, extension speed
Rate is not more than 1.5 μm/minute.
13. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that when preparing the second epitaxial layer, extension speed
Rate is not more than 2 μm/minute.
14. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that the first conduction type is N-type, second
Conduction type is p-type.
15. semiconductor device fabrication processes as claimed in claim 1, it is characterised in that after removing sacrifice layer and side wall, formed
Second groove there is the vertical sidewall pattern of tabular surface.
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