CN104465382B - Mos transistor source and drain forming method - Google Patents
Mos transistor source and drain forming method Download PDFInfo
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- CN104465382B CN104465382B CN201310435686.2A CN201310435686A CN104465382B CN 104465382 B CN104465382 B CN 104465382B CN 201310435686 A CN201310435686 A CN 201310435686A CN 104465382 B CN104465382 B CN 104465382B
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- grid structure
- lightly doped
- drain
- source
- mos transistor
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- 238000000034 method Methods 0.000 title claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000006467 substitution reaction Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 2
- 239000007924 injection Substances 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- -1 BF2 ions Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of MOS transistor source and drain forming method, including：In the silicon chip of grid structure is formed with, source electrode lightly doped district and drain electrode lightly doped district are formed respectively in grid structure both sides；Gate lateral wall is formed in grid structure both sides；Source region and drain region are formed respectively in the silicon chip of grid structure both sides of gate lateral wall is formed；In the layer where grid structure, barrier layer is formed on silicon chip；Hereafter, the side wall of grid structure both sides is removed, so as to leave groove structure between grid structure and barrier layer；By the use of grid structure and barrier layer as mask, ion implanting is carried out to silicon chip, so as to form new source electrode lightly doped district and new drain electrode lightly doped district in silicon chip surface；Filled media in groove structure is left between grid structure and barrier layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of MOS transistor source and drain side of being formed
Method.
Background technology
The transistor abbreviation MOS crystal of Metal-oxide-semicondutor (Metal-Oxide-Semiconductor) structure
Pipe.Nowadays, MOS transistor is had been widely used in most digital circuit and partial simulation circuit.
MOS transistor includes arrangement source electrode in the substrate and drain electrode, and is arranged on substrate and is located at source electrode and leakage
Grid between pole.
Fig. 1 to Fig. 3 schematically shows each step of the MOS transistor source and drain forming method according to prior art.
Specifically, as shown in Figure 1 to Figure 3, included according to the MOS transistor source and drain forming method of prior art：First,
It is being formed with grid structure 40（For example, grid structure 40 includes grid oxic horizon and polysilicon layer）Silicon chip 10 in, in grid
The both sides of structure 40 form source electrode lightly doped district 20 and drain electrode lightly doped district 30 respectively（As shown in Figure 1）；Then, in grid structure 40
Both sides form gate lateral wall 50（As shown in Figure 2）；Then, divide in the silicon chip of the both sides of grid structure 40 of gate lateral wall 50 is formed
Xing Cheng not source region 60 and drain region 70（As shown in Figure 3）.Wherein, for example, section of source region 60 and drain region 70
Face is U-shaped, sigma shapes or triangle.
But, in the MOS transistor source and drain forming method according to prior art, as shown in figure 3, forming source region 60
Become fairly small with remaining residual source electrode lightly doped district 21 and residual drain electrode lightly doped district 31 after drain region 70.And very
In many applications, the residual source electrode lightly doped district 21 and residual drain electrode lightly doped district 31 for only leaving very little part are undesirable.
Accordingly, it is desirable to be able to provide, a kind of can to form larger source electrode respectively above source region and drain region light
The scheme of doped region and drain electrode lightly doped district.
The content of the invention
The technical problems to be solved by the invention are can be in source there is provided one kind for there is drawbacks described above in the prior art
The source electrode lightly doped district of enlarged region and the MOS transistor source of drain electrode lightly doped district are formed above polar region domain and drain region respectively
Leak forming method.
In order to realize above-mentioned technical purpose, according to the present invention there is provided a kind of MOS transistor source and drain forming method, it is wrapped
Include：In the silicon chip of grid structure is formed with, source electrode lightly doped district and drain electrode lightly doped district are formed respectively in grid structure both sides；
Gate lateral wall is formed in grid structure both sides；Source area is formed respectively in the silicon chip of grid structure both sides of gate lateral wall is formed
Domain and drain region；In the layer where grid structure, barrier layer is formed on silicon chip；Hereafter, the side of grid structure both sides is removed
Wall, so as to leave groove structure between grid structure and barrier layer；By the use of grid structure and barrier layer as mask, to silicon chip
Ion implanting is carried out, so as to form new source electrode lightly doped district and new drain electrode lightly doped district in silicon chip surface；In grid structure and resistance
Filled media in groove structure is left between barrier.
Preferably, the section of source region and drain region is U-shaped, sigma shapes or triangle.
Preferably, the material of source region and drain region is SiGe or SiC.
Preferably, the material of etching barrier layer is one kind in SiO2, SiON or SiN.
Preferably, the material of gate lateral wall is silicon nitride.
Preferably for NMOS, the ion injected in ion implanting be As ions, P ion, N ions, C ions and Ge from
One or more in son etc..
Preferably for PMOS, the ion injected in ion implanting be BF2 ions, In ions and B ions, N ions, C from
One or more in son and Ge ions etc..
Preferably, grid structure includes grid oxic horizon and polysilicon layer.
Preferably, the material of medium and the material of gate lateral wall are identical.
Preferably, the material of medium is silicon nitride.
In the MOS transistor source and drain forming method according to the present invention, shape is distinguished above source region and drain region
Into larger new source electrode lightly doped district and new drain electrode lightly doped district, the source electrode lightly doped district and drain electrode lightly doped district of script are overcome
The defect that smaller strip is come.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 to Fig. 3 schematically shows each step of the MOS transistor source and drain forming method according to prior art.
Fig. 4 to Fig. 7 schematically shows each of MOS transistor source and drain forming method according to the preferred embodiment of the invention
Individual step.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
It can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 4 to Fig. 7 schematically shows each of MOS transistor source and drain forming method according to the preferred embodiment of the invention
Individual step.
Specifically, as shown in Figures 1 to 7, MOS transistor source and drain forming method bag according to the preferred embodiment of the invention
Include：
First, it is being formed with grid structure 40（For example, grid structure 40 includes grid oxic horizon and polysilicon layer）Silicon
In piece 10, source electrode lightly doped district 20 and drain electrode lightly doped district 30 are formed respectively in the both sides of grid structure 40（As shown in Figure 1）；
Then, gate lateral wall 50 is formed in the both sides of grid structure 40（As shown in Figure 2）；Preferably, the material of gate lateral wall 50
Expect for silicon nitride.
Then, source region 60 and drain electrode are formed respectively in the silicon chip of the both sides of grid structure 40 of gate lateral wall 50 is formed
Region 70（As shown in Figure 3）；Wherein, for instance, it is preferred that the section of source region 60 and drain region 70 is U-shaped, sigma shapes
Or triangle.It is further preferred that the material of source region 60 and drain region 70 is SiGe or SiC；The present invention is especially to source
The material of polar region domain 60 and drain region 70 is obvious for the improvement effect of SiGe or SiC application.
Source region 60 and drain region 70 can be formed using any proper method well known in the prior art.Example
Such as, it can be etched by silicon substrate, the step such as epitaxial growth forms source region 60 and drain region 70.
Hereafter, in the layer where grid structure 40, barrier layer 80 is formed on silicon chip 10；Preferably, etching barrier layer 80
Material be SiO2, SiON or SiN in one kind（As shown in Figure 4）；
Hereafter, the side wall of the both sides of grid structure 40 is removed, so as to leave groove between grid structure 40 and barrier layer 80
Structure（As shown in Figure 5）；
Hereafter, by the use of grid structure 40 and barrier layer 80 as mask, ion implanting is carried out to silicon chip 10（In Fig. 6
Shown in arrow）, so as to form new source electrode lightly doped district 80 and new drain electrode lightly doped district 90 on the surface of silicon chip 10（As shown in Figure 6）；
In fact, new source electrode lightly doped district 80 and the residual source electrode lightly doped district 21 and residual of new drain electrode lightly doped district 90 substitution script are leaked
Pole lightly doped district 31 so that source electrode lightly doped district and drain electrode lightly doped district can be bigger.
For example, for NMOS, the ion injected in ion implanting is As ions, P ion, N ions, C ions and Ge ions
One or more in；For PMOS, the ion injected in ion implanting is BF2 ions, In ions and B ions, N ions, C
One or more in ion and Ge ions etc..
Hereafter, filled media 100 in groove structure can be left between grid structure 40 and barrier layer 80.Preferably,
The material of medium 100 is identical with the material of gate lateral wall 50；For example, the material of medium 100 is silicon nitride.
In MOS transistor source and drain forming method according to the preferred embodiment of the invention, in source region and drain region
Top forms larger new source electrode lightly doped district and new drain electrode lightly doped district respectively, overcomes source electrode lightly doped district and the leakage of script
The defect that pole lightly doped district smaller strip is come.
Furthermore, it is necessary to explanation, unless stated otherwise or is pointed out, term " first " otherwise in specification, " the
Two ", the description such as " 3rd " is used only for distinguishing each component, element, step in specification etc., without being intended to indicate that each
Logical relation or ordinal relation between component, element, step etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible variations and modification are all made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of change.Therefore, every content without departing from technical solution of the present invention, the technical spirit pair according to the present invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (10)
1. a kind of MOS transistor source and drain forming method, it is characterised in that including：
In the silicon chip of grid structure is formed with, source electrode lightly doped district is formed respectively in grid structure both sides and drain electrode is lightly doped
Area；
Gate lateral wall is formed in grid structure both sides；
Source region and drain region are formed respectively in the silicon chip of grid structure both sides of gate lateral wall is formed, and are left residual source
Pole lightly doped district and residual drain electrode lightly doped district；
In the layer where grid structure, barrier layer is formed on silicon chip；
Hereafter, the side wall of grid structure both sides is removed, so as to leave groove structure between grid structure and barrier layer；
By the use of grid structure and barrier layer as mask, ion implanting is carried out to silicon chip, so as to form new source electrode in silicon chip surface
Lightly doped district and new drain electrode lightly doped district, new source electrode lightly doped district and the new drain electrode lightly doped district substitution residual source electrode are lightly doped
Area and residual drain electrode and become much larger lightly doped district；
Filled media in groove structure is left between grid structure and barrier layer.
2. MOS transistor source and drain forming method according to claim 1, it is characterised in that source region and drain region
Section be U-shaped, sigma shapes or triangle.
3. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that source region and drain region
The material in domain is SiGe or SiC.
4. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material on barrier layer is
One kind in SiO2, SiON or SiN.
5. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material of gate lateral wall is
Silicon nitride.
6. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that for NMOS, ion note
The ion for entering injection is the one or more in As ions, P ion, N ions, C ions and Ge ions.
7. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that for PMOS, ion note
The ion for entering middle injection is BF2One or more in ion, In ions and B ions, N ions, C ions and Ge ions.
8. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that grid structure includes grid
Oxide layer and polysilicon layer.
9. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material and grid of medium
The material of side wall is identical.
10. MOS transistor source and drain forming method according to claim 1 or 2, it is characterised in that the material of medium is nitrogen
SiClx.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310435686.2A CN104465382B (en) | 2013-09-23 | 2013-09-23 | Mos transistor source and drain forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310435686.2A CN104465382B (en) | 2013-09-23 | 2013-09-23 | Mos transistor source and drain forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465382A CN104465382A (en) | 2015-03-25 |
| CN104465382B true CN104465382B (en) | 2017-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310435686.2A Active CN104465382B (en) | 2013-09-23 | 2013-09-23 | Mos transistor source and drain forming method |
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| Country | Link |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504023A (en) * | 1995-01-27 | 1996-04-02 | United Microelectronics Corp. | Method for fabricating semiconductor devices with localized pocket implantation |
| US5534447A (en) * | 1995-11-13 | 1996-07-09 | United Microelectronics Corporation | Process for fabricating MOS LDD transistor with pocket implant |
| US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
| US5693974A (en) * | 1995-07-03 | 1997-12-02 | Taiwan Semiconductor Manufacturing Company Ltd | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS |
| US5736446A (en) * | 1997-05-21 | 1998-04-07 | Powerchip Semiconductor Corp. | Method of fabricating a MOS device having a gate-side air-gap structure |
| US6190981B1 (en) * | 1999-02-03 | 2001-02-20 | United Microelectronics Corp. | Method for fabricating metal oxide semiconductor |
| US6261912B1 (en) * | 1999-08-10 | 2001-07-17 | United Microelectronics Corp. | Method of fabricating a transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7642607B2 (en) * | 2005-08-10 | 2010-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with reduced recess on substrate surface |
-
2013
- 2013-09-23 CN CN201310435686.2A patent/CN104465382B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504023A (en) * | 1995-01-27 | 1996-04-02 | United Microelectronics Corp. | Method for fabricating semiconductor devices with localized pocket implantation |
| US5693974A (en) * | 1995-07-03 | 1997-12-02 | Taiwan Semiconductor Manufacturing Company Ltd | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS |
| US5534447A (en) * | 1995-11-13 | 1996-07-09 | United Microelectronics Corporation | Process for fabricating MOS LDD transistor with pocket implant |
| US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
| US5736446A (en) * | 1997-05-21 | 1998-04-07 | Powerchip Semiconductor Corp. | Method of fabricating a MOS device having a gate-side air-gap structure |
| US6190981B1 (en) * | 1999-02-03 | 2001-02-20 | United Microelectronics Corp. | Method for fabricating metal oxide semiconductor |
| US6261912B1 (en) * | 1999-08-10 | 2001-07-17 | United Microelectronics Corp. | Method of fabricating a transistor |
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| Publication number | Publication date |
|---|---|
| CN104465382A (en) | 2015-03-25 |
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