CN104465376B - Transistor and forming method thereof - Google Patents

Transistor and forming method thereof Download PDF

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Publication number
CN104465376B
CN104465376B CN201310425291.4A CN201310425291A CN104465376B CN 104465376 B CN104465376 B CN 104465376B CN 201310425291 A CN201310425291 A CN 201310425291A CN 104465376 B CN104465376 B CN 104465376B
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layer
side wall
grid structure
forming method
source
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CN104465376A (en
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A kind of transistor and forming method thereof, the forming method of the transistor include：Semiconductor substrate is provided；Grid structure is formed in semiconductor substrate surface, there is mask layer at the top of the grid structure；In the grid structure and mask layer both sides the first side wall of sidewall surfaces and the second side wall；Semiconductor substrate surface in the grid structure both sides forms semiconductor material layer, and the surface of the semiconductor material layer is less than the surface of grid structure；Ion implanting is carried out to semiconductor material layer, forms source-drain area；The second side wall is removed, groove is formed between source-drain area and the side wall of grid first；The Semiconductor substrate of bottom portion of groove is carried out that ion implanting is lightly doped, forms lightly doped district；The mask layer at the top of grid structure is removed, exposes the top surface of grid structure；Metal silicide layer is formed on source-drain area, lightly doped district surface.The above method can reduce the source-drain area resistance of transistor, improve the performance of transistor.

Description

Transistor and forming method thereof
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of transistor and forming method thereof.
Background technology
As the continuous development of semiconductor technology, integrated circuit integration degree more and more higher, the size of device are also continuous Reduce.But the continuous reduction of device size causes the performance of device to be also greatly affected.For example, short-channel effect, work( The problems such as consumption is big, parasitic capacitance is big.
Prior art is in SOI（Silicon on insulation bottom）Semiconductor devices is formed on substrate, forms transistor on soi substrates, The parasitic capacitance in transistor can be reduced, improve the speed of service, and the transistor has lower power consumption.
But the thinner thickness of the top silicon layer due to SOI substrate, the transistor directly formed in the SOI substrate The thinner thickness of source-drain area, there is higher series resistance, so, prior art is typically in the grid structure both sides of transistor Certain thickness silicon layer is epitaxially formed on substrate, then the source-drain area raised is formed in the silicon layer, and in the source-drain area Surface forms metal silicide layer, so as to improve the thickness of source-drain area, reduces the resistance of source-drain area.
But the series resistance of the source-drain area of the transistor also needs to further reduce.
The content of the invention
The present invention solve the problems, such as to be to provide a kind of transistor and its forming method, reduce the string of the source-drain area of transistor Join resistance.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Semiconductor substrate is provided； The semiconductor substrate surface forms grid structure, has mask layer at the top of the grid structure；In the grid structure and cover Film layer both sides sidewall surfaces form sidewall structure, and the sidewall structure includes being located at the grid structure and mask layer both sides side wall First side wall on surface and the second side wall positioned at the first side wall surface；Semiconductor substrate in the grid structure both sides Surface forms semiconductor material layer, and the surface of the semiconductor material layer is less than the surface of grid structure；To the semiconductor material The bed of material carries out ion implanting, forms source-drain area；Second side wall is removed, the shape between the source-drain area and the side wall of grid first Into groove；The Semiconductor substrate of the bottom portion of groove is carried out that ion implanting is lightly doped, forms lightly doped district；Remove grid structure The mask layer at top, expose the top surface of grid structure；On the source-drain area surface, the lightly doped district surface of bottom portion of groove Form metal silicide layer.
Optionally, the Semiconductor substrate is silicon-on-insulator.
Optionally, the material of the mask layer is silica.
Optionally, the material of first side wall and the second side wall differs.
Optionally, the material of first side wall is silica, and the thickness of first side wall is more than
Optionally, the material of second side wall is silicon nitride or silicon oxynitride
Optionally, the material of the semiconductor material layer is silicon, germanium or SiGe.
Optionally, using selective epitaxial process, the semiconductor material layer is formed.
Optionally, the grid structure is included positioned at the gate dielectric layer of semiconductor substrate surface and positioned at the gate dielectric layer The grid on surface, the material of the gate dielectric layer is silica, the material of the grid is polysilicon.
Optionally, it is additionally included at the top of grid structure and also forms metal silicide layer.
Optionally, forming the method for the metal silicide includes：The source-drain area, bottom portion of groove lightly doped district, Forming metal layer on surface at the top of first side wall and grid structure；Made annealing treatment, in the source-drain area surface, groove-bottom The lightly doped district surface in portion and grid structure top surface form metal silicide layer；Remove remaining metal level.
Optionally, the material of metal level comprises at least a kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.
Optionally, the lightly doped district of the bottom portion of groove is fully converted to metal silicide.
Optionally, in addition to：Dielectric layer is formed on the metal silicide layer surface, the first side wall surface.
Optionally, the material of the dielectric layer is low-K dielectric material.
Optionally, the material of the dielectric layer comprises at least：Carborundum, silicon oxide carbide, organic siloxane polymer, fluorine carbon One kind in compound.
Technical scheme also provides a kind of transistor formed using the above method, including：Semiconductor substrate；Position In the grid structure of semiconductor substrate surface, the gate structure sidewall surface has the first side chamber；Positioned at the grid structure And first side wall both sides Semiconductor substrate in source-drain area, there is groove between the source-drain area and the first side wall, it is described The surface of source-drain area is higher than semiconductor substrate surface and is less than grid structure surface；Positioned at the source-drain area and the first side wall it Between bottom portion of groove Semiconductor substrate in lightly doped district；Positioned at the source-drain area surface, the lightly doped district table of bottom portion of groove The metal silicide layer in face.
Optionally, the material of the lightly doped district of the bottom portion of groove is metal silicide.
Optionally, in addition to the metal silicide layer at the top of the grid structure.
Optionally, positioned at the metal silicide layer surface, the first side wall surface and the dielectric layer for filling the full groove.
Compared with prior art, technical scheme has advantages below：
Technical scheme, the first side wall and the second side wall are formed in the grid structure both sides；Then with described Grid structure, the first side wall, the second side wall are mask, and the source-drain area raised is formed in the grid structure both sides；Then remove Second side wall, groove is formed between the source-drain area raised and the first side wall, exposes part semiconductor substrate Surface；The Semiconductor substrate of the bottom portion of groove is carried out that ion implanting is lightly doped, forms lightly doped district；In the source-drain area and Lightly doped district surface forms metal silicide layer simultaneously, and only metal silicide layer phase is formed on source-drain area surface with prior art Than can further reduce the resistance of lightly doped district, improve the performance of transistor.
Further, after the metal silicide layer is formed, the shape in the metal silicide layer surface and groove Into dielectric layer.The material of the dielectric layer is low-K dielectric material, can reduce the parasitic capacitance between source-drain area and grid, carry The performance of high transistor.
Brief description of the drawings
Fig. 1 is the structural representation of the transistor of the prior art of the present invention.
Fig. 2 to Figure 15 is the structural representation of the forming process of the transistor of embodiments of the invention.
Embodiment
As described in the background art, the series resistance of the source-drain area of transistor need further to drop in the prior art It is low.
Fig. 1 is refer to, for the structural representation of the transistor formed on soi substrates.
The transistor includes：Bottom silicon layer 10, the insulating barrier 11 positioned at bottom silicon surface, positioned at the insulating barrier table The source-drain area 12 raised in the top silicon layer in face；Gate dielectric layer 21 positioned at the top silicon layer surface, it is situated between positioned at the grid The grid 22 of matter layer surface, positioned at the gate dielectric layer 21 and the first side wall 23 and described first of the both sides sidewall surfaces of grid 22 Second side wall 24 on the surface of side wall 23.The transistor also includes the gold positioned at the top of grid 22 and the surface of source-drain area 12 Belong to silicide layer 25.
Because the top silicon layer of the SOI substrate is relatively thin, silicon is formed on the top silicon layer surface of the grid structure both sides Layer, so as to form the source-drain area 12 raised, the thickness of source-drain area 12 can be improved, reduces the series resistance of source-drain area 12；Institute The series resistance of the source-drain area 12 can equally be reduced by stating the surface of source-drain area 12 formation metal silicide layer 25.
But due to described some extended area of source-drain area 12（Lightly doped district）Positioned at first side wall 23, Second side wall 24, the lower section of gate dielectric layer 21, the thinner thickness of the extended area, and surface can not form metal silicide Layer, so as to which the extended area still has higher resistance, the performance of transistor can be influenceed.
Embodiments of the invention, in the extended area of the source-drain area（Lightly doped district）Part surface also form metallic silicon Compound layer, further reduce the series resistance of the source-drain area of transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
It refer to Fig. 2, there is provided Semiconductor substrate 100.
The material of the Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs, the semiconductor Substrate 100 can be that body material can also be composite construction such as silicon-on-insulator.Those skilled in the art can be according to partly leading The semiconductor devices formed on body substrate 100 selects the type of the Semiconductor substrate 100, therefore the class of the Semiconductor substrate Type should not limit the scope of the invention.
In the present embodiment, the Semiconductor substrate 100 for silicon-on-insulator（SOI）Substrate, the Semiconductor substrate 100 Insulating barrier 102 including bottom silicon layer 101, positioned at bottom silicon surface, the top silicon layer 103 positioned at the surface of insulating barrier 102.
In the silicon-on-insulator（SOI）Transistor is formed on substrate, the parasitic capacitance of transistor can be reduced, is improved brilliant The switching rate of body pipe, reduce the power consumption of transistor.
Fig. 3 is refer to, gate dielectric material layer 201 is formed on the surface of Semiconductor substrate 100, positioned at the gate dielectric layer The gate material layers 202 on the surface of material layer 201, and the mask layer 300 positioned at the surface of gate material layers 202.
The gate dielectric material layer 201 is formed using depositing operation, the depositing operation is chemical vapor deposition or atom Layer depositing operation, the thickness of the gate dielectric material layer 201 is 1nm to 100nm.
The gate material layers 202 are formed using depositing operation, the thickness of the gate material layers is 10nm~200nm.
In the present embodiment, the material of the gate dielectric material layer 201 is silica or silicon oxynitride, the gate material layers 202 material is polysilicon.
The material of the mask layer 300 is silica or silicon nitride, and the thickness of the mask layer 300 is 1nm ~200nm, subsequently the mask layer 300 is patterned, forms etching grid material layer 202 and gate dielectric material layer 201 mask.
Fig. 4 is refer to, etches the mask layer 300（It refer to Fig. 3）Form mask layer 301；With the mask layer 301 be gate material layers 202 described in mask etching（It refer to Fig. 3）With gate dielectric material layer 201（It refer to Fig. 3）, form grid Pole 212 and gate dielectric layer 211.
Forming the method for the mask layer 301 includes：Photoresist layer is formed on the above-mentioned surface of mask layer 300；To upper State photoresist layer and carry out development exposure, form graphical photoresist layer, the graphical photoresist layer defines what is be subsequently formed The positions and dimensions of grid structure；Using the graphical photoresist layer as mask, the mask layer 300 is etched（It refer to Fig. 3）, form mask layer 301.The mask layer 301 is as subsequent etching gate material layers 202（It refer to Fig. 3）And gate medium Material layer 201（It refer to Fig. 3）Mask.
The gate material layers 202 are etched using dry etch process（It refer to Fig. 3）With gate dielectric material layer 201（Please With reference to figure 3）, grid 212 and gate dielectric layer 211 are formed respectively, and the grid 212 and gate dielectric layer 211 form the grid of transistor Pole structure.
Fig. 5 is refer to, in the gate dielectric layer 211, grid 212, the sidewall surfaces of mask layer 301 and top silicon layer 103 Surface forms the first spacer material layer 302.
Oxidation technology or depositing operation can be used to form the first spacer material layer 302.In the present embodiment, described The material of the side walling bed of material 302 is silica, and the first spacer material layer 302 is formed using thermal oxidation technology, described The thickness of the side walling bed of material 302 is more than
The first spacer material layer 302 is subsequently used for forming the first side wall, and first side wall on the one hand can conduct The isolation structure of grid structure both sides, the damage that the grid 212 is subject in etching process can also be repaired.
In other embodiments of the invention, the material of the first spacer material layer 302 can also be silicon nitride or nitrogen Silica.
Fig. 6 is refer to, the second spacer material layer 303 is formed on the first spacer material layer 302, the surface of mask layer 301.
The second spacer material layer 303 can be formed using chemical vapor deposition method, second described in the present embodiment The material of spacer material layer 303 is silicon nitride.
Second spacer material layer 303 described in subsequent etching forms the second side wall, and second side wall is noted as ion is formed Enter to form the mask of source-drain area.
The thickness of second side wall is 1nm~200nm.
Fig. 7 is refer to, etches the second spacer material layer 302（It refer to Fig. 6）With the first spacer material layer 301, divide The second side wall 313 and the first side wall 312 are not formed.
Using the first side removed without mask etching technique positioned at the top of mask layer 301 and the surface of Portions of top layer silicon layer 103 The spacer material layer 303 of the walling bed of material 302 and second, form the second side wall 313 and the first side wall 312.
The mask film covering layer 301 of first side wall 312, grid 212, the sidewall surfaces of gate dielectric layer 211 and part are pushed up Layer silicon layer 103, second side wall 313 are located at the surface of the first side wall 312.
First side wall 313 injects the mask to form source-drain area as subsequent ion, for limiting source-drain area and grid The distance between.
Fig. 8 is refer to, on the surface of top silicon layer 103 of the grid 212, the first side wall 312 and the both sides of the second side wall 313 Form semiconductor material layer 400.
Using selective epitaxial process, the semiconductor material layer 400 is formed.In the present embodiment, the semi-conducting material The material of layer 400 be silicon, in other described examples of the invention, the material of the semiconductor material layer 400 can also be SiGe, The semi-conducting materials such as Ge.The growth rate and thickness of the semi-conducting material can be preferably controlled using selective epitaxial process Degree, the surface for the semiconductor material layer 400 for making to ultimately form are less than the surface of grid 212.
The semiconductor material layer 400 is used for the thickness for improving the semiconductor layer of the both sides of grid 212, is subsequently partly led described Source-drain area is formed in body material layer 400 and top silicon layer 103 below.The semiconductor material layer 400 improves source-drain area Thickness, so as to reduce the series resistance of the source-drain area of formation.
Fig. 9 is refer to, top silicon layer 103 to the semiconductor material layer 400 and below carries out heavy doping ion note Enter, form source-drain area 401.
It is mask with the mask layer 301, the first side wall 312, the second side wall 313, to the semiconductor material layer 400 （It refer to Fig. 8）And positioned at the semiconductor material layer 400（It refer to Fig. 8）The Portions of top layer silicon layer 103 of underface is carried out Heavy doping ion is injected to form source-drain area 401.
The type of the heavy doping ion injection is identical with the type of transistor to be formed.
Figure 10 is refer to, removes second side wall 313（It refer to Fig. 9）, form groove 314.
In the present embodiment, the second side wall 313 is removed using wet-etching technology（It refer to Fig. 9）, the wet etching Etching solution is phosphoric acid solution.In other embodiments of the invention, dry etch process can also be used to remove described second Side wall 313.
The groove 314 exposes the portion on top silicon layer 103 surface of the part between source-drain area 401 and grid 212 Second is divided to survey wall 312.
Figure 11 is refer to, to carrying out that ion note is lightly doped in the Portions of top layer silicon layer 103 of the bottom portion of groove of groove 314 Enter, form lightly doped district 402.
The ionic type that ion implanting is lightly doped is identical with the type of transistor to be formed.Make because ion spreads With part lightly doped district 402 is located at the lower section of gate dielectric layer 211.
The short-channel effect of transistor can be improved by forming the lightly doped district 402.
Figure 12 is refer to, removes the first side wall of part 312 of the bottom of groove 314 and the mask at the top of grid 212 Layer 301（It refer to Figure 11）, expose the part surface of lightly doped district 402 and the top surface of grid 212.
After the first side wall of part 312 and mask layer 301 that remove the surface of lightly doped district 402, expose and be lightly doped Area 402 and the surface of grid 212, it is easy to subsequently form metal on the surface of lightly doped district 402 and the top surface of grid 212 Silicide layer.
Figure 13 is refer to, on the source-drain area 401, part lightly doped district 402, the first side wall 312 and the surface of grid 212 Form metal level 500.
The material of metal level 500 comprises at least a kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.The present embodiment In, the material of the metal level 500 is Ni.
Evaporation or sputtering technology can be used to form the metal level 500.
Figure 14 is refer to, is formed on the surface of source-drain area 401, the surface of part lightly doped district 402 and the surface of grid 212 Metal silicide layer 501.
In the present embodiment, boiler tube or short annealing equipment are used using two step silicification technics, in high-purity nitrogen environment, Low temperature short annealing, such as 260 DEG C of reaction temperature, 30 seconds duration, form nickel-rich phase silicide；Then, carved using wet method The method of erosion, remove unnecessary Ni metal levels；Finally, using high temperature rapid thermal annealing, such as 500 DEG C of reaction temperature, duration 30 seconds, undergo phase transition nickel-rich phase silicide, in the surface of source-drain area 401, the surface of part lightly doped district 402 and the grid 212 surfaces form metal silicide layer 501.
In other embodiments of the invention, a step silicification technics can also be used：Set using boiler tube or short annealing It is standby, the high temperature rapid thermal annealing under the nitrogen environment of high-purity, directly form nickel silicide.
Because metal can only react to form metal silicide layer with silicon, the metal silicide layer 501 can only Formed on the surface of source-drain area 401, the surface of part lightly doped district 402 and the surface of grid 212.
Formed after the metal silicide layer 501, using wet etching method, remove unnecessary metal layer material.
In the present embodiment, due to the thinner thickness of the lightly doped district 402, the silicon of the lightly doped district 402 fills with metal Divide reaction, being completely transformed into metal silicide reduces the resistance of the lightly doped district 402.
Compared with prior art, in the present embodiment, metal silicide layer not only is formed on the surface of source-drain area 401, also light The surface of doped region 402 forms metal silicide layer, reduce further resistance, avoids the thinner thickness due to lightly doped district, make Into resistance it is larger the problem of, so as to improve the performance of transistor.
Figure 15 is refer to, dielectric layer 600 is formed on the surface of metal silicide layer 501, the surface of the first side wall 312.
The full groove 314 of the filling of dielectric layer 600（It refer to Figure 14）And cover the source-drain area 401, be partly lightly doped Area 402, the metal silicide layer 501 on the surface of grid 212.Interlayer dielectric layer of the dielectric layer 600 as transistor surface, after It is continuous that metal plug can be formed in the dielectric layer 600, connect the source-drain area 401 and grid 212 of transistor.
The material of the dielectric layer 600 is low-K dielectric material, is gathered including at least carborundum, silicon oxide carbide, organosiloxane One kind in compound, fluorocarbons.The K values of the low-K dielectric material are relatively low, can effectively reduce grid 211 and source-drain area Parasitic capacitance between 401, the operating rate of transistor is improved, improve the performance of transistor.In the present embodiment, the dielectric layer 600 material is carborundum, and the dielectric layer 600 is formed using chemical vapor deposition method.
The present embodiment also provides a kind of transistor formed using the above method.
Figure 15 is refer to, is the structural representation of the transistor.
The transistor includes：Semiconductor substrate, in the present embodiment, the Semiconductor substrate is silicon-on-insulator（SOI） Substrate, the Semiconductor substrate include bottom silicon layer 101, the insulating barrier 102 positioned at bottom silicon surface, positioned at insulating barrier 102 The top silicon layer 103 on surface；
Grid structure positioned at the surface of top silicon layer 103 of Semiconductor substrate, the grid structure include gate dielectric layer 211 With grid 212, the gate structure sidewall surface has the first side wall 312；
Source-drain area 401 in the Semiconductor substrate of the grid structure and the both sides of the first side wall 312, the source and drain There is groove, the surface of the source-drain area 401 is higher than the surface of Semiconductor substrate and low between the side wall 312 of area 401 and first In grid structure surface；
Lightly doped district in the Semiconductor substrate of bottom portion of groove between the side wall 312 of source-drain area 401 and first 402；
Metal silicide layer 501 positioned at the surface of source-drain area 401, the surface of lightly doped district 402 of bottom portion of groove.
In the present embodiment, the material of the lightly doped district 402 of the bottom portion of groove is metal silicide, the grid structure top Portion also has metal silicide layer 501.
In the present embodiment, the transistor is also included positioned at the surface of metal silicide layer 501, the table of the first side wall 312 Face and the dielectric layer 600 for filling the full groove, the material of the dielectric layer is low-K dielectric material, is comprised at least：Carborundum, One kind in silicon oxide carbide, organic siloxane polymer, fluorocarbons.
The source-drain area 401 for the transistor that the present embodiment provides and the surface of lightly doped district 402 are each formed with metal silicide layer, Source-drain area and the resistance of lightly doped district can be reduced simultaneously, improve the performance of transistor.Also, the grid structure and source-drain area Between be filled with low K dielectric layer, the parasitic capacitance between the grid and source-drain area can be reduced, improve transistor operation speed Rate, improve the performance of transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (15)

  1. A kind of 1. forming method of transistor, it is characterised in that including：
    Semiconductor substrate is provided, the Semiconductor substrate is silicon-on-insulator；
    Grid structure is formed in the semiconductor substrate surface, there is mask layer at the top of the grid structure；
    The grid structure and mask layer both sides sidewall surfaces formed the first side wall and positioned at the first side wall surface the Two side walls；
    Semiconductor substrate surface in the grid structure both sides forms semiconductor material layer, the surface of the semiconductor material layer Less than the surface of grid structure；
    Ion implanting is carried out to the semiconductor material layer, forms source-drain area；
    Second side wall is removed, groove is formed between the source-drain area and the first side wall；
    The Semiconductor substrate of the bottom portion of groove is carried out that ion implanting is lightly doped, forms lightly doped district；
    The mask layer at the top of the side wall of part first and grid structure of bottom portion of groove is removed, exposes the part table of lightly doped district Face and the top surface of grid structure；
    Metal silicide layer is formed on the lightly doped district surface of the source-drain area surface, bottom portion of groove.
  2. 2. the forming method of transistor according to claim 1, it is characterised in that the material of the mask layer is oxidation Silicon.
  3. 3. the forming method of transistor according to claim 1, it is characterised in that first side wall and the second side wall Material differs.
  4. 4. the forming method of transistor according to claim 3, it is characterised in that the material of first side wall is oxidation Silicon, the thickness of first side wall are more than
  5. 5. the forming method of transistor according to claim 4, it is characterised in that the material of second side wall is nitridation Silicon or silicon oxynitride.
  6. 6. the forming method of transistor according to claim 1, it is characterised in that the material of the semiconductor material layer is Silicon, germanium or SiGe.
  7. 7. the forming method of transistor according to claim 6, it is characterised in that using selective epitaxial process, formed The semiconductor material layer.
  8. 8. the forming method of transistor according to claim 1, it is characterised in that the grid structure, which includes being located at, partly leads The gate dielectric layer of body substrate surface and the grid positioned at the gate dielectric layer surface, the material of the gate dielectric layer is silica, The material of the grid is polysilicon.
  9. 9. the forming method of transistor according to claim 8, it is characterised in that be additionally included at the top of grid structure also shape Into metal silicide layer.
  10. 10. the forming method of transistor according to claim 9, it is characterised in that form the side of the metal silicide Method includes：Surface at the top of the source-drain area, the lightly doped district of bottom portion of groove, the first side wall and grid structure forms metal Layer；Made annealing treatment, in the source-drain area surface, the lightly doped district surface of bottom portion of groove and grid structure top surface shape Into metal silicide layer；Remove remaining metal level.
  11. 11. the forming method of transistor according to claim 10, it is characterised in that the material of metal level comprises at least A kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.
  12. 12. the forming method of transistor according to claim 11, it is characterised in that the lightly doped district of the bottom portion of groove It is fully converted to metal silicide.
  13. 13. the forming method of transistor according to claim 1, it is characterised in that also include：In the metal silicide Layer surface, the first side wall surface form dielectric layer.
  14. 14. the forming method of transistor according to claim 13, it is characterised in that the material of the dielectric layer is low K Dielectric material.
  15. 15. the forming method of transistor according to claim 14, it is characterised in that the material of the dielectric layer at least wraps Include：One kind in carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.
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CN107346730B (en) * 2016-05-05 2019-09-27 中芯国际集成电路制造(上海)有限公司 Improve the method for performance of semiconductor device
CN112928153B (en) * 2019-12-05 2023-07-04 中芯国际集成电路制造（天津）有限公司 Semiconductor structure and forming method thereof
CN113539809B (en) * 2021-07-19 2023-07-04 长鑫存储技术有限公司 Method for preparing semiconductor structure and semiconductor structure
CN113937005A (en) * 2021-12-16 2022-01-14 广州粤芯半导体技术有限公司 Method for manufacturing metal oxide semiconductor transistor

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US6248637B1 (en) * 1999-09-24 2001-06-19 Advanced Micro Devices, Inc. Process for manufacturing MOS Transistors having elevated source and drain regions
US6316303B1 (en) * 2000-01-11 2001-11-13 United Microelectronics Corp. Method of fabricating a MOS transistor having SEG silicon
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains

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KR101812036B1 (en) * 2011-01-06 2017-12-26 삼성전자 주식회사 Semiconductor device including metal silicide layer and fabrication method thereof

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US6248637B1 (en) * 1999-09-24 2001-06-19 Advanced Micro Devices, Inc. Process for manufacturing MOS Transistors having elevated source and drain regions
US6316303B1 (en) * 2000-01-11 2001-11-13 United Microelectronics Corp. Method of fabricating a MOS transistor having SEG silicon
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains

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