CN104465315B - The chip separation method of 3D Stacked Die Packaging devices - Google Patents
The chip separation method of 3D Stacked Die Packaging devices Download PDFInfo
- Publication number
- CN104465315B CN104465315B CN201310439837.1A CN201310439837A CN104465315B CN 104465315 B CN104465315 B CN 104465315B CN 201310439837 A CN201310439837 A CN 201310439837A CN 104465315 B CN104465315 B CN 104465315B
- Authority
- CN
- China
- Prior art keywords
- chip
- grinding
- stacked die
- separation method
- abrasive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 30
- 238000000926 separation method Methods 0.000 title claims abstract description 23
- 238000000227 grinding Methods 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000000126 substance Substances 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 13
- 230000007797 corrosion Effects 0.000 claims abstract description 9
- 238000005260 corrosion Methods 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims abstract description 6
- 239000012943 hotmelt Substances 0.000 claims abstract description 6
- 238000003801 milling Methods 0.000 claims description 9
- 238000012544 monitoring process Methods 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 40
- 239000011230 binding agent Substances 0.000 abstract description 3
- 238000005259 measurement Methods 0.000 abstract description 2
- 238000004458 analytical method Methods 0.000 description 8
- 239000000523 sample Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 239000004033 plastic Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005088 metallography Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 dress Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Sampling And Sample Adjustment (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of chip separation method of 3D Stacked Die Packagings device, comprises the steps：The internal structure of the micro- detection 3D Stacked Die Packaging ULSI samples of acoustic scan, it is determined that required abrasive areas and its area；3D Stacked Die Packaging ULSI samples are fixed on grinding table with hot melt wax；Grinding：According to the area of above-mentioned abrasive areas, abrasive drill, grinding dynamics and grinding direction are selected, encapsulating material and chip is removed, is ground to the protective layer of objective chip surface covering；Using chemical corrosion method, above-mentioned protective layer is removed.The present invention is based on grinding, supplemented by chemical attack；Grinding needle is removed to specific localized areas, does not damage lower layer chip internal structure and its bonding wire；The protective layer covered on objective chip surface or chip binding agent are removed by chemical corrosion method, objective chip exposure；Bonding wire in the objective chip internal structure and chip of gained is not completely damaged, and facilitates follow-up electrical measurement to analyze.
Description
Technical field
The present invention relates to chip separation method, more particularly to a kind of chip separation side of 3D Stacked Die Packagings device
Method.
Background technology
3D Stacked Die Packaging technologies realize multichip interconnection using solid space, in the premise for not changing package body sizes
Under, two are stacked using the mode such as wire bonding or through-silicon-via TSV interconnection in vertical direction in vivo in same encapsulation
Or more chip.3D Stacked Die Packaging super large-scale integration（ULSI）While circuit performance is improved, greatly drop
The low power consumption of circuit, becomes the new lover of high performance device.
At present, for brand-new 3D ULSI products, sometimes by destructive physical analysis, its internal structure is checked,
This needs successively to expose the multilayer chiop inside 3D ULSI, and the internal structure to each layer carries out interior visual inspection, to verify which
Whether internal material, design and structure meet applicable design document requirement or other regulations are required.
And the 3D ULSI to using and occurring to fail, need first with defect location technological orientation to defect concrete
Which layer chip, then this layer of chip is come out carry out physical analysis, morphology observation analysis and failure machine are carried out to rejected region
Reason confirms.When defect is on top layer chip, the separation method of ULSI is encapsulated using one chip, i.e., by traditional chemistry
The corrosive liquids such as etch nitric acid are realized removing to the corrosiveness of plastic encapsulant, or by mechanical Kaifeng method file
Or ceramics or Metal Packaging cover plate are levered up and are removed by small milling machine.Both sample treatments can realize plastic seal
The removal of various encapsulating materials such as dress, ceramic package, packed by metal casing；But 3D Stacked Die Packaging ULSI contain two or with
Upper chip, when defect is on non-top layer chip, in addition to the encapsulating material for getting rid of ULSI, also needs on objective chip
Other chips are gone divided by exposing objective chip and be analyzed；In addition, 3D Stacked Die Packaging ULSI are in addition to encapsulating material,
There are other chips and chip chamber binding agent.And, after the non-top layer chip of 3D ULSI comes out, it may be necessary to carry out
Defect location again.The existing Detection Techniques for chip-scale defect, such as mechanical probes, light transmitting microtechnic, red
Outer thermal imagery method, liquid crystal Method, electron beam tester etc., are required to device plus certain voltage bias to reappear failure phenomenon, this
Require that the electrical property of device is good.Therefore, when the 3D Stacked Die Packagings ULSI to failing carries out non-top layer chip exposure, must
Must ensure while encapsulating material, upper strata chip etc. is removed, it is ensured that the electrical property of objective chip layer is good, i.e. objective chip layer
Internal structure, the bonding welding pad on chip, bonding wire etc. all intact must not be damaged.
As chip material is silicon（Si）, it is impossible to removed with chemical corrosion method, even using hydrofluoric acid（HF）Immersion, also not
Can be by its erosion removal.And mechanical Kaifeng method is mainly used for the Kaifeng of ceramic cover plate encapsulation or metal-back packaging, lead to
Package casing material is removed by the method that overground or sled combines, and exposes encapsulation inner chamber, but the method cannot be in package cavity body
Chip carry out Local treatment and reserved lead it is lossless.
Therefore, traditional chemical attack or mechanical Kaifeng method cannot meet the non-top layer chip things of 3D Stacked Die Packaging ULSI
The demand of reason analysis.How the chip on objective chip to be removed, be 3D Stacked Die Packagings ULSI failure analyses/physics point
The thorny problem run into during analysis.
The content of the invention
Based on this, it is an object of the invention to provide a kind of chip separation method of 3D Stacked Die Packagings device.
The concrete technical scheme for solving above-mentioned technical problem is as follows：
A kind of chip separation method of 3D Stacked Die Packagings device, comprises the steps：
（1）Determine abrasive areas and its area
The internal structure of the micro- detection 3D Stacked Die Packaging ULSI samples of acoustic scan, the such as chip layer of device inside
Number, chip area size, and determine abrasive areas and its area；
（2）It is fixed
3D Stacked Die Packaging ULSI samples are fixed on grinding table with hot melt wax；
（3）Grinding
According to step（1）Determined by abrasive areas and its area, select abrasive drill, grinding dynamics, depth and speed,
The encapsulating material and chip of abrasive areas are removed, the protective layer of objective chip surface covering is ground to；In the grinding：If grinding
Area is 3-6mm, and abrasive drill is 1mm, if milling area be 7-15mm, abrasive drill is 3mm, if milling area be more than
15mm, abrasive drill are 5mm；
（4）Chemical attack
Using chemical corrosion method, removal step（3）Described protective layer.
Wherein in some embodiments, step（3）
It is wherein in some embodiments, described to be ground to step-by-step movement grinding, i.e. stepping applying grinding dynamics, for same
Material, when initial, dynamics is larger, example：The 1/4-1/2 of total grinding thickness is ground once, with the carrying out of grinding, dynamics gradually subtracts
It is few.Grinding dynamics refers to and arrange the thickness of grinding downwards and apply corresponding power by dialing knob；Grinding dynamics is determined often
The thickness that secondary grinding is removed.
Wherein in some embodiments, step（3）Described grinding dynamics is step（3）The grinding direction is：XY side
To or X-direction or Y-direction.
Wherein in some embodiments, step（2）Described fixation and step（3）Also include calibration in described grinding：
The calibration is the thickness by measuring difference on abrasive areas surface, while the height of grinding table is adjusted, to adjust grinding
The flatness in face.
Wherein in some embodiments, the chemical corrosion method is：Corroded using the concentrated sulfuric acid.
Wherein in some embodiments, also including monitoring：Using metallographic microscope monitoring step（3）The grinding and step
（4）The progress of the chemical attack.
A kind of chip separation method of 3D Stacked Die Packagings device of the present invention has the advantage that and beneficial effect
Really：
（1）In chip separation method of the present invention, based on grinding technique, supplemented by chemical corrosion method；It is main to utilize
Region sample preparation grinding technique realizes micron-sized region grinding, can be deep into encapsulation inside cavity, for specific localized areas
（Such as the upper area only to chip area size）De-layer is ground, certain layer of chip and encapsulating material is being removed, while not damaging
Hinder lower layer chip internal structure and its bonding wire；Wherein, in the grinding：If milling area is 3-6mm, abrasive drill is
1mm, if milling area is 7-15mm, abrasive drill is 3mm, if milling area is more than 15mm, abrasive drill is 5mm；It is auxiliary again
The protective layer covered on objective chip surface or chip binding agent are removed with chemical corrosion method, make objective chip surface clearly sudden and violent
Expose；The objective chip for being come out, the bonding wire in internal structure and chip etc. are not completely damaged, i.e., electrical property is good
Good, the convenient electrical measurement subsequently to this layer of chip is analyzed；
（2）In chip separation method of the present invention, the method for fixing sample using hot melt wax is avoided and adopts fixture
When being fixedly clamped to encapsulate that inside chip causes be forced to rupture or warpage is damaged, when making grinding, the thickness of sample, size be not
It is constrained；
（3）In chip separation method of the present invention, using multiple spot thickness measure, coordinate the calibration side of adjustment grinding table
Method makes lapped face smooth, it is to avoid unnecessary inclination grinding damage.
（4）In chip separation method of the present invention, also using metallography microscope sem observation each material in process of lapping
In color change with realize real-time monitoring grinding progress, accordingly adjust grinding dynamics, not only broken away to sample size according to
Rely, also further ensure that the size of abrasive areas, depth are controllable, it is to avoid overmastication or grinding are not enough；
（5）Chip separation method of the present invention realizes 3D Stacked Die Packaging device insides multilayer chiop successively
Exposure, solves the problems, such as that the non-top layer chip makes physical analysis of 3D Stacked Die Packaging devices is difficult, can also make some 3D laminated chips
The failure analysis of the ineffective part of encapsulation is smoothly completed, and determines its final failure cause and mechanism, prevents the weight for failing
Appear again existing, the reliability to improving device is significant.
Description of the drawings
Fig. 1 is the techniqueflow chart of the memory chips separation method described in embodiment 1；
Fig. 2 is the internal structure schematic diagram of the memory described in embodiment 1；Wherein, 1 is ground floor chip, and 2 is the second layer
Chip；
Local pattern metallographic microscope figures of the Fig. 3 for second layer chip in the memory described in embodiment 1；
Fig. 4 is second layer chip local pattern and lead pattern metallographic microscope figure in the memory described in embodiment 1.
Specific embodiment
Below with reference to specific embodiment, the present invention will be further described.
Wherein, the micro- detection of acoustic scan described in following embodiments refers to ultrasonic scanning microscope, abbreviation C-SAM；
ALLIED companies of the U.S. of the hot melt wax manufacturer.
Embodiment 1
The present embodiment is including two chips of NAND Flash+Mobile SDRAM（Layers of chips adopts cross type
Refracting films）Memory as a example by, obtain second layer chip by separating, its separation method comprises the steps（Techniqueflow
Figure is referring to Fig. 1）：
（1）Determine abrasive areas and its area
The micro- detection of acoustic scan（C-SAM）The internal structure of memory, as shown in Fig. 2 memory is cross type
Bilateral lead packages, wherein, 1 is ground floor chip, and 2 is second layer chip；Determine abrasive areas for encapsulating material and 1 first
Layer chip, area is 8mm；Memory original depth is measured simultaneously is about 1mm, rule of thumb, the encapsulating material of the usual the superiors
The 1/3 of memory gross thickness is accounted for, this provides reference for grinding dynamics when encapsulating material is ground in follow-up grinding steps；
（2）It is fixed
Memory sample is fixed on grinding table with hot wax melting；Can flow as hot melt wax is heated, may make during cooling
Into the out-of-flatness of device surface, by the thickness for measuring difference chip on abrasive areas surface, while coordinate adjusting grinding table
Height, to adjust the flatness of abradant surface.
（3）Grinding
According to step（1）The abrasive areas and its area, select abrasive drill 3mm, metallographic microscope monitoring grind into
Degree, while being ground using step-by-step movement, initial grinding dynamics is set to 100 μm of grinding downwards, carries out from two directions of grinding direction X, Y
Grinding, removes the upper strata chip of encapsulating material and second layer chip, is ground to the protective layer of second layer chip surface covering, i.e., thoroughly
Cross the protective layer transparent material to can be observed to stop grinding during this layer of chip internal structure；In process of lapping, according to metallography microscope
The memory inside material color of mirror monitoring, pattern change, observe the process of grinding, and adjust grinding dynamics, for same
Material, grinding dynamics are gradually decreased.The plastic packaging material not being ground is in black, and the plastic packaging material color being ground is in light gray, and
Pattern is careful.Silicon chip before not being ground, in light mirror-like.After being ground, color is formed after grinding in light gray
Pattern can be significantly coarse.When upper strata silicon chip is ground to very thin one layer, the interior of lower layer chip can be seen through the thin layer
Portion's structure.Continue grinding, it can be seen that the protective layer on second layer chip（Usually polyimides）, in orange-yellow transparence, thoroughly
The protective layer is crossed, the internal structure of lower layer chip can be more clearly seen.
（4）Chemical attack
Using concentrated sulfuric acid removal step（3）The protective layer that described second layer chip surface is covered（Usually polyamides is sub-
Amine）, you can expose the second layer chip surface of complete display.Device is carefully detected by metallographic microscope, second layer core is observed
Bonding wire on the internal structure of piece, chip, as a result referring to Fig. 3 and Fig. 4, wherein, local patterns of the Fig. 3 for second layer chip
Figure, Fig. 4 are second layer chip local pattern and lead shape appearance figure.
Knowable to Fig. 3 and Fig. 4：Using separation method of the present invention, the bonding of the separated objective chip for obtaining draws
Line is completely intact, and the internal structure and its bonding wire of lower layer chip are completely intact.
If objective chip is the third layer of other 3D Stacked Die Packaging devices, the chip such as the 4th layer, repeat above-mentioned
Grind and steps of chemical attack is to remove the chip of more lower.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more concrete and detailed, but and
Therefore the restriction to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, some deformations and improvement can also be made, these belong to the guarantor of the present invention
Shield scope.Therefore, the protection domain of patent of the present invention should be defined by claims.
Claims (6)
1. a kind of chip separation method of 3D Stacked Die Packagings device, it is characterised in that comprise the steps：
(1) abrasive areas and its area are determined：
The internal structure of the micro- detection 3D Stacked Die Packaging ULSI samples of acoustic scan, determines abrasive areas and its area；
(2) it is fixed：
3D Stacked Die Packaging ULSI samples are fixed on grinding table with hot melt wax；
(3) grind：
Abrasive areas and its area according to determined by step (1), select abrasive drill, grinding dynamics and grinding direction, remove
The encapsulating material and chip of abrasive areas, is ground to the protective layer of objective chip surface covering；In the grinding：If milling area
For 3-6mm2, abrasive drill is 1mm, if milling area is 7-15mm2, abrasive drill is 3mm, if milling area be more than
15mm2, abrasive drill is 5mm；
(4) chemical attack：
Using chemical corrosion method, the protective layer described in removal step (3).
2. the chip separation method of 3D Stacked Die Packagings device according to claim 1, it is characterised in that step (3)
It is described to be ground to step-by-step movement grinding.
3. the chip separation method of 3D Stacked Die Packagings device according to claim 1, it is characterised in that step (3)
The grinding direction is：XY directions or X-direction or Y-direction.
4. the chip separation method of 3D Stacked Die Packagings device according to claim 1, it is characterised in that step (4)
The chemical corrosion method is：The concentrated sulfuric acid corrodes.
5. the chip separation method of 3D Stacked Die Packagings device according to claim 1, it is characterised in that step (2)
Also include calibration in grinding described in described fixation and step (3)：The calibration is by measuring on abrasive areas surface not
With the thickness of point, while the height of grinding table is adjusted, to adjust the flatness of abradant surface.
6. the chip separation method of the 3D Stacked Die Packaging devices according to any one of claim 1-5, it is characterised in that
Also include monitoring：Using metallographic microscope monitoring step (3) grinding and the progress of step (4) chemical attack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310439837.1A CN104465315B (en) | 2013-09-24 | 2013-09-24 | The chip separation method of 3D Stacked Die Packaging devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310439837.1A CN104465315B (en) | 2013-09-24 | 2013-09-24 | The chip separation method of 3D Stacked Die Packaging devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465315A CN104465315A (en) | 2015-03-25 |
| CN104465315B true CN104465315B (en) | 2017-04-05 |
Family
ID=52911193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310439837.1A Active CN104465315B (en) | 2013-09-24 | 2013-09-24 | The chip separation method of 3D Stacked Die Packaging devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465315B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105842611B (en) * | 2016-03-31 | 2018-11-30 | 工业和信息化部电子第五研究所 | The preparation method of flip-chip test sample |
| CN107244648B (en) * | 2017-05-08 | 2020-01-31 | 中国电子产品可靠性与环境试验研究所 | Unsealing method of chip-stacked plastic-packaged MEMS inertial device |
| CN109950156A (en) * | 2017-12-20 | 2019-06-28 | 海太半导体（无锡）有限公司 | Chip flip-chip unsealing method |
| CN112179915B (en) * | 2019-07-04 | 2024-07-05 | 深圳长城开发科技股份有限公司 | Hierarchical removing method for positioning damage points inside bare chip |
| CN110587385B (en) * | 2019-09-30 | 2021-08-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for thinning flip chip on circuit board, grinding drill bit and fixed base |
| CN111579555A (en) * | 2020-04-02 | 2020-08-25 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Structure detection method of SiP module |
| CN111710627B (en) * | 2020-05-28 | 2024-03-01 | 北京芯可鉴科技有限公司 | Chip packaging pretreatment method and chip analysis method |
| CN111883453B (en) * | 2020-08-28 | 2021-11-12 | 长江存储科技有限责任公司 | Wafer obtaining method and semiconductor device failure analysis method |
| CN114496824A (en) * | 2020-10-23 | 2022-05-13 | 长鑫存储技术有限公司 | Bare chip taking-out method |
| US11686765B2 (en) | 2020-10-23 | 2023-06-27 | Changxin Memory Technologies, Inc. | Die extraction method |
| CN113013021A (en) * | 2021-03-01 | 2021-06-22 | 长江存储科技有限责任公司 | Unsealing method of semiconductor packaging structure |
| CN113702807A (en) * | 2021-08-25 | 2021-11-26 | 长鑫存储技术有限公司 | Chip carrier and chip detection device |
| CN114487788A (en) * | 2022-04-02 | 2022-05-13 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Failure positioning method of packaging device |
| CN114927408B (en) * | 2022-05-19 | 2023-03-24 | 深圳市东方聚成科技有限公司 | Nondestructive chip separation and packaging test recycling method for electronic device |
| CN115031855B (en) * | 2022-06-13 | 2023-09-19 | 北京智创芯源科技有限公司 | Manufacturing method of infrared detector and blind pixel processing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254440A (en) * | 1997-05-02 | 2000-05-24 | Memc电子材料有限公司 | Method for etching silicon wafer |
| CN101197268A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating leftover after chemical mechanical grinding |
| CN102044405A (en) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Chip separation method in multi-chip pack |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2796758B1 (en) * | 1999-07-22 | 2003-02-14 | France Telecom | PROCESS FOR CORRECTION OF TOPOGRAPHIC EFFECTS ON MICRO-ELECTRONIC SUBSTRATE |
| TWI324801B (en) * | 2007-02-05 | 2010-05-11 | Touch Micro System Tech | Method of protecting front surface structure of wafer and dividing wafer |
-
2013
- 2013-09-24 CN CN201310439837.1A patent/CN104465315B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254440A (en) * | 1997-05-02 | 2000-05-24 | Memc电子材料有限公司 | Method for etching silicon wafer |
| CN101197268A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating leftover after chemical mechanical grinding |
| CN102044405A (en) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Chip separation method in multi-chip pack |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465315A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104465315B (en) | The chip separation method of 3D Stacked Die Packaging devices | |
| CN105842611B (en) | The preparation method of flip-chip test sample | |
| CN104008956B (en) | Opening method for flip chip devices | |
| CN108493123B (en) | Preparation method for taking bare chip from flip chip and failure analysis method | |
| CN105070668B (en) | A kind of wafer stage chip encapsulation method | |
| CN101769876A (en) | Method for carrying out failure analysis in semiconductor device | |
| CN102810492B (en) | Process monitoring method after metal gate CMP | |
| CN103969569A (en) | Preparation method and analytical method for back optical failure positioning sample of integrated circuit | |
| CN106356312A (en) | Testing and failure analysis method for packaged chip | |
| JP2008218565A (en) | Semiconductor device, appearance inspection method, and appearance inspection apparatus | |
| TW201513236A (en) | Mold flash cleaning method for QFN package | |
| CN105206506B (en) | The processing method of wafer | |
| KR20200137971A (en) | Method for manufacturing wafer and method for manufacturing stacked device chip | |
| US9728440B2 (en) | Non-transparent microelectronic grade glass as a substrate, temporary carrier or wafer | |
| CN104215482A (en) | Preparation method of failure analysis sample | |
| JP5748198B2 (en) | Manufacturing method of laminated device and laminated device | |
| Wang et al. | 300-mm Low-${\hbox {k}} $ Wafer Dicing Saw Development | |
| Kor et al. | Sample preparation for deprocessing of 3D multi-die stacked package | |
| CN109883365A (en) | The judgment method of crystal grain layer method for measuring thickness and crystal grain layer exception | |
| Alapati et al. | TSV metrology and inspection challenges | |
| Wong et al. | A novel x-ray diffraction technique for analysis of die stress inside fully encapsulated packaged chips | |
| Li et al. | A study on the relationship between pad surface fluorine concentration and the formation of pad corrosion defect | |
| US20230034412A1 (en) | Wafer structure and manufacturing method thereof | |
| WO2022083185A1 (en) | Die taking-out method | |
| Thomas et al. | SAM??: New Failure Analysis Methods for Heterogeneous Systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |