CN104425395A - Semiconductor packaging part and manufacturing method thereof - Google Patents
Semiconductor packaging part and manufacturing method thereof Download PDFInfo
- Publication number
- CN104425395A CN104425395A CN201310364137.0A CN201310364137A CN104425395A CN 104425395 A CN104425395 A CN 104425395A CN 201310364137 A CN201310364137 A CN 201310364137A CN 104425395 A CN104425395 A CN 104425395A
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- Prior art keywords
- chip
- cladding
- lateral surface
- electrical contact
- contact
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Abstract
Disclosed are a semiconductor packaging part and a manufacturing method thereof. The semiconductor packaging part includes a chip, electrical connection points, a first cladding body and a second cladding body. The chip is provided with an outer side face. The electrical connection points are formed on the chip. The first cladding body wraps a first part at the outer side face of the chip. The second cladding body wraps a second part on the outer side face of the chip and part of the electrical connection points. The first cladding body directly contacts the second cladding body on the outer side face of the chip.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to a kind of semiconductor package part and the manufacture method thereof with cladding especially.
Background technology
Conventional semiconductor package part comprises chip and several defeated in/out contact.Defeated in/out contact is such as soldered ball, and it is formed on the active surface of chip.Semiconductor package part is electrically connected by soldered ball and the external circuit board.But because chip structure is more and more thinner and increasing, when semiconductor package part is located on circuit board in process, chip easily chaps.
Summary of the invention
The invention relates to a kind of semiconductor package part and manufacture method thereof, the problem that be full of cracks occurs semiconductor package part can be improved.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a chip, an electrical contact, one first cladding and one second cladding.Chip has a lateral surface.Electrical contact is formed on chip.One Part I of the lateral surface of the first cladding coating chip.One Part II of the lateral surface of the second cladding coating chip and part electrical contact.First cladding directly contacts with the lateral surface of the second cladding in chip.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.There is provided a chip, chip has a lateral surface; Heavy cloth chip is pasted on film in a support plate, and a Part II of the lateral surface of chip is absorbed in support plate and pastes in film; Form the Part I that one first cladding covers the lateral surface of chip; Remove support plate and paste film, with exposed chip; Form an electrical contact on chip; Arrange a contact and paste film covering electrical contact, part electrical contact is absorbed in contact and pastes in film; And the Part II and the electrical contact that form the lateral surface of one second cladding covering chip are not subject to the part that contact pastes film covering, and wherein the first cladding directly contacts with the lateral surface of the second cladding in chip.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Fig. 2 illustrates the graph of a relation of the characteristic of the semiconductor package part of Fig. 1 and the exposed portion of electrical contact.
Fig. 3 A to 3H illustrates the process drawing of the semiconductor package part of Fig. 1.
Main element symbol description:
10: bed die
20: mold
100: semiconductor package part
110: chip
110s, 112s, 1131s, 1133s, 114s, 130s, 140s: lateral surface
111: connection pad
112: protective layer
113: redistribution layer
1131: the first dielectric layers
1132: line layer
1133: the second dielectric layers
1133u, 130u: upper surface
1131a, 1133a: perforate
110a: active surface
110b: the back side
110s1: Part I
110s2: Part II
114: silicon substrate
120: electrical contact
121: exposed portion
122: covered section
123: end
130: the first claddings
140: the second claddings
140b: lower surface
140 ': the second clad material
140u: concave curvature
141: resin
142: particle filled composite
200: support plate pastes film
300: contact pastes film
300b: protrude curved surface
C1, C2: curve
H: highly
H, hs: highly
S: spacing
SP1: angular space
T: thickness
Embodiment
Please refer to Fig. 1, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises chip 110, at least one electrical contact 120, first cladding 130 and the second cladding 140.
Chip 110 has relative active surface 110a, back side 110b and lateral surface 110s.Chip 110 comprises at least one connection pad 111, protective layer 112 and redistribution layer 113, and connection pad 111 is positioned at active surface 110a.
Protective layer 112 is such as inorganic protective layer, and it covers the active surface 110a of chip 110 and exposes connection pad 111.
Redistribution layer 113 comprises the first dielectric layer 1131, line layer 1132 and the second dielectric layer 1133.First dielectric layer 1131 protective mulch 112 also has at least one perforate 1131a and exposes connection pad 111, makes line layer 1132 be electrically connected at the connection pad 111 exposed by perforate 1131a.Second dielectric layer 1133 covers a part for line layer 1132 and has another part that at least one perforate 1133a exposes line layer 1132, makes electrical contact 120 can be formed on another part exposed of line layer 1132, to be electrically connected line layer.First dielectric layer 1131 and the second dielectric layer 1133 can by polyimides (Polyimide, PI) or polybenzoxazoles (Polybenzoxozoles, PBO), and benzocyclobutene (Benzocyclobutene, BCB) is made.First dielectric layer 1131 can be identical or different with the material of the second dielectric layer 1133.
Electrical contact 120 is such as solder projection, and it is electrically connected at connection pad 111 by redistribution layer 113.
The back side 110b of the first cladding 130 coating chip 110 and Part I 110s1 of lateral surface 110s.In the present embodiment, Part I 110s1 comprises a part of the lateral surface 1131s of the lateral surface 114s of silicon substrate 114, the whole lateral surface 112s of protective layer 112 and the first dielectric layer 1131.In another example, Part I 110s1 comprises a part of the whole lateral surface 114s of silicon substrate 114 and the lateral surface 112s of protective layer 112; Or Part I 110s1 comprises the portions of lateral side 1133s of whole lateral surface 114s, the whole lateral surface 112s of protective layer 112 of silicon substrate 114, the whole lateral surface 1131s of the first dielectric layer 1131 and the second dielectric layer 1133.
The Part II 110s2 of the second cladding 140 coated upper surface 1133u of the second dielectric layer 1133 and lateral surface 110s of chip 110.In the present embodiment, Part II 110s2 comprises a part of the lateral surface 1131s of the first dielectric layer 1131 and the whole lateral surface 1133s of the second dielectric layer 1133.In another example, Part II 110s2 comprises the whole lateral surface 1133s of a part of the lateral surface 112s of protective layer 112, the whole lateral surface 1131s of the first dielectric layer 1131 and the second dielectric layer 1133; Or Part II 110s2 comprises a part of the lateral surface 1133s of the second dielectric layer 1133.
As mentioned above, the Part I 110s1 of the lateral surface 110s of the first cladding 130 and the second cladding 140 difference coating chip 110 and Part II 110s2, and the first cladding 130 directly contacts with the lateral surface 110s part of the second cladding 140 in chip 110; Specifically, the first cladding 130 has a upper surface 130u, and the second cladding 140 has a lower surface 140b, and wherein the upper surface 130u of the first cladding 130 directly contacts with the lower surface 140b of the second cladding 140.In the present embodiment, upper surface 130u and lower surface 140b directly contact in the lateral surface 1131s part of the first dielectric layer; In another example, upper surface 130u directly can contact in the lateral surface 1133s part of the second dielectric layer 1133 with lower surface 140b; Or upper surface 130u directly can contact in the lateral surface 112s part of protective layer 112 with lower surface 140.
In addition, the first cladding 130 thickness T of covering the back side 110b of chip 110 between about 100 microns to 200 microns between.If when thickness T is excessive, easily because the thermal coefficient of expansion between chip 110 with the first cladding 130 does not mate (CTE mismatch), and warpage (warpage) is caused to produce; If when thickness T is too small, easily because pressing control is improper, such as glue amount is very few or power is excessive, causes the die face of stamper mould (not illustrating) to touch chip 110, causes chip 110 to damage.
First cladding 130 can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.First cladding 130 also can comprise suitable filler, such as, be the silicon dioxide of powdery.Several encapsulation technologies can be utilized to form the first cladding 130, such as, be compression forming (compression molding), liquid encapsulation type (liquidencapsulation), injection moulding (injection molding) or metaideophone shaping (transfer molding).First cladding 130 can be identical or different with the material of the second cladding 140.
Second cladding 140 comprises the resin 141 of mixing and several particle filled composite 142.When particle filled composite 142 accounts for the ratio of the second cladding 140 the more, then the intensity of the second cladding 140 is higher and thermal coefficient of expansion is lower, but viscosity increases.Viscosity is larger, then the second cladding 140 more difficulty insert between two electrical contacts 120.Particle filled composite 142 due to the present embodiment accounts for the ratio of the second cladding 140 between 65% to 75%, can obtain high strength, thermal coefficient of expansion close to chip 110 and viscosity control to insert the second cladding 140 between two electrical contacts 120 smoothly.
With regard to the viscosity of the second cladding 140, when the ratio that particle filled composite 142 accounts for the second cladding 140 is between 65% to 75% time, the viscosity of the second cladding 140 is between 100Pas and 500Pas, and this viscosity can allow the second cladding 140 successfully insert space between adjacent two electrical contacts 120.。
With regard to the intensity of the second cladding 140, when the ratio that particle filled composite 142 accounts for the second cladding 140 is between 65% to 75% time, the young's modulus of the second cladding 140 between 10Gpa to 13Gpa, the intensity that the young's modulus of this scope provides the second cladding 140 enough.
With regard to the thermal coefficient of expansion of the second cladding 140, when the ratio that particle filled composite 142 accounts for the second cladding 140 is between 65% to 75% time, high-temperature heat expansion coefficient (temperature is higher than the thermal coefficient of expansion of the glass transition temperature of the second cladding 140) is between about between 16ppm to 27ppm, and the high-temperature heat expansion coefficient of this scope contributes to the reliability improving semiconductor package part 100.
With regard to the size of particle filled composite 142, the size of particle filled composite 142 is less than the interval S of adjacent two electrical contacts 120, just can not block between adjacent two electrical contacts 120.
First cladding 130 and the second cladding 140 have lateral surface 130s and 140s respectively.Because the lateral surface 130s of the first cladding 130 and lateral surface 140s of the second cladding 140 is formed in same cutting technique, therefore the lateral surface 130s of the first cladding 130 aligns haply with the lateral surface 140s of the second cladding 140, such as, flush.
The part of the coated electrical contact 120 of the second cladding 140 forms concave curvature 140u, concave curvature 140u towards the direction of the active surface 110a away from chip 110, i.e. concave curvature 140u active surface 110a dorsad.In addition, electrical contact 120 comprises one and is not subject to the coated exposed portion 121 of the second cladding 140 and is subject to the coated covered section 122 of the second cladding 140.Part (region more than dotted line) between the exposed portion 121 intersection 140e that to be concave curvature 140u contact with contiguous electrical contact 120 and the end 123 of electrical contact 120.Covered section 122 is parts of below the intersection 140e of electrical contact 120, and it is coated that it is subject to the second cladding 140.
When the coated electrical contact of the second cladding 140 120 volume the more (namely the volume of exposed portion 121 is fewer), the reliability of semiconductor package part 100 is better, but the scolding tin ability (Solderability) of electrical contact 120 poorer (when representing that semiconductor package part 100 is located at circuit board, electrical contact 120 more easily crack occurs).In the present embodiment, the volume of exposed portion 121 accounts for the ratio of the volume of electrical contact 120 between 40% to 60%, outstanding reliability can be obtained and and semiconductor package part 100 is located at circuit board time electrical contact 120 not easily there is crack.
Please refer to Fig. 2, it illustrates the graph of a relation of the characteristic of the semiconductor package part of Fig. 1 and the exposed portion of electrical contact.Curve C 1 represents that the second cladding 140 covers the graph of a relation of the height h (Fig. 1) of electrical contact 120 and the reliability of semiconductor package part 100.Curve C 2 represents that the second cladding 140 covers the graph of a relation of the height h (Fig. 1) of electrical contact 120 and the scolding tin ability of electrical contact 120.As seen from the figure, h is higher for height, then the reliability of semiconductor package part 100 better, but the scolding tin ability of electrical contact 120 is poorer.In the present embodiment, with the height H of electrical contact 120 be about 200 microns, the interval S of adjacent two electrical contacts 120 is for about 150 microns, volume ratio (volume of exposed portion 121 accounts for the ratio of the volume of electrical contact 120) about 50% corresponding to preferred height hs, outstanding reliability can be obtained and and semiconductor package part 100 is located at circuit board time electrical contact 120 not easily there is crack.
Please refer to Fig. 3 A to 3H, it illustrates the process drawing of the semiconductor package part of Fig. 1.
As shown in Figure 3A, the chip 110 after several unification is provided.Each chip 110 has lateral surface 110s and relative active surface 110a and back side 110b.Chip 110 comprises at least one connection pad 111, protective layer 112 and redistribution layer 113, and connection pad 111 is positioned at active surface 110a.
Protective layer 112 is such as inorganic protective layer, and it covers the active surface 110a of chip 110 and exposes connection pad 111.Redistribution layer 113 is the wafers before being formed at unification; Redistribution layer 113 can adopt laser or cutter unification wafer to become several chip 110 after being formed.
Redistribution layer 113 comprises the first dielectric layer 1131, line layer 1132 and the second dielectric layer 1133.First dielectric layer 1131 protective mulch 112 also has at least one perforate 1131a and exposes connection pad 111, makes line layer 1132 be electrically connected at the connection pad 111 exposed by perforate 1131a.Second dielectric layer 1133 covers a part for line layer 1132 and has another part that at least one perforate 1133a exposes line layer 1132, make the electrical contact 120 of follow-up formation can be formed on another part exposed of line layer 1132, to be electrically connected line layer 1132.
As shown in Figure 3A, this little chip 110 of rerouting is pasted on film 200 in support plate.The quality pasting film 200 due to support plate is soft, making the Part II 110s2 of the lateral surface 110s of chip 110 be absorbed in support plate pastes in film 200, and wherein the Part II 110s2 of lateral surface 110s comprises a part of the lateral surface 1133s of the second dielectric layer 1133 and the lateral surface 1131s of the first dielectric layer 1131.
As shown in Figure 3 B; can adopt is such as that compression forming, liquid encapsulation type, injection moulding or metaideophone are shaping; form the Part I 110s1 that the first cladding 130 covers the lateral surface 110s of chip 110; this Part I 110s1 is the part that the lateral surface 110s of chip 110 is not absorbed in that support plate pastes film 200, such as, be the lateral surface 112s of protective layer 112, another part of lateral surface 1131s of the first dielectric layer 1131 and the lateral surface 114s of silicon substrate 114.
As shown in Figure 3 C, remove support plate and paste film 200(Fig. 3 B), with the redistribution layer 113 of exposed chip 110.
As shown in Figure 3 D, at least one electrical contact 120 is formed on chip 110.Electrical contact 120 is formed at the line layer 1132 exposed, to be electrically connected at line layer 1132.
As shown in FIGURE 3 E, arrange the structure of Fig. 3 D in bed die 10, wherein electrical contact 120 is towards mold 20.
Arrange contact and paste film 300 on mold 20, contact pastes film 300 towards the electrical contact 120 being positioned at bed die 10.Then, to be such as coating technique, to form the second clad material 140 ' and cover electrical contact 120.If the second clad material 140 ' is now at pressurized and can produce mobility under being heated and be covered with all chips 110.
As illustrated in Figure 3 F, matched moulds bed die 10 and mold 20, make contact paste film 300 and extrude electrical contact 120, and then make the exposed portion 121 of electrical contact 120 be absorbed in contact to paste in film 300.The covered section 122 of electrical contact 120 is not absorbed in contact and pastes in film 300, makes covered section 122 can be subject to the coated of the second clad material 140 '.The quality pasting film 300 due to contact is soft, and contact is pasted after film 300 contacts with electrical contact 120, contact is pasted film 300 and squeezed out a protrusion curved surface 300b, so makes the second clad material 140 ' form corresponding concave curvature 140u.
In matched moulds process, the second clad material 140 ' is at pressurized and riddle contact under being heated and paste between film 300 and the first cladding 130, and covers the Part II 110s2 of the lateral surface 110s of chip 110 and the covered section 122 of electrical contact 120.Although the angular space SP1 that electrical contact 120 and contact are pasted between film 300 is narrow and small, so because the viscosity of the second clad material 140 ' controls between 100Pas to 500Pas, make the second clad material 140 ' successfully can fill up electrical contact 120 and contact pastes angular space SP1 narrow and small between film 300.
In addition, the accommodation space being expressed to the second clad material 140 ' in film 300 is pasted because electrical contact 120 part is absorbed in contact, make the second clad material 140 ' paste space between film 300 and chip 110 filling up contact more quickly by pressure, also can make the second clad material 140 ' more consolidation.
In addition, the second clad material 140 ' is directly touching the first cladding 130 by pressure.Specifically, after matched moulds, the second clad material 140 ' and the first cladding 130 form lower surface 140b and upper surface 130u respectively, and wherein lower surface 140b directly contacts with upper surface 130u.
In one embodiment, bed die 10 can be driven to move toward mold 20, with matched moulds bed die 10 and mold 20.Before matched moulds, in matched moulds process or after matched moulds, at least one of sustainable heating bed die 10 and mold 20, to be solidified into the second cladding 140 by the second clad material 140 ' after matched moulds.In addition, Cheng Qian is crossed at matched moulds, can first preheating bed die 10 and mold 20 at least one.
As shown in Figure 3 G, be separated bed die 10(Fig. 3 F) and mold 20(Fig. 3 F), paste film 300(Fig. 3 F to be separated the contact be positioned on mold 20) and the second cladding 140.
As shown in figure 3h, to be such as cutter or laser, at least all cut P1 through the second cladding 140 and the first cladding 130, to be formed at least just like the semiconductor package part 100 shown in Fig. 1 in formation.After cutting, the second cladding 140 and the first cladding 130 form lateral surface 140s and 130s respectively, and wherein lateral surface 140s and 130s aligns haply, as flushed.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (10)
1. a semiconductor package part, is characterized in that, comprising:
One chip, has a lateral surface;
One electrical contact, is formed on this chip;
One first cladding, a Part I of this lateral surface of this chip coated; And
One second cladding, a Part II of this lateral surface of this chip coated and this electrical contact of part, wherein this first cladding directly contacts with the place of the second cladding in this lateral surface of this chip.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this chip comprises:
One redistribution layer, has a lateral surface;
Wherein, this first cladding covers a part for this lateral surface of this redistribution layer, and this second cladding covers another part of this lateral surface of this redistribution layer.
3. semiconductor package part as claimed in claim 2, it is characterized in that, this chip has an active surface and comprises:
One connection pad, is formed at this active surface; And
One protective layer, covers this active surface and exposes this connection pad and have a lateral surface;
One redistribution layer, comprising:
One first dielectric layer, this first dielectric layer covers this protective layer and exposes this connection pad and have a lateral surface;
One line layer, is electrically connected this connection pad; And
One second dielectric layer, cover a part for this line layer and have another part that a perforate exposes this line layer, this second dielectric layer has a lateral surface.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this second cladding has a concave curvature, the direction of this concave curvature active surface of this chip dorsad.
5. semiconductor package part as claimed in claim 4, it is characterized in that, this electrical contact comprises:
Part between the intersection that one exposed portion is this concave curvature to be contacted with this contiguous electrical contact and the end of this electrical contact;
Wherein, the volume of this exposed portion accounts for the ratio of the volume of this electrical contact between 40% to 60%.
6. semiconductor package part as claimed in claim 1, it is characterized in that, the material of this first cladding and this second cladding is different.
7. a manufacture method for semiconductor package part, is characterized in that, comprising:
There is provided a chip, this chip has a lateral surface;
This chip of rerouting is pasted on film in a support plate, and a Part II of this lateral surface of this chip is absorbed in this support plate and pastes in film;
Form the Part I that one first cladding covers this lateral surface of this chip;
Remove this support plate and paste film, to expose this chip;
Form an electrical contact on this chip;
Arrange a contact to paste film and cover this electrical contact, this electrical contact of part is absorbed in this contact and pastes in film; And
Form one second cladding to cover this Part II of this lateral surface of this chip and this electrical contact and be not subject to this contact and paste the part that film covers, wherein this first cladding directly contacts with the second cladding this lateral surface part in this chip.
8. manufacture method as claimed in claim 7, it is characterized in that, in the step providing this chip, this chip comprises a redistribution layer, and this redistribution layer has a lateral surface;
Cover in the step of this Part I of this lateral surface of this chip in this first cladding of formation, this first cladding covers a part for this lateral surface of this redistribution layer;
Cover in the step of this Part II of this lateral surface of this chip in this second cladding of formation, this second cladding covers another part of this lateral surface of this redistribution layer.
9. manufacture method as claimed in claim 7, it is characterized in that, paste film cover in the step of this electrical contact in arranging this contact, this contact is pasted film and is formed a projected curved surface, make to cover in the step of this Part II of this lateral surface of this chip in this second cladding of formation, this second cladding is formed should a concave curvature of projected curved surface.
10. manufacture method as claimed in claim 7, is characterized in that, pastes the step that film covers this electrical contact comprise in arranging this contact:
This first clad material and this chip are set on a bed die;
This contact is set and pastes film in a mold; And
This bed die of matched moulds and this mold, make this part electrical contact be absorbed in this contact and paste in film.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810183068.6A CN108281398B (en) | 2013-08-20 | 2013-08-20 | Semiconductor package and method of manufacturing the same |
| CN201310364137.0A CN104425395A (en) | 2013-08-20 | 2013-08-20 | Semiconductor packaging part and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310364137.0A CN104425395A (en) | 2013-08-20 | 2013-08-20 | Semiconductor packaging part and manufacturing method thereof |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810183068.6A Division CN108281398B (en) | 2013-08-20 | 2013-08-20 | Semiconductor package and method of manufacturing the same |
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| CN104425395A true CN104425395A (en) | 2015-03-18 |
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| CN201310364137.0A Pending CN104425395A (en) | 2013-08-20 | 2013-08-20 | Semiconductor packaging part and manufacturing method thereof |
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| CN107195594A (en) * | 2016-03-14 | 2017-09-22 | 美光科技公司 | The semiconductor packages and its manufacture method of redistribution layer intermediary layer are protected with side wall |
| CN110462855A (en) * | 2017-03-31 | 2019-11-15 | 3M创新有限公司 | Electronic device including solid semiconductor tube core |
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| CN102122646A (en) * | 2011-02-01 | 2011-07-13 | 南通富士通微电子股份有限公司 | Wafer packaging device and chip packaging unit |
| US20130181338A1 (en) * | 2012-01-12 | 2013-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on Package Interconnect Structure |
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| CN107195594A (en) * | 2016-03-14 | 2017-09-22 | 美光科技公司 | The semiconductor packages and its manufacture method of redistribution layer intermediary layer are protected with side wall |
| CN107195594B (en) * | 2016-03-14 | 2018-12-04 | 美光科技公司 | Semiconductor packages and its manufacturing method with side wall protection redistribution layer intermediary layer |
| CN110462855A (en) * | 2017-03-31 | 2019-11-15 | 3M创新有限公司 | Electronic device including solid semiconductor tube core |
| US11114599B2 (en) * | 2017-03-31 | 2021-09-07 | 3M Innovative Properties Company | Electronic devices including solid semiconductor dies |
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| CN108281398A (en) | 2018-07-13 |
| CN108281398B (en) | 2021-10-08 |
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