CN104410132A - Voltage balancing device of supercapacitor and control method of voltage balancing device - Google Patents
Voltage balancing device of supercapacitor and control method of voltage balancing device Download PDFInfo
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Abstract
The invention provides a voltage balancing device of a supercapacitor and a control method of the voltage balancing device, relates to the energy storage technology of the supercapacitor, and aims to solve the problem that the service life of the supercapacitor is shortened due to inconsistent voltage of shunt sections of the supercapacitor. According to the voltage balancing device of the supercapacitor and the control method of the voltage balancing device, each energy storage unit is equipped with a balance controller which is controlled by a master controller, so that voltage of the shunt sections of the supercapacitor is balanced, consistent voltage of the shunt sections is kept, the service life of the supercapacitor is prolonged, and the energy storage quality of the supercapacitor is improved; and besides, the voltage balancing device of the supercapacitor and the control method of the voltage balancing device have the advantages that detection for voltage of the shunt sections of the supercapacitor is accurate, charge and discharge efficiency of the supercapacitor is high, the voltage balancing speed is high, the voltage consistency is good, capacity and internal resistance of the supercapacitor are identified accurately, module power density is high and the like.
Description
Technical field
The present invention relates to the energy storage technology of ultracapacitor.
Background technology
Ultracapacitor is a kind of electrochemical element being carried out energy storage by polarized electrolytic matter grown up from the 1970s and 1980s in last century.Outstanding advantages is that power density is high, the discharge and recharge time is short, have extended cycle life, operating temperature range is wide, is the one that in the double electric layer capacitor having dropped into volume production in the world, capacity is maximum.But ultracapacitor also exists some problems, such as each economize on electricity pressure in parallel is inconsistent, shortens the useful life etc. of ultracapacitor.
Summary of the invention
The object of the invention is to solve each economize on electricity pressure in parallel of ultracapacitor inconsistent, causing the problem of ultracapacitor shortening in useful life, the control method of a kind of ultracapacitor voltage balancer and this device is provided.
Ultracapacitor voltage balancer of the present invention comprises master controller, total current/voltage detection unit, multiple balance controller and DC-DC power module;
DC-DC power module is master controller, total current/voltage detection unit and multiple balance controller provide working power;
Multiple balance controller described in master controller connects and total current/voltage detection unit;
Each balance controller is also that the individual also interlink of described n charges for the terminal voltage of the individual also interlink of n measuring ultracapacitor;
Total current/voltage detection unit is for detecting total voltage and the total current of ultracapacitor output port.
Balance controller comprises n and interlink balancing unit, m simulation commutation circuit, AD treatment circuit, Balance route processor, processes temperature signal circuit, light-coupled isolation communicating circuit and insulating power supply, and m is less than n;
Each and interlink balancing unit is used for being one and interlink charging, and the control signal input of interlink balancing unit connects the charging control signal output of Balance route processor;
Each simulation commutation circuit is for measuring the terminal voltage of multiple and interlink, and m simulation commutation circuit measures the terminal voltage of n and interlink altogether, and measurement result is sent to Balance route processor by AD treatment circuit;
The output of processes temperature signal circuit connects the temperature signal input of Balance route processor, and the input of processes temperature signal circuit is for connecting temperature sensor;
Measurement result for measuring the temperature of energy-storage units, and is sent to Balance route processor by processes temperature signal circuit by temperature sensor, the also interlink that described energy-storage units comprises balance controller and is connected with this balance controller;
Balance route processor refrigeration control signal output part is used for the control signal input of connecting fan;
Balance route processor carries out transfer of data by CAN signal transmission line and master controller.
Described Balance route processor is embedded in and interrupts submodule by the Balance route of software simulating, and this module comprises with lower unit:
Economize on electricity pressure reading unit in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit and sending; And after this unit end of run, start economize on electricity pressure sequencing unit in parallel;
Economize on electricity pressure sequencing unit in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And overall charging instruction judging unit is started after this unit end of run;
Overall charging instruction judging unit: judge whether to receive the overall charging instruction that master controller is sent, and start overall charging instruction transmitting element when judged result is for being, start the first maximum voltage difference judging unit when judged result is no;
Overall charging instruction transmitting element: send charging instruction to the individual also interlink balancing unit of n; And after this unit end of run, start overall charging END instruction judging unit;
Overall charging END instruction judging unit: judge whether to receive the entirety charging END instruction that master controller is sent, and start when judged result is for being and stop overall charging instruction transmitting element; Overall charging END instruction judging unit is restarted when judged result is no;
Stop overall charging instruction transmitting element: send to the individual also interlink balancing unit of n and stop charging instruction; And the first maximum voltage difference judging unit is started after this unit end of run;
First maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and start selective charge instruction sending unit when judged result is for being, start identification unit when judged result is no;
Selective charge instruction sending unit: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit sends charging instruction; And the second maximum voltage difference judging unit is started after this unit end of run;
Second maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference judging unit is restarted when judged result is for being, start when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit corresponding to three and interlink and stop charging instruction; And identification unit is started after this unit end of run;
Identification unit: the capacity and the internal resistance that calculate super capacitor; And identification result transmitting element is started after this unit end of run;
Identification result transmitting element: also interlink capacity and the internal resistance that are calculated by identification unit are sent to master controller; And temperature conditioning unit is started after this unit end of run;
Temperature conditioning unit: control the temperature of energy-storage units in its temperature range normally worked; And overall charging instruction judging unit is started after this unit end of run.
The control method of above-mentioned ultracapacitor voltage balancer comprises the following steps:
Economize on electricity pressure read step in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit and sending; And after this step terminates, perform economize on electricity pressure ordered steps in parallel;
Economize on electricity pressure ordered steps in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And after this step terminates, perform overall charging instruction determining step;
Overall charging instruction determining step: judge whether to receive the overall charging instruction that master controller is sent, and perform overall charging instruction forwarding step when judged result is for being, perform the first maximum voltage difference determining step when judged result is no;
Overall charging instruction forwarding step: send charging instruction to the individual also interlink balancing unit of n; And after this step terminates, perform overall charging END instruction determining step;
Overall charging END instruction determining step: judge whether to receive the entirety charging END instruction that master controller is sent, and perform when judged result is for being and stop overall charging instruction forwarding step; Overall charging END instruction determining step is re-executed when judged result is no;
Stop overall charging instruction forwarding step: send to the individual also interlink balancing unit of n and stop charging instruction; And after this step terminates, perform the first maximum voltage difference determining step;
First maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and perform selective charge instruction forwarding step when judged result is for being, perform identification step when judged result is no;
Selective charge instruction forwarding step: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit sends charging instruction; And after this step terminates, perform the second maximum voltage difference determining step;
Second maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference determining step is re-executed when judged result is for being, perform when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit corresponding to three and interlink and stop charging instruction; And identification step is performed after this step terminates;
Identification step: the capacity and the internal resistance that calculate super capacitor; And identification result forwarding step is performed after this step terminates;
Identification result forwarding step: also interlink capacity and the internal resistance that identification step are calculated are sent to master controller; And temperature control step is performed after this step terminates;
Temperature control step: control the temperature of energy-storage units in its temperature range normally worked; And after this step row terminates, return the overall charging instruction determining step of execution.
The control method of ultracapacitor voltage balancer of the present invention and this device, for each energy-storage units configuration balance controller, balance controller is by passing through main controller controls, the voltage of each also interlink of balanced super capacitor, each junction voltage in parallel is consistent, thus extend the life-span of super capacitor, promote the energy storage quality of ultracapacitor.It is that energy-storage units supplements pressure reduction that condenser voltage is converted into 24V constant voltage source by DC-DC power module.This device has super capacitor parallel connection joint voltage detecting accurate, and super capacitor efficiency for charge-discharge is high, and electric voltage equalization speed is fast, and voltage consistency is good, super capacitor capacity and internal resistance identification accurate, module power density advantages of higher.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the ultracapacitor voltage balancer described in execution mode;
Fig. 2 is the functional block diagram of the master controller chip in execution mode one;
Fig. 3 is the theory diagram of energy-storage units in execution mode two;
Fig. 4 is the functional block diagram of Balance route processor in execution mode two;
Fig. 5 is the theory diagram of the AD treatment circuit in execution mode three;
Fig. 6 is the circuit structure diagram of simulation commutation circuit in execution mode three and AD treatment circuit;
Fig. 7 is the circuit structure diagram of processes temperature signal circuit in execution mode four;
Fig. 8 is the control method flow chart in execution mode ten;
Fig. 9 is the flow chart of temperature control step in execution mode 11;
Figure 10 is the equivalent circuit diagram of joint capacitance in parallel and internal resistance in execution mode 12;
Figure 11 is the schematic diagram of the calculating voltage in execution mode 12;
Figure 12 is the discrimination method flow chart in execution mode 12;
Figure 13 is the circuit structure diagram of DC-DC power module in execution mode eight.
Embodiment
Embodiment one: composition graphs 1 and Fig. 2 illustrate present embodiment, the ultracapacitor voltage balancer described in present embodiment comprises master controller 1, total current/voltage detection unit 2, multiple balance controller 3 and DC-DC power module 4;
DC-DC power module 4 is master controller 1, total current/voltage detection unit 2 and multiple balance controller 3 provide working power;
Master controller 1 connects described multiple balance controllers 3 and total current/voltage detection unit 2;
Each balance controller 3 is also that the individual also interlink of described n charges for the terminal voltage of the individual also interlink of n measuring ultracapacitor;
Total current/voltage detection unit 2 is for detecting total voltage and the total current of ultracapacitor output port.
In present embodiment, the capacitor be connected with balance controller 3 be ultracapacitor and connect.The chip selection model of master controller 1 is the ARM chip of STM32F407, the framework of this chip is Cortex-M4,32 MCU, with FPU unit, have 210DMIPS, nearly 1MB FLASH/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 timers, 3 ADC, 15 communication interfaces and a shooting mouth, clock frequency is 168MHz.The sampling of energy-storage units total current and total voltage is responsible for by master controller 1, and LEM current sensor selected by current sensor, and output voltage is 5V, sends into 16 bit AD sample chips after sampling processing circuit.Voltage sensor selects LEM voltage sample module, and output voltage is 5V, sends into the 16 bit AD sample chips that model is AD32680 after sampling processing circuit.The also interlink that described energy-storage units comprises balance controller 3 and is connected with this balance controller 3.
The function of master controller 1 comprises: read and mainly make that contact inputs, balanced judgements, temperature detection, total voltage and total current detect energy-storage units voltage, state and protection contact export, read bus data, pass down the fan control of equalization instruction, energy-storage units control of discharge and integrating cabinet, show monitoring voltage Monitoring Data in real time and carry out telecommunication etc.
Embodiment two: composition graphs 3 and Fig. 4 illustrate present embodiment, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode one, in present embodiment, described balance controller 3 comprises n and interlink balancing unit 3-1, m simulation commutation circuit 3-2, AD treatment circuit 3-3, Balance route processor 3-4, processes temperature signal circuit 3-5, light-coupled isolation communicating circuit 3-6 and insulating power supply, and m is less than n;
Each and interlink balancing unit 3-1 is used for being one and interlink charging, and the control signal input of interlink balancing unit 3-1 connects the charging control signal output of Balance route processor 3-4;
Each simulation commutation circuit 3-2 is for measuring the terminal voltage of multiple and interlink, and m simulation commutation circuit 3-2 measures the terminal voltage of n and interlink altogether, and measurement result is sent to Balance route processor 3-4 by AD treatment circuit 3-3;
The output of processes temperature signal circuit 3-5 connects the temperature signal input of Balance route processor 3-4, and the input of processes temperature signal circuit 3-5 is for connecting temperature sensor 3-7
Measurement result for measuring the temperature of energy-storage units, and is sent to Balance route processor 3-4 by processes temperature signal circuit 3-5 by temperature sensor 3-7, the also interlink that described energy-storage units comprises balance controller 3 and is connected with this balance controller 3;
Balance route processor 3-4 refrigeration control signal output part is used for the control signal input of connecting fan 3-8;
Balance route processor 3-4 carries out transfer of data by CAN signal transmission line and master controller 1.
As shown in Figure 3, during use, be connected by Balance route processor 3-4 with blower fan 3-8, be connected by processes temperature signal circuit 3-5 with temperature sensor 3-7, temperature sensor 3-7 is for measuring the temperature of energy-storage units.Multiple processes temperature signal circuit 3-5 and multiple temperature sensor 3-7 can be set, for measuring the temperature of energy-storage units diverse location.Each simulation commutation circuit 3-2 is to one and the voltage of interlink carries out differential sample; by and the voltage difference at interlink two ends changes absolute voltage over the ground into; send into after proportional component, filtering link and limited amplitude protection link in AD sampling A/D chip; AD sampling A/D chip changes analog quantity into digital quantity, controls and relevant exception and fault detect for voltage dynamic equalization.As shown in Figure 4, Balance route processor 3-4 adopts DSPIC30F5011 cake core to realize, and its major function makes charging to also interlink of being correlated with to judge, sends relevant also interlink charge command.And interlink balancing unit 3-1 starts after receiving order, charge to corresponding also interlink.After parallel connection economize on electricity presses and is raised to predetermined value, Balance route processor 3-4 sends stopping charge command, and interlink balancing unit 3-1 quits work.Balance route processor 3-4 also has the function monitored the temperature of energy-storage units, the also interlink that described energy-storage units comprises balance controller 3 and is connected with this balance controller 3.Temperature sensor 3-7 exports the voltage signal of representation temperature; ratio through processes temperature signal circuit 3-5 adjusts, send into Balance route processor 3-4 after filtering and limited amplitude protection link; Balance route processor 3-4 changes temperature analog signal into digital signal; when temperature exceedes predetermined value, Balance route processor 3-4 sends the order starting blower fan.DC-DC power module 4 for insulating power supply and and interlink balancing unit 3-1 working power is provided, insulating power supply exports two electric pressures, comprise for m the 24V voltage that provides of simulation commutation circuit 3-2 and AD treatment circuit 3-3, and the 5V voltage provided for Balance route processor 3-4, processes temperature signal circuit 3-5 and light-coupled isolation communicating circuit 3-6.
The function of Balance route processor 3-4 comprises: the condition monitoring that joint voltage detecting in parallel, energy-storage units internal temperature detect, joint capacitance in parallel and internal resistance identification, economize on electricity in parallel are held, energy-storage units temperature control, energy-storage units internal balance unit controls and and master controller 1 between information exchange etc.As shown in Figure 4, the control chip of Balance route processor 3-4 selects high-performance 16 position digital signal single-chip microcomputer to its functional block diagram, and model is DSPIC30F5011.This chip has 12,16 tunnel ADC, and other function comprises: DSPIC30F5011 chip adopts high-performance modified model RISC CPU, and 8 interrupt priority levels, comprise the data converter interfaces such as I2C, two with the CAN module of CAN2.0B operating such.
N joint voltage signal in parallel is transferred to after digital quantity through AD treatment circuit 3-3 and being sent in the single-chip microcomputer of Balance route processor 3-4 by the SPI serial signal of light-coupled isolation communicating circuit 3-6 after being selected by m multi-channel analog commutation circuit 3-2.Arrange 2 each and every one a temperature sensor 3-7 and 2 processes temperature signal circuit 3-5 in present embodiment, the temperature signal of 2 road energy-storage units is directly delivered in single-chip microcomputer, utilizes AD in sheet to carry out the conversion of analog quantity to digital quantity.The gating of multi-channel analog commutation circuit 3-2 is controlled by four road I/O ports of single-chip microcomputer, and 16 tunnels the start and stop of interlink balancing unit have 16 road I/O ports of single-chip microcomputer to control, and the break-make Ye You mono-road I/O port of blower fan 3-8 controls.External memory space is expanded by parallel data mouth.
Embodiment three: composition graphs 5 and Fig. 6 illustrate present embodiment, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode two, in present embodiment, described AD treatment circuit 3-3 comprises analog processing circuit 3-3-1, analog-to-digital converting module 3-3-2 and digital isolation module 3-3-3;
M the signal input part of analog processing circuit 3-3-1 connects the signal output part of m simulation commutation circuit 3-2 respectively, the input end of analog signal of the signal output part connecting analog/data-converting block 3-3-2 of analog processing circuit 3-3-1, the digital signal output end of analog-to-digital converting module 3-3-2 connects the parallel connection joint voltage signal inputs of Balance route processor 3-4 by digital isolation module 3-3-3, the channel selecting control signal output of digital isolation module 3-3-3 connects the channel selecting control signal input of m simulation commutation circuit 3-2.
As shown in Figure 6, elect the centre position of the connection in series-parallel joint in an energy-storage units as ground, then the energy-storage units of 60V becomes ± 30V, then voltage is reduced further by divider resistance by each and interlink, become ± 15V, this voltage range is within the operating voltage of amplifier, and divider resistance is 32 resistance in Fig. 6 between four simulation commutation circuit 3-2 and electric capacity module.16 joint voltage signals in parallel, by after the transformation of divider resistance, through the channel selecting of 4 multi-channel analog commutation circuit 3-2 (analog switch chip namely in Fig. 6), enter analog processing circuit 3-3-1.The parallel connection economize on electricity pressure on every road all samples separately by differential amplifier.Analog processing circuit 3-3-1 adopts three operational amplifiers to realize, and operational amplifier model is LT1014, and duplicate supply 15V powers.R1 and C1 forms low-pass first order filter and carries out filtering to voltage signal, and D1 plays limited amplitude protection effect.When voltage is more than 5V, Vi voltage will be clamped to 5.7V, and the overvoltage of voltage signal can be prevented like this to the damage of analog processing circuit 3-3-1.As shown in Figure 6, the follow circuit that in analog processing circuit 3-3-1, two amplifiers on the left side are formed can be used for impedance isolation, to eliminate the impact of conduction impedance on sampled voltage of analog switch.
The significant advantage of this design is: 1, sampling precision is high, directly samples to super-capacitor voltage, and the resolution of each parallel connection joint voltage sample immobilizes; 2, error is without coupling, and the error Zhi Yuzhe road sampling channel of voltage sample is correlated with, without coupled relation between neighboring voltage sampling.
Embodiment four: composition graphs 7 illustrates present embodiment, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode two.Because temperature has appreciable impact the useful life on super capacitor, in use to ensure that the temperature in energy-storage units is no more than the scope of super capacitor working temperature, therefore need to monitor the temperature of energy-storage units inside.Two temperature sensors are placed at the diverse location of energy-storage units, by the 5V Power supply of isolating in this programme.Temperature sensor 3-7 adopts PT100, and output voltage signal is input to Balance route processor 3-4 after the processes temperature signal circuit 3-5 shown in Fig. 7.Operational amplification circuit in processes temperature signal circuit 3-5 realizes the scale amplifying to temperature sensor output signal, R2 and C2 forms first-order low-pass ripple link, the High-frequency Interference in filtered signal.VD can prevent temperature signal overvoltage from causing the damage of Balance route processor 3-4.
Embodiment five: composition graphs 8 illustrates present embodiment, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode two, in present embodiment, described Balance route processor 3-4 is embedded in and interrupts submodule by the Balance route of software simulating, and this module comprises with lower unit:
Economize on electricity pressure reading unit in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit 3-2 and sending; And after this unit end of run, start economize on electricity pressure sequencing unit in parallel;
Economize on electricity pressure sequencing unit in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And overall charging instruction judging unit is started after this unit end of run;
Overall charging instruction judging unit: judge whether to receive the overall charging instruction that master controller 1 is sent, and start overall charging instruction transmitting element when judged result is for being, start the first maximum voltage difference judging unit when judged result is no;
Overall charging instruction transmitting element: send charging instruction to the individual also interlink balancing unit 3-1 of n; And after this unit end of run, start overall charging END instruction judging unit;
Overall charging END instruction judging unit: judge whether to receive the entirety charging END instruction that master controller 1 is sent, and start when judged result is for being and stop overall charging instruction transmitting element; Overall charging END instruction judging unit is restarted when judged result is no;
Stop overall charging instruction transmitting element: send to the individual also interlink balancing unit 3-1 of n and stop charging instruction; And the first maximum voltage difference judging unit is started after this unit end of run;
First maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and start selective charge instruction sending unit when judged result is for being, start identification unit when judged result is no;
Selective charge instruction sending unit: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit 3-1 sends charging instruction; And the second maximum voltage difference judging unit is started after this unit end of run;
Second maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference judging unit is restarted when judged result is for being, start when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit 3-1 corresponding to three and interlink and stop charging instruction; And identification unit is started after this unit end of run;
Identification unit: the capacity and the internal resistance that calculate super capacitor; And identification result transmitting element is started after this unit end of run;
Identification result transmitting element: also interlink capacity and the internal resistance that are calculated by identification unit are sent to master controller 1; And temperature conditioning unit is started after this unit end of run;
Temperature conditioning unit: control the temperature of energy-storage units in its temperature range normally worked; And overall charging instruction judging unit is started after this unit end of run.
As shown in Figure 8, Balance route interrupts the reading that first submodule carries out economize on electricity pressure in parallel to the software flow of Balance route processor 3-4.The parallel connection joint magnitude of voltage at every turn read is stored, and covers the last parallel connection joint magnitude of voltage read, namely only store the last parallel connection joint magnitude of voltage read.The voltage signal read sorts from high to low by carrying out parallel connection economize on electricity pressure after digital filtering.Then judge whether master controller 1 sends the overall charging instruction of energy-storage units, if there is overall charging instruction, then all in this energy-storage units and interlink balancing unit 3-1 sends charging instruction, until overall charging instruction is cancelled.If there is no overall charging instruction, then carry out the electric voltage equalization of energy-storage units inside, judge whether the difference of the highest parallel connection economize on electricity pressure and minimum parallel connection economize on electricity pressure exceedes Δ U, if exceed Δ U, then give magnitude of voltage on the low side 3 and interlink balancing unit sends charging instruction, until internal balance terminates, if the difference of the highest parallel connection economize on electricity pressure and minimum parallel connection economize on electricity pressure does not exceed Δ U, then exit energy-storage units internal balance.In present embodiment, Δ U gets 25mV.Then carry out and the identification of interlink super capacitor capacity and internal resistance, and identification result is sent to master controller 1.Finally read the temperature of energy-storage units and judge whether overtemperature, if overtemperature, starting cooling system, be i.e. blower fan 3-8.
Embodiment six: composition graphs 9 illustrates present embodiment, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode five, and in present embodiment, described temperature conditioning unit comprises with lower unit:
Temperature signal reading unit: read the temperature value that also storing temperature signal processing circuit 3-5 sends; And after this unit end of run start-up temperature judging unit;
First temperature judging unit: whether the temperature value described in judgement is higher than T
0, and start fan starting unit when judged result is for being, stop Balance route interrupting the operation of submodule when judged result is no;
Described Δ U and T
0be pre-set value, T
0for the temperature upper limit that energy-storage units can normally work;
Fan starting unit: send enabled instruction to blower fan 3-8; And the second temperature judging unit is started after this unit end of run;
Second temperature judging unit: whether the temperature value described in judgement is higher than T
0, and the second temperature judging unit is restarted when judged result is for being, start blower fan stop element when judged result is no;
Blower fan stop element: send instruction out of service to blower fan 3-8, and the operation terminating that after this unit end of run Balance route interrupts submodule.
Embodiment seven: present embodiment is described in conjunction with Figure 10 to Figure 12, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode five, and in present embodiment, described identification unit comprises with lower unit:
Super capacitor terminal voltage and input current reading unit: constantly read and store terminal voltage and the input current of the super capacitor that master controller 1 is sent; And after this unit end of run start end voltage and input current average value computing unit;
Terminal voltage and input current average value computing unit: calculate up-to-date average voltage u
3and up-to-date input current average value i
3, u
3for the mean value of the terminal voltage of the super capacitor of nearest p reading, i
3for the mean value of the input current of the super capacitor of nearest p reading; P be more than or equal to 3 integer; And after this unit end of run start-up capacitance and internal resistance computing unit;
Electric capacity and internal resistance computing unit: the electric capacity C and the internal resistance r that calculate super capacitor according to the following equation; And after this unit end of run start-up simulation result judging unit;
U
2for nearest second time is to the mean value of the terminal voltage of the super capacitor of the p+1 time reading, i
2for nearest second time is to the mean value of the input current of the super capacitor of the p+1 time reading;
U
1for nearest third time is to the mean value of the terminal voltage of the super capacitor of the p+2 time reading, i
1for nearest third time is to the mean value of the input current of the super capacitor of the p+2 time reading;
Result of calculation judging unit: judge the value of C and r that calculates whether within correct scope, and when judged result is for being start-up simulation result transmitting element; Start-up capacitance and internal resistance updating block when judged result is no;
Result of calculation transmitting element: the value of C and r calculated is sent to master controller 1; And after this unit end of run start-up capacitance and internal resistance updating block;
Electric capacity and internal resistance updating block: u
1=u
2, i
1=i
2, u
2=u
3, i
2=i
3; And identification unit end of run is terminated after this unit end of run.
The capacity of online real-time identification super capacitor and internal resistance for super capacitor life estimation and fault detect significant, the method that present embodiment is taked is by obtaining the calculating of continuous 3 groups of average voltages and average current value, make can calculate super capacitor in this way and the equivalent capacity of interlink and equivalent series resistance, principle as shown in Figure 10 and Figure 11.In Figure 10, u is the terminal voltage of super capacitor, and i is the input current of super capacitor, and r is the internal resistance of super capacitor, and C is the capacitance of super capacitor, before subscript 1 and 2 representative not in the same time, and T
1for i
1the corresponding moment, T
2for i
2the corresponding moment.
Following relation is there is by the known not voltage and current in the same time of Figure 10 and Figure 11:
Wherein,
can with a top, be respectively i below
1, i
2, be highly △ T=T
2-T
1ladder approximation represent, getting not three groups of data in the same time can obtain:
The identification formula that can obtain super capacitor capacity and internal resistance is then arranged by (2) formula:
As shown in figure 12, to the continuous filtering that is averaged of sampling for 5 times of parallel connection joint voltage and current, the result drawn is as up-to-date magnitude of voltage u for the algorithm flow of super capacitor capacity and internal resistance identification
3with current value i
3, substitute in formula (3) and calculate, result of calculation is judged, if calculate correct, upgrade the value of capacitance and internal resistance and upload result of calculation to master controller 1; If incorrect, give up this result of calculation.Update mode is for giving up u
1and i
1, by u
2and i
2value be assigned to u respectively
1and i
1, by u
3and i
3value be assigned to u respectively
2and i
2, then terminate the operation of identification unit.In result of calculation determining step, can according to before this repeatedly the mean value of result of calculation determine correct scope, such as, get repeatedly the mean value of result of calculation up and down 10% for correct scope.
Embodiment eight: present embodiment is described in conjunction with Figure 13, present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode one, in present embodiment, described DC-DC power module 4 is for providing energy for whole voltage balancing device.Its index request is: can meet and the power demand that simultaneously charges of 1/4th of interlink sum and interlink balancing unit 3-1.
All and 1/4th of interlink balancing unit 3-1 by 120 tunnels calculate, every road maximum power is 50W, then the rated power of DC-DC power conversion is 120 × 50W=6kW.The principle of DC-DC power module 4 as shown in figure 13, in order to improve conversion efficiency, reduce humorous wave interference, adopt LLC resonant half-bridge converter structure, can in full voltage range, under full load condition, primary side MOSFET be made to realize ZVS (zero voltage switch), secondary commutation diode realizes ZCS (Zero Current Switch), reduces switching loss, substantially increases efficiency.And when input voltage and loading range change greatly, the change of its switching frequency is less, is conducive to the design of principal parameter.In present embodiment, the efficiency of DC-DC power module 4 is 94%, and the efficiency of interlink balancing unit 3-1 is 90%, and balanced pressure system gross efficiency is 85%.
Embodiment nine: present embodiment is the further restriction to the ultracapacitor voltage balancer described in execution mode one, in present embodiment, described ultracapacitor voltage balancer also comprises display device, and this display device is connected with master controller 1.
Display device adopts touch-screen to realize, for carrying out function selection and parameters etc.
Embodiment ten: composition graphs 8 illustrates present embodiment, present embodiment is the control method of the ultracapacitor voltage balancer described in execution mode two, and the method comprises the following steps:
Economize on electricity pressure read step in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit 3-2 and sending; And after this step terminates, perform economize on electricity pressure ordered steps in parallel;
Economize on electricity pressure ordered steps in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And after this step terminates, perform overall charging instruction determining step;
Overall charging instruction determining step: judge whether to receive the overall charging instruction that master controller 1 is sent, and perform overall charging instruction forwarding step when judged result is for being, perform the first maximum voltage difference determining step when judged result is no;
Overall charging instruction forwarding step: send charging instruction to the individual also interlink balancing unit 3-1 of n; And after this step terminates, perform overall charging END instruction determining step;
Overall charging END instruction determining step: judge whether to receive the entirety charging END instruction that master controller 1 is sent, and perform when judged result is for being and stop overall charging instruction forwarding step; Overall charging END instruction determining step is re-executed when judged result is no;
Stop overall charging instruction forwarding step: send to the individual also interlink balancing unit 3-1 of n and stop charging instruction; And after this step terminates, perform the first maximum voltage difference determining step;
First maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and perform selective charge instruction forwarding step when judged result is for being, perform identification step when judged result is no;
Selective charge instruction forwarding step: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit 3-1 sends charging instruction; And after this step terminates, perform the second maximum voltage difference determining step;
Second maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference determining step is re-executed when judged result is for being, perform when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit 3-1 corresponding to three and interlink and stop charging instruction; And identification step is performed after this step terminates;
Identification step: the capacity and the internal resistance that calculate super capacitor; And identification result forwarding step is performed after this step terminates;
Identification result forwarding step: also interlink capacity and the internal resistance that identification step are calculated are sent to master controller 1; And temperature control step is performed after this step terminates;
Temperature control step: control the temperature of energy-storage units in its temperature range normally worked; And after this step row terminates, return the overall charging instruction determining step of execution.
In present embodiment, when overall charging instruction sent by master controller 1, Balance route processor 3-4 controls coupled all and interlink carries out entirety charging.When not carrying out entirety charging, Balance route processor 3-4 can monitor the voltage of each also interlink, when the maximum of each parallel connection economize on electricity pressure reduction exceedes pre-set a certain numerical value, start 3 the also interlink chargings lower to voltage, to balance the voltage of each and interlink, until the maximum of each parallel connection economize on electricity pressure reduction is less than pre-set numerical value.In charging process, also need constantly detected temperatures, when temperature is too high, Balance route processor 3-4 controls blower fan and starts working, and lowers the temperature, until temperature drops within the scope of normal working temperature.In addition, Balance route processor 3-4 also needs to calculate the capacitance of super capacitor and interior resistance, and result of calculation is sent to master controller 1 to show in real time.
Embodiment 11: composition graphs 9 illustrates present embodiment, present embodiment is the further restriction of the control method to the ultracapacitor voltage balancer described in execution mode ten, and in present embodiment, described temperature control step comprises the following steps:
Temperature signal read step: read the temperature value that also storing temperature signal processing circuit 3-5 sends; And after this step terminates, perform the first temperature determining step;
First temperature determining step: whether the temperature value described in judgement is higher than T
0, and perform fan starting step when judged result is for being, terminate temperature control step when judged result is no;
Described Δ U and T
0be pre-set value, T
0for the temperature upper limit that energy-storage units step can normally work;
Fan starting step: send enabled instruction to blower fan 3-8; And the second temperature determining step is performed after this step end of run;
Second temperature determining step: whether the temperature value described in judgement is higher than T
0, and blower fan stopping step being performed when judged result is for being, execution second temperature determining step is returned when judged result is no;
Blower fan stops step: send instruction out of service to blower fan 3-8; And temperature control step is terminated after this step end of run.
Embodiment 12: present embodiment is described in conjunction with Figure 10 to 12, present embodiment is the further restriction of the control method to the ultracapacitor voltage balancer described in execution mode ten, in present embodiment, described identification step comprises the following steps:
Super capacitor terminal voltage and input current read step: constantly read and store terminal voltage and the input current of the super capacitor that master controller 1 is sent; And after this step terminates actuating station voltage and input current average value calculation procedure;
Terminal voltage and input current average value calculation procedure: calculate up-to-date average voltage u
3and up-to-date input current average value i
3, u
3for the mean value of the terminal voltage of the super capacitor of nearest p reading, i
3for the mean value of the input current of the super capacitor of nearest p reading; P be more than or equal to 3 integer; And after this step terminates, perform electric capacity and internal resistance calculation procedure;
Electric capacity and internal resistance calculation procedure: the electric capacity C and the internal resistance r that calculate super capacitor according to the following equation; And result of calculation determining step is performed after this step terminates;
U
2for nearest second time is to the mean value of the terminal voltage of the super capacitor of the p+1 time reading, i
2for nearest second time is to the mean value of the input current of the super capacitor of the p+1 time reading;
U
1for nearest third time is to the mean value of the terminal voltage of the super capacitor of the p+2 time reading, i
1for nearest third time is to the mean value of the input current of the super capacitor of the p+2 time reading;
Result of calculation determining step: judge the value of C and r that calculates whether within correct scope, and perform result of calculation forwarding step when judged result is for being; Electric capacity and internal resistance step of updating is performed when judged result is no;
Result of calculation forwarding step: the value of C and r calculated is sent to master controller 1; And after this step terminates, perform electric capacity and internal resistance step of updating;
Electric capacity and internal resistance step of updating: u
1=u
2, i
1=i
2, u
2=u
3, i
2=i
3, so far, identification step terminates.
Identification steps flow chart as shown in figure 12.Online real-time identification parallel connection joint capacitance and internal resistance for super capacitor life estimation and fault detect significant, the method that present embodiment is taked is by obtaining the calculating of continuous 3 groups of average voltages and average current value, make can calculate super capacitor in this way and the equivalent capacity of interlink and equivalent series resistance, principle as shown in Figure 10 and Figure 11.In Figure 10, u is the terminal voltage of super capacitor, and i is the input current of super capacitor, and r is the internal resistance of super capacitor, and C is the capacitance of super capacitor, before subscript 1 and 2 representative not in the same time, and T
1for i
1the corresponding moment, T
2for i
2the corresponding moment.In result of calculation determining step, can according to before this repeatedly the mean value of result of calculation determine correct scope, such as, get repeatedly the mean value of result of calculation up and down 10% for correct scope.
Claims (9)
1. ultracapacitor voltage balancer, is characterized in that: it comprises master controller (1), total current/voltage detection unit (2), multiple balance controller (3) and DC-DC power module (4);
DC-DC power module (4) is master controller (1), total current/voltage detection unit (2) and multiple balance controller (3) provide working power;
Multiple balance controllers (3) described in master controller (1) connects and total current/voltage detection unit (2);
Each balance controller (3) is also that the individual also interlink of described n charges for the terminal voltage of the individual also interlink of n measuring ultracapacitor;
Total current/voltage detection unit (2) is for detecting total voltage and the total current of ultracapacitor output port.
2. ultracapacitor voltage balancer according to claim 1, it is characterized in that: described balance controller (3) comprises n and interlink balancing unit (3-1), m simulation commutation circuit (3-2), AD treatment circuit (3-3), Balance route processor (3-4), processes temperature signal circuit (3-5), light-coupled isolation communicating circuit (3-6) and insulating power supply, and m is less than n;
Each and interlink balancing unit (3-1) is for being one and interlink charging, and the control signal input of interlink balancing unit (3-1) connects the charging control signal output of Balance route processor (3-4);
Each simulation commutation circuit (3-2) is for measuring the terminal voltage of multiple and interlink, m simulation commutation circuit (3-2) measures the terminal voltage of n and interlink altogether, and measurement result is sent to Balance route processor (3-4) by AD treatment circuit (3-3);
The output of processes temperature signal circuit (3-5) connects the temperature signal input of Balance route processor (3-4), and the input of processes temperature signal circuit (3-5) is for connecting temperature sensor (3-7);
Temperature sensor (3-7) is for measuring the temperature of energy-storage units, and measurement result is sent to Balance route processor (3-4) by processes temperature signal circuit (3-5), the also interlink that described energy-storage units comprises balance controller (3) and is connected with this balance controller (3);
Balance route processor (3-4) refrigeration control signal output part is used for the control signal input of connecting fan (3-8);
Balance route processor (3-4) carries out transfer of data by CAN signal transmission line and master controller (1).
3. ultracapacitor voltage balancer according to claim 2, is characterized in that: described AD treatment circuit (3-3) comprises analog processing circuit (3-3-1), analog-to-digital converting module (3-3-2) and digital isolation module (3-3-3);
M signal input part of analog processing circuit (3-3-1) connects the signal output part of m simulation commutation circuit (3-2) respectively, the input end of analog signal of the signal output part connecting analog/data-converting block (3-3-2) of analog processing circuit (3-3-1), the digital signal output end of analog-to-digital converting module (3-3-2) connects the parallel connection joint voltage signal inputs of Balance route processor (3-4) by digital isolation module (3-3-3), the channel selecting control signal output of numeral isolation module (3-3-3) connects the channel selecting control signal input of m simulation commutation circuit (3-2).
4. ultracapacitor voltage balancer according to claim 2, is characterized in that: described Balance route processor (3-4) is embedded in and interrupts submodule by the Balance route of software simulating, and this module comprises with lower unit:
Economize on electricity pressure reading unit in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit (3-2) and sending; And after this unit end of run, start economize on electricity pressure sequencing unit in parallel;
Economize on electricity pressure sequencing unit in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And overall charging instruction judging unit is started after this unit end of run;
Overall charging instruction judging unit: judge whether to receive the overall charging instruction that master controller (1) is sent, and overall charging instruction transmitting element is started when judged result is for being, the first maximum voltage difference judging unit is started when judged result is no;
Overall charging instruction transmitting element: send charging instruction to the individual also interlink balancing unit (3-1) of n; And after this unit end of run, start overall charging END instruction judging unit;
Overall charging END instruction judging unit: judge whether to receive the entirety charging END instruction that master controller (1) is sent, and start when judged result is for being and stop overall charging instruction transmitting element; Overall charging END instruction judging unit is restarted when judged result is no;
Stop overall charging instruction transmitting element: send to the individual also interlink balancing unit (3-1) of n and stop charging instruction; And the first maximum voltage difference judging unit is started after this unit end of run;
First maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and start selective charge instruction sending unit when judged result is for being, start identification unit when judged result is no;
Selective charge instruction sending unit: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit (3-1) sends charging instruction; And the second maximum voltage difference judging unit is started after this unit end of run;
Second maximum voltage difference judging unit: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference judging unit is restarted when judged result is for being, start when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit (3-1) corresponding to three and interlink and stop charging instruction; And identification unit is started after this unit end of run;
Identification unit: the capacity and the internal resistance that calculate super capacitor; And identification result transmitting element is started after this unit end of run;
Identification result transmitting element: also interlink capacity and the internal resistance that are calculated by identification unit are sent to master controller (1); And temperature conditioning unit is started after this unit end of run;
Temperature conditioning unit: control the temperature of energy-storage units in its temperature range normally worked; And overall charging instruction judging unit is started after this unit end of run.
5. ultracapacitor voltage balancer according to claim 4, is characterized in that: described temperature conditioning unit comprises with lower unit:
Temperature signal reading unit: read the temperature value that also storing temperature signal processing circuit (3-5) is sent; And after this unit end of run start-up temperature judging unit;
First temperature judging unit: whether the temperature value described in judgement is higher than T
0, and start fan starting unit when judged result is for being, stop Balance route interrupting the operation of submodule when judged result is no;
Described Δ U and T
0be pre-set value, T
0for the temperature upper limit that energy-storage units can normally work;
Fan starting unit: send enabled instruction to blower fan (3-8); And the second temperature judging unit is started after this unit end of run;
Second temperature judging unit: whether the temperature value described in judgement is higher than T
0, and the second temperature judging unit is restarted when judged result is for being, start blower fan stop element when judged result is no;
Blower fan stop element: send instruction out of service to blower fan (3-8), and the operation terminating that after this unit end of run Balance route interrupts submodule.
6. ultracapacitor voltage balancer according to claim 4, is characterized in that: described identification unit comprises with lower unit:
Super capacitor terminal voltage and input current reading unit: constantly read and store terminal voltage and the input current of the super capacitor that master controller (1) is sent; And after this unit end of run start end voltage and input current average value computing unit;
Terminal voltage and input current average value computing unit: calculate up-to-date average voltage u
3and up-to-date input current average value i
3, u
3for the mean value of the terminal voltage of the super capacitor of nearest p reading, i
3for the mean value of the input current of the super capacitor of nearest p reading; P be more than or equal to 3 integer; And after this unit end of run start-up capacitance and internal resistance computing unit;
Electric capacity and internal resistance computing unit: the electric capacity C and the internal resistance r that calculate super capacitor according to the following equation; And after this unit end of run start-up simulation result judging unit;
U
2for nearest second time is to the mean value of the terminal voltage of the super capacitor of the p+1 time reading, i
2for nearest second time is to the mean value of the input current of the super capacitor of the p+1 time reading;
U
1for nearest third time is to the mean value of the terminal voltage of the super capacitor of the p+2 time reading, i
1for nearest third time is to the mean value of the input current of the super capacitor of the p+2 time reading;
Result of calculation judging unit: judge the value of C and r that calculates whether within correct scope, and when judged result is for being start-up simulation result transmitting element; Start-up capacitance and internal resistance updating block when judged result is no;
Result of calculation transmitting element: the value of C and r calculated is sent to master controller (1); And after this unit end of run start-up capacitance and internal resistance updating block;
Electric capacity and internal resistance updating block: u
1=u
2, i
1=i
2, u
2=u
3, i
2=i
3; And identification unit end of run is terminated after this unit end of run.
7. the control method of ultracapacitor voltage balancer according to claim 2, is characterized in that: the method comprises the following steps:
Economize on electricity pressure read step in parallel: constantly read and store m n the joint magnitude of voltage in parallel of simulating commutation circuit (3-2) and sending; And after this step terminates, perform economize on electricity pressure ordered steps in parallel;
Economize on electricity pressure ordered steps in parallel: described n joint magnitude of voltage in parallel is sorted according to by high order on earth; And after this step terminates, perform overall charging instruction determining step;
Overall charging instruction determining step: judge whether to receive the overall charging instruction that master controller (1) is sent, and overall charging instruction forwarding step is performed when judged result is for being, the first maximum voltage difference determining step is performed when judged result is no;
Overall charging instruction forwarding step: send charging instruction to the individual also interlink balancing unit (3-1) of n; And after this step terminates, perform overall charging END instruction determining step;
Overall charging END instruction determining step: judge whether to receive the entirety charging END instruction that master controller (1) is sent, and perform when judged result is for being and stop overall charging instruction forwarding step; Overall charging END instruction determining step is re-executed when judged result is no;
Stop overall charging instruction forwarding step: send to the individual also interlink balancing unit (3-1) of n and stop charging instruction; And after this step terminates, perform the first maximum voltage difference determining step;
First maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and perform selective charge instruction forwarding step when judged result is for being, perform identification step when judged result is no;
Selective charge instruction forwarding step: to magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit (3-1) sends charging instruction; And after this step terminates, perform the second maximum voltage difference determining step;
Second maximum voltage difference determining step: judge whether the difference of the maxima and minima in n joint magnitude of voltage in parallel is greater than Δ U, and the second maximum voltage difference determining step is re-executed when judged result is for being, perform when judged result is no and stop selective charge instruction forwarding step;
Stop selective charge instruction forwarding step: send to the also interlink balancing unit (3-1) corresponding to three and interlink and stop charging instruction; And identification step is performed after this step terminates;
Identification step: the capacity and the internal resistance that calculate super capacitor; And identification result forwarding step is performed after this step terminates;
Identification result forwarding step: also interlink capacity and the internal resistance that identification step are calculated are sent to master controller (1); And temperature control step is performed after this step terminates;
Temperature control step: control the temperature of energy-storage units in its temperature range normally worked; And after this step row terminates, return the overall charging instruction determining step of execution.
8. the control method of ultracapacitor voltage balancer according to claim 7, is characterized in that: described temperature control step comprises the following steps:
Temperature signal read step: read the temperature value that also storing temperature signal processing circuit (3-5) is sent; And after this step terminates, perform the first temperature determining step;
First temperature determining step: whether the temperature value described in judgement is higher than T
0, and perform fan starting step when judged result is for being, terminate temperature control step when judged result is no;
Described Δ U and T
0be pre-set value, T
0for the temperature upper limit that energy-storage units step can normally work;
Fan starting step: send enabled instruction to blower fan (3-8); And the second temperature determining step is performed after this step end of run;
Second temperature determining step: whether the temperature value described in judgement is higher than T
0, and blower fan stopping step being performed when judged result is for being, execution second temperature determining step is returned when judged result is no;
Blower fan stops step: send instruction out of service to blower fan (3-8); And temperature control step is terminated after this step end of run.
9. the control method of ultracapacitor voltage balancer according to claim 7, is characterized in that: described identification step comprises the following steps:
Super capacitor terminal voltage and input current read step: constantly read and store terminal voltage and the input current of the super capacitor that master controller (1) is sent; And after this step terminates actuating station voltage and input current average value calculation procedure;
Terminal voltage and input current average value calculation procedure: calculate up-to-date average voltage u
3and up-to-date input current average value i
3, u
3for the mean value of the terminal voltage of the super capacitor of nearest p reading, i
3for the mean value of the input current of the super capacitor of nearest p reading; P be more than or equal to 3 integer; And after this step terminates, perform electric capacity and internal resistance calculation procedure;
Electric capacity and internal resistance calculation procedure: the electric capacity C and the internal resistance r that calculate super capacitor according to the following equation; And result of calculation determining step is performed after this step terminates;
U
2for nearest second time is to the mean value of the terminal voltage of the super capacitor of the p+1 time reading, i
2for nearest second time is to the mean value of the input current of the super capacitor of the p+1 time reading;
U
1for nearest third time is to the mean value of the terminal voltage of the super capacitor of the p+2 time reading, i
1for nearest third time is to the mean value of the input current of the super capacitor of the p+2 time reading;
Result of calculation determining step: judge the value of C and r that calculates whether within correct scope, and perform result of calculation forwarding step when judged result is for being; Electric capacity and internal resistance step of updating is performed when judged result is no;
Result of calculation forwarding step: the value of C and r calculated is sent to master controller (1); And after this step terminates, perform electric capacity and internal resistance step of updating;
Electric capacity and internal resistance step of updating: u
1=u
2, i
1=i
2, u
2=u
3, i
2=i
3, so far, identification step terminates.
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