CN104409422A - Low-thickness and low-cost chip size package with cavity - Google Patents
Low-thickness and low-cost chip size package with cavity Download PDFInfo
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- CN104409422A CN104409422A CN201410678131.5A CN201410678131A CN104409422A CN 104409422 A CN104409422 A CN 104409422A CN 201410678131 A CN201410678131 A CN 201410678131A CN 104409422 A CN104409422 A CN 104409422A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
The invention discloses a low-thickness and low-cost chip size package with a cavity, and belongs to the field of packaging of semiconductors. The package structure comprises a cover plate, a wafer, a function region, bonding pads, bonding glue, silicon through holes, a redistribution circuit layer and a solder ball, wherein a cavity structure is formed in the front surface of the cover plate; the wafer comprises a wafer front surface and a wafer back surface; the function region and the bonding pads are distributed on the wafer front surface; the bonding pads are distributed on the periphery of the function region and are communicated with one another; the bonding glue is positioned between the cover plate and the wafer; the cover plate and the wafer are bonded together by the bonding glue; the bonding pads are exposed via the silicon through holes, so that the bonding pads are communicated with the a follow-up redistribution layer; the redistribution circuit layer is positioned on the wafer back surface and comprises a passivation layer, a metal layer and a solder layer; the bonding pads are communicated with the solder ball via the redistribution circuit layer; and the solder ball is positioned on the redistribution circuit layer of the wafer back surface. The thickness of the package is reduced, and the stress in the structure is also reduced. Moreover, the yield of a cutting process and the reliability of the package are improved.
Description
Technical field
The present invention relates to a kind of low thickness low-cost chip sized package containing cavity, belong to field of semiconductor package.Imageing sensor, MEMS or integrated chip etc. can be preferably used for.
Background technology
Chip size packages (CSP) is the chip encapsulation technology of a new generation, and its technical performance has had again new lifting.CSP encapsulation can allow the ratio of chip area and package area more than 1:1.14, quite close to the ideal situation of 1:1, absolute dimension also only has 32 square millimeters, is about 1/3 of common BGA, is only equivalent to 1/6 of Outline Package (TSOP) memory chip area.Encapsulate with common ball grid array structure compared with (BGA), under equal space, memory capacity can be improved three times by CSP encapsulation.When the object of CSP is the chip before use superchip (chip functions is more, and performance is better, and chip is more complicated) substitutes, the area that its packaging body takies printed panel remains unchanged or less.Little and thin just because of CSP packaging body, therefore it obtains application rapidly in Portable mobile electronic device.Volume size after CSP not only reduces encapsulation significantly, reduce packaging cost, improve packaging efficiency, and more meet the requirement of high-density packages; Simultaneously because data transfer path is short, stability is high, this be encapsulated in reduce energy consumption while also improve speed and the stability of transfer of data.
Silicon through hole (Through-Silicon Via) technology by making vertical conducting between chip or wafer, realizes the technology of vertical direction interconnection as one, is considered to the important channel realizing three-dimensional interconnection encapsulation.It possesses many advantages simultaneously: overall dimension is little, low in energy consumption, packaging density is high, high frequency characteristics is excellent, it is the shortest etc. to interconnect between chip.
When some current imageing sensors and MEMS are encapsulated, often there is following problem:
1., according to its chip feature, sometimes need, its surface coverage layer protective layer cover plate (cover sheet can be glass, silicon etc.), then to utilize the supporting wall structure that macromolecule polymer material makes, it is carried out bonding with chip by cover plate.First, because knee wall all has certain height, thus add the overall thickness of encapsulating structure, have impact on final overall dimension, particularly produce inferior position at thickness direction.Secondly, material due to knee wall is high molecular polymer, under arms in process, because the thermal coefficient of expansion difference of cover plate 100, wafer 102, these three kinds of materials of knee wall is larger, and thermal coefficient of expansion do not mate the generation that can cause thermal stress, cause encapsulating structure at follow-up failtests with in being on active service, easily the destruction such as knee wall and the layering between cover plate 100 and wafer 102, crackle occurs, thus cause device function decline even to be lost efficacy.
2. existing encapsulating structure often makes the distribution again line layer of metal-containing layer 107 before this on whole of wafer rear 102b, and then carries out wafer 102 cutting the chip forming single.Owing to needing the region of cutting to comprise the different material of the multiple hardness such as distribution again line layer, silicon, polymer, cover plate 100, this just proposes great challenge to cutting technique, easily produces the phenomenon such as fragment, sliver.On the other hand, in the follow-up military service process of encapsulating products, because metal level 107 is direct same extraneous contact at the surrounding place of encapsulating structure, once there is the layering between interface, easily the moisture in external environment is introduced encapsulating structure inner, cause the acceleration of device to lose efficacy.
3. when using silicon through hole 105 technology, because prior art also exists many challenges when preparing the silicon through hole of high-aspect-ratio.First its cost remains high always, secondly in preparation technology as: the hole etching of silicon through hole 105, plating to be filled etc. technique step and all be there is complex process, situation that product yield is low.When the depth-to-width ratio of silicon through hole 105 is higher, institute's facing challenges is also severeer.
In order to overcome above problem, need to research and develop a low thickness, low cost, high reliability and the chip scale package structure containing cavity easily realized and manufacture method.
Summary of the invention
A first aspect of the present invention is: provide a kind of low thickness low-cost chip size packaging structure containing cavity.By encapsulating structure of the invention process, first the thickness of encapsulating structure can be reduced, reduce the stress produced due to thermal mismatching between different materials, result of finite element shows, compare tradition and adopt the structure of knee wall, encapsulating structure of the present invention has the range of decrease of about 30% at the stress of cover plate 100 and wafer 102 interface.Thus the inefficacy such as interface debonding, crackle can be improved; Secondly, by utilizing welding resisting layer 108 to be wrapped up by metal level 107, decreasing in cutting process the kind needing to remove material, both having improve cutting technique yield, and in turn enhanced the reliability of encapsulation; Finally, by adopting two step silicon etchings, first the silicon of wafer 102 surrounding is carried out partial etching, then in the mode making silicon through hole 105, the demand to silicon through hole having high depth-to-width ratio 105 can be reduced, thus achieve high reliability packaging with lower cost and technique threshold.
In order to realize above object, the present invention by the following technical solutions:
A kind of low thickness low-cost chip size packaging structure containing cavity of the invention process, described structure comprises: cover plate 100, and is manufactured with cavity structure 100c at cover plate front 100a; Wafer 102, is manufactured with functional areas 103 and pad 104 at wafer frontside 102a; By being coated with one deck bonding glue 101 at cover plate front 100a, cover plate front 100a is bonded to together with wafer frontside 102a; By making silicon through hole 105 and distribution again line layer at wafer rear 102b, the pad 104 of wafer frontside 102a is realized conducting with the soldered ball 109 of wafer rear 102b.Described distribution again line layer comprises passivation layer 106, metal level 107, welding resisting layer 108.
Described metal level 107 the edge of wafer 102 wrap up by described welding resisting layer 108 and directly do not contact with the external world.
Optionally, described chip can be image sensor chip, MEMS IC or integrated chip etc.
Optionally, described pad 104 is distributed in the edge of functional areas 103, and with wafer 102 central authorities functional areas 103 between conducting in advance.
Optionally, described cover plate 100 can be the transparent materials such as glass, quartz, plastic cement, also can be the materials such as silicon, pottery, metal.
Optionally, described cavity structure 100c is positioned at the central authorities of cover plate front 100a, directly over functional areas 103; And the cross section of cavity structure 100c can be circular or square.
Optionally, when making described silicon through hole 105, first the silicon of wafer 102 surrounding being carried out thinning removal, then at making silicon through hole 105, making its thickness be no more than 1/2nd of wafer 102 thickness.
A second aspect of the present invention there is provided a kind of method preparing the described low thickness low-cost chip size packaging structure containing cavity, comprises the following steps:
Step 1, makes cover plate 100: make cavity structure 100c at cover plate front 100a;
Step 2, wafer 102 bonding: by bonder, is bonded together cover plate front 100a with wafer frontside 102a, thus forms a closed cavity between cover plate 100 and wafer 102;
Step 3, wafer 102 is thinning: thinning process carries out in two steps: first, by grinder, grinds, wafer 102 is thinned to setting thickness to wafer rear 102b; Then, destressing plasma etching is carried out to the wafer rear 102b after thinning;
Step 4, silicon etching, comprises twice plasma etching industrial: first time etches, and is removed by the silicon of wafer rear 102b surrounding, by over half for its thickness etching; Second time etching, on the basis of previous step, the region of continuing wafer 102 surrounding has etched etches, and to form silicon through hole 105, is come out by the pad 104 of wafer frontside 102a simultaneously;
Step 5, passivation layer 106 deposits: by plasma activated chemical vapour deposition, in silicon through hole 105 hole, deposit one deck passivation layer 106 with wafer rear 102b, and removes, the passivation layer bottom silicon through hole 105 to expose pad 104;
Step 6, successively at wafer rear 102b, makes metal level 107 and welding resisting layer 108 in silicon through hole 105 hole, thus pad 104 is conducting to default soldered ball 109 position of wafer rear 102b;
Step 7, makes soldered ball 109: be formed at by soldered ball 109 on the distribution again line layer of wafer rear 102b, then the surrounding cutting of wafer 102 formed to the encapsulation of single chips.
Optionally, described cover plate front 100a utilizes bonding glue 101 to carry out bonding with wafer frontside 102a, and described bonding glue 101 is a kind of resinae bonded adhesives.
Optionally, described first time and second time silicon etching are the dry etch process adopting plasma etching, comprise deep reaction ion etching (DRIE).
Optionally, when removing the passivation layer 106 bottom described silicon through hole 105, the method for plasma etching or laser ablation can be adopted.
Optionally, the thickness of described outermost welding resisting layer 108 is no more than 1.5 times of passivation layer 106 thickness, to reduce the stress between different materials interface.
Compared with prior art, by the enforcement of patent of the present invention, beneficial effect is:
1. by making cavity structure 100c on cover plate 100, thus eliminate in conventional package, the supporting wall structure required when cover plate 100 and wafer 102 bonding.On the one hand, present invention reduces the thickness of encapsulating structure entirety, achieve the miniaturization of encapsulating structure, ultrathin.On the other hand, owing to not adopting traditional supporting wall structure, the stress owing to producing due to thermal mismatching between different materials in structure can be reduced, show by there being line element result of calculation, compare traditional supporting wall structure, have the range of decrease of about 30% at the stress of cover plate 100 and wafer 102 interface.Thus the inefficacy such as interface debonding, crackle can be improved, improve the reliability of encapsulation.
2. by utilizing described welding resisting layer 108 to be wrapped up by the metal level 107 of wafer 102 edge, thus metal level 107 is not directly contacted with the external world, first, owing to decreasing the cutting to metal level 107 in cutting technique, decrease the material category needing cutting, thus decrease owing to cutting the fragment, the sliver phenomenon that cause, improve the yield of cutting, reduce the challenge to cutting technique step.Secondly, because metal level 107 does not directly contact with the external world, reduce the peel stress between the different interface of boundary, also can prevent moisture from entering into encapsulation along metal level 107 inner, the reliability in improve product stage under arms.
3. by employing two step silicon etching, first the silicon of wafer 102 surrounding is carried out part removal, then in the mode making silicon through hole 105, the demand to silicon through hole having high depth-to-width ratio 105 can be reduced, cost is low and easily realize, thus achieves high reliability packaging with lower cost and technique threshold.
Routine embodiment cited below particularly of the present invention, and coordinate accompanying drawing to elaborate to above-mentioned feature and advantage of the present invention.
Accompanying drawing explanation
Fig. 1 is a kind of low thickness low-cost chip size packaging structure schematic diagram containing cavity drawn according to the present invention.
Fig. 2 (a) is a kind of manufacturing process generalized section containing the low thickness low-cost chip sized package of cavity of drawing according to embodiments of the invention to (e).
Number in the figure: 100. cover plates, 100a. cover plate front, the 100b. cover plate back side, 100c. cavity structure, 101. bonding glue, 102. wafers, 102a. wafer frontside, 102b. wafer rear, 103. functional areas, 104. pad, 105. silicon through holes, 106. passivation layers, 107. metal levels, 108. welding resisting layers, 109. soldered balls.
Embodiment
Below with reference to accompanying drawings the present invention is described in more detail:
Shown in Fig. 1, a kind of low thickness low-cost chip sized package containing cavity of embodiment of the present invention, its structure comprises:
1. cover plate 100, in cover plate front, 100a is manufactured with cavity structure 100c; 2. wafer 102, it comprises wafer frontside 102a and wafer rear 102b; 3. functional areas 103 and pad 104, described functional areas 103 and pad 104 are all distributed in wafer frontside 102a, and wherein pad 104 is distributed in the periphery of function 103, and realizes conducting; 4. bonding glue 101, between cover plate 100 and wafer 102, is bonded together the two; 5. silicon through hole 105, pad 104 comes out by described silicon through hole 105, realizes conducting to make pad 104 with between follow-up redistribution layer; 6. distribution again line layer, described distribution again line layer is positioned at wafer rear 102b, comprises passivation layer 106, metal level 107 and welding resisting layer 108, by distribution again line layer, the pad 104 of wafer frontside 102a is conducting to soldered ball 109 position of wafer rear 102b; 7. soldered ball 109, is positioned on the distribution again line layer of wafer rear 102b.
A kind of low thickness low-cost chip sized package manufacturing process containing cavity of the present embodiment is described in detail below in conjunction with Fig. 2 (a) to (e).Fig. 2 (a) is a kind of low thickness low-cost chip sized package manufacturing process generalized section containing cavity of drawing according to embodiments of the invention to (e).
Step 1, cover plate 100 makes:
Please refer to Fig. 2 (a), first cover plate 100 is provided, by equal glue machine, even spread one deck photoresist on the 100a of cover plate front, exposure imaging technique is utilized to open needing the window making cavity structure 100c, then form cavity structure 100c by etching technics at cover plate front 100a, finally the photoresist of coating is removed.
In the present embodiment, described cover plate 100 can be the transparent materials such as glass, quartz, plastic cement, also can be the materials such as silicon, pottery, metal.The cross section of described cavity structure 100c can be circular or square.
Step 2, wafer 102 bonding:
Please refer to Fig. 2 (b), be first coated with one deck bonding glue 101 at cover plate front 100a, then utilize bonder, cover plate front 100a is carried out bonding with wafer frontside 102a.
In the present embodiment, bonding glue 101 can adopt the mode of round brush to be coated with, and described bonding glue 101 is a kind of resinae bonded adhesives.
Step 3, wafer 102 is thinning:
Please refer to Fig. 2 (c), first, by grinder, wafer rear 102b is ground, be thinned to setting thickness; Then, after grinding destressing plasma etching is carried out to wafer rear 102b.
In the present embodiment, from 600 ~ 700 microns of the thickness of wafer 102 are down to 130 microns; Destressing plasma etching is the internal stress in order to remove due to grinding generation in wafer 102, improves the warpage of wafer 102, is convenient to subsequent technique and carries out.
Step 4, silicon etching, comprises twice plasma etching industrial:
Silicon etching for the first time: please refer to Fig. 2 (c), removed by the silicon of wafer rear 102b surrounding, by over half for its thickness etching;
Second time silicon etching: on the basis of previous step, the region of continuing wafer 102 surrounding has etched etches, and to form silicon through hole 105, is come out by the pad 104 of wafer frontside 102a simultaneously.
In the present embodiment, described secondary silicon etching is the dry etch process adopting plasma etching, comprises deep reaction ion etching (DRIE).
Step 5, passivation layer 106 deposits:
Please refer to Fig. 2 (d), by plasma activated chemical vapour deposition, in silicon through hole 105 hole, deposit one deck passivation layer 106 with wafer rear 102b; And the passivation layer 106 bottom silicon through hole 105 is removed, to expose pad 104.
In the present embodiment, when the passivation layer 106 bottom described silicon through hole 105 is removed, the method for plasma etching or laser ablation can be adopted.
Step 6, makes metal level 107 and welding resisting layer 108:
Please refer to Fig. 2 (e), first, by sputtering or electroplating technology in silicon through hole 105 hole and passivation layer 106 surface deposition layer of metal layer 107, and it is graphically formed circuit; Then on metal level 107, be coated with one deck welding resisting layer 108, and form opening in the position of default soldered ball 109.
In the present embodiment, when carrying out patterning to described metal level 107, described patterning comprises to be removed the metal level 107 in wafer 102 edge, metal level 107 is wrapped up at surrounding boundary by welding resisting layer 108, thus avoids metal level 107 directly to contact with the external world.In addition, the filling mode of described silicon through hole 105 both can adopt the method for plated metal to carry out hatching solid, and welding resisting layer 108 can also be utilized to fill.
Step 7, makes soldered ball 109:
Please refer to Fig. 2 (e), soldered ball 109 is formed on the distribution again line layer of wafer rear 102b, then the surrounding cutting of wafer 102 is formed to the encapsulation of single chips.
In the present embodiment, described soldered ball 109 can adopt the mode of planting ball or steel mesh printing to make.
To be object be effectively illustrates and describe the present invention in the description of the embodiment that the present invention carries out, but only should not be construed as by example the scope of the present invention limiting and defined by claims by this.Technical staff belonging to any this area without departing from the spirit and scope of the present invention, can make possible variation and amendment.Therefore protection of the present invention covers the amendment in the essence of an invention that defines of claim and scope.
Claims (4)
1., containing a low thickness low-cost chip size packaging structure for cavity, its feature is comprising:
There is provided wafer, comprising having the chip region comprising multiple pad in wafer frontside;
Cover plate, covers one deck cover plate in wafer frontside, is wherein manufactured with cavity structure in the central authorities in cover plate front, thus forms a closed cavity between cover plate and wafer;
Silicon through hole, the pad of wafer frontside through described wafer, thus comes out by described silicon through hole;
The distribution again line layer structure of wafer rear, distribution again line layer is made up of passivation layer, metal level and welding resisting layer, by making distribution again line layer, the pad of wafer frontside is conducting to the soldered ball of wafer rear.
For the metal level in described wafer rear distribution again line layer, its at crystal round fringes place wrap up by welding resisting layer and directly do not contact with the external world.
2. encapsulating structure according to claim 1, is characterized in that, wherein said chip is image sensor chip, MEMS IC or integrated chip.
3. the method for preparation a kind of low thickness low-cost chip size packaging structure containing cavity according to claim 1, is characterized in that, comprise the following steps:
Step 1, cover plate makes: adopt plasma etching industrial, forms cavity structure in cover plate front;
Step 2, wafer bonding: utilize wafer bonding machine, by being coated with one deck bonding glue in cover plate front, is bonded together cover plate front with wafer frontside;
Step 3, wafer is thinning, and thinning process carries out in two steps: first, by grinder, grinds wafer rear, wafer is thinned to setting thickness; Then, destressing plasma etching is carried out to the wafer rear after thinning;
Step 4, silicon etching, comprises twice plasma etching industrial: first time etches, and is removed by the silicon of wafer rear surrounding, by over half for its thickness etching; Second time etching, on the basis of previous step, the region of continuing wafer surrounding has etched etches, and to form silicon through hole, is come out by the pad of wafer frontside simultaneously.
Step 5, passivation layer deposition: by plasma activated chemical vapour deposition, deposits one deck passivation layer with wafer rear in the hole of silicon through hole, then adopts the method for plasma etching or laser ablation, removes, the passivation layer of silicon via bottoms to expose pad;
Step 6, successively at wafer rear, makes metal level and welding resisting layer in silicon through hole hole, thus pad is conducting to the default soldered ball position of wafer rear;
Step 7, makes soldered ball: be formed at by soldered ball on the distribution again line layer of wafer rear, then the surrounding cutting of wafer formed to the encapsulation of single chips.
4. method according to claim 3, is characterized in that, the thickness of welding resisting layer is no more than 1.5 times of passivation layer thickness.
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| CN201410678131.5A CN104409422A (en) | 2014-11-23 | 2014-11-23 | Low-thickness and low-cost chip size package with cavity |
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| CN201410678131.5A CN104409422A (en) | 2014-11-23 | 2014-11-23 | Low-thickness and low-cost chip size package with cavity |
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| CN107265391A (en) * | 2017-06-29 | 2017-10-20 | 华进半导体封装先导技术研发中心有限公司 | MEMS wafer class encapsulation structure and its technique |
| CN107396239A (en) * | 2017-06-06 | 2017-11-24 | 纽威仕微电子（无锡）有限公司 | A kind of hydrophone and its packaging technology |
| CN107658380A (en) * | 2017-10-27 | 2018-02-02 | 无锡吉迈微电子有限公司 | The wafer packaging structure and manufacture craft of SAW filter |
| CN108975264A (en) * | 2017-06-01 | 2018-12-11 | 北京万应科技有限公司 | Chip of micro-electro-mechanical system wafer and system packaging method and MEMS |
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| CN110416236A (en) * | 2018-04-28 | 2019-11-05 | 中芯国际集成电路制造（天津）有限公司 | The packaging method of chip, semiconductor structure and preparation method thereof |
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| CN109100398A (en) * | 2018-07-23 | 2018-12-28 | 华进半导体封装先导技术研发中心有限公司 | A kind of Alcohol mental disorders system packaging structure and its manufacturing method |
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| CN111384915A (en) * | 2018-12-29 | 2020-07-07 | 中芯集成电路（宁波）有限公司上海分公司 | Integrated structure of crystal resonator and control circuit and integration method thereof |
| CN110649054A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving stress of solder mask layer of CIS chip |
| CN113066781A (en) * | 2021-03-23 | 2021-07-02 | 浙江集迈科微电子有限公司 | Interposer stacking module, three-dimensional module and stacking process |
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