CN104393962A - Multi-way E1 deframing system - Google Patents
Multi-way E1 deframing system Download PDFInfo
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- CN104393962A CN104393962A CN201410761932.8A CN201410761932A CN104393962A CN 104393962 A CN104393962 A CN 104393962A CN 201410761932 A CN201410761932 A CN 201410761932A CN 104393962 A CN104393962 A CN 104393962A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
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Abstract
The invention relates to the communication field, in particular to a multi-way E1 deframing system. The system comprises multi-way HDB3 decoding modules, an MUX (multiplexer) module, an FIFO (first in first out) module and an E1 deframer module, wherein the multi-way HDB3 decoding modules are sequentially connected with the MUX module; one end of the MUX module is connected with one end of the FIFO module, and the other end of the FIFO module is connected with one end of the E1 deframer module; and the other end of the E1 deframer module is connected with a lower assembly. Multi-way E1 deframing data are assembled into a serial data stream by an MUX, E1 deframing recovery can be performed only by one E1 deframer, multi-way E1 data are reassembled, the condition that each way of E1 requires one independent deframer conventionally is avoided, and logical units required by the E1 deframer are greatly saved.
Description
technical field
The present invention relates to a kind of communications field, particularly a kind of multichannel E1 separates frame system.
Background technology
In data communication field, it is the most basic frame process that E1 signal framing conciliates frame, according to G.704, every basic frame is made up of 32 channel time slots (ts0-ts31), each channel time slot, is made up of 8bit code, basic frame frame frequency is 8000 frames/second, and namely 2.048Mbit/s data carry out framing transmission by anchor-frame structure, receives frame solution frame.
According to " design of E1 one-tenth/deframer " (Hunan University's physics and microelectronics science institute, Li Peng's journey, Yan Yonghong, handsome gold is known, Guo Youhong) E1 one-tenth/deframer comprises e1_framer, e1_deframer, e1pi tri-modules, e1_framer module forms the E1 frame structure meeting G.704 agreement and specify to the data sent; Module carries out solution frame to the data received, and is namely separated the carrying out of frame part and is explained; Data are sent to line side and simultaneously receive data from circuit by e1pi module in charge, and this is comprising detecting, recovering from data clock (debit to) to data, carry out the conversion (hdb3 encoding and decoding) of pattern, check coded violation, CV.
E1 one-tenth/deframer comparatively describes single channel E1 framing solution frame method and process in detail, but in actual applications, it is often many that E1 receives and dispatches road, we conventional 16 road E1 receive and dispatch, if adopt single channel separate processing approach, a large amount of logical resource will be needed, for saving logical resource, the present invention adopts multichannel E1 to separate frame data and is assembled into serial data stream through multiplexer, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, the every road E1 of tradition is avoided all to need an independent deframer, so just greatly save logical block needed for E1 deframer.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency existing in prior art, provide a kind of multichannel E1 to separate frame system.Multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer, only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, avoid tradition solution frame system Zhong Mei road E1 all to need the problem of an independent deframer, greatly save the logical block needed for E1 deframer.
In order to realize foregoing invention object, the invention provides following technical scheme:
A kind of multichannel E1 separates frame system, comprises multichannel HDB3 decoder module, multiplexer MUX module, fifo module and E1 deframer module; Wherein every road HDB3 decoder module is connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the next device.
According to the E1 signalling channel number that system comprises, comprise the HDB3 decoder module of 1,2,4,8,16 or 32, wherein said HDB3 decoder module is connected with multiplexer MUX module respectively.
Further, described HDB3 decoder module, comprises HDB3 decoder, cv_check module, Los_det module and ais_det module; Wherein HDB3 decoder is connected with ais_det module respectively with cv_check module, Los_det module; Native system is based on HDB3 code, and HDB3 code is a kind of modified model of AMI code, not only overcomes the shortcoming when there is connecting " 0 " code timing detection difficult in AMI code, and has spectrum energy and mainly concentrate on below fundamental frequency, the advantage that band occupancy is narrower.
In work, every road E1 signal, after HDB3 decoding module decodes, detects coded violation, CV alarm by cv_check module respectively, detects dropout (Los) alarm by Los_det module, detects " 1 " (ais) alarm entirely by ais_det module; And directly send alarming processing by above-mentioned fault alarm signal, loss alarm signal Los and complete " 1 " alarm signal (ais).
Further, described HDB3 decoder module, also comprise Clk-recovery module, described Clk-recovery module is used for recovered clock E1_clk_2M rising edge, and then the enable E1_clk_2M_en of the recovered clock generating every road, complete HDB3 adaptive clock recovery, recover this road E1 2.048 MHz clock.
This kind of multichannel E1 separates the course of work following steps of frame system:
(1) every road E1 signal is input to respectively in corresponding HBD3 module;
(2) every road E1 is through HDB3 decoding module decodes, recovers E1 data; Detect complete " 1 " alarm signal Ais, lose alarm signal Los, fault alarm signal Cv_err etc., directly the next device of input processes;
(3) multiplexer MUX module, carries out circulating sampling by passage to E1 signal, generates multichannel E1_data serial data stream, and by described E1_data serial data stream write FIFO;
(4) E1 deframer module carries out the process of solution frame from FIFO reading data, detects that the data of LOF, LOM, FAS-ERR, CRC-ERR alarm and passage E1_data output in the next device respectively.
Multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer by native system, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, avoid the every road E1 of tradition all to need an independent deframer, greatly save logical block needed for E1 deframer.
Further, to the E1 data that HDB3 decoder module recovers in native system, carry out sampling by passage high-speed circulating:
Further, adopt each channel frequence of high-frequency clock circulating sampling to be the E1 signal of 2.048 MHz in native system, recover every road E1 clock E1_clk_2M and every road E1 data E1_data.
Preferably, native system comprises 16 road E1 signals.When system comprises 16 road E1 signal, an each channel frequence of 81.92MHz high-frequency clock circulating sampling is adopted to be the E1 signal recuperation Chu Mei road E1 clock E1_clk_2M of 2.048 MHz and every road E1 data E1_data.
Further, when system comprises 16 road E1 signal, described FIFO selects 32*5bit, wherein 4bit port numbers+1 bit data; FIFO selects according to the designing requirement of system.
Preferably, native system comprises 32 road E1 signals.When system comprises 32 road E1 signals, adopt an each channel frequence of 163.84MHZ high-frequency clock circulating sampling to be the E1 signal of 2.048 MHz, recover every road E1 clock E1_clk_2M and every road E1 data E1_data.
Further, when system comprises 32 road E1 signal, described FIFO selects 32*6bit, wherein 5bit port numbers+1 bit data; FIFO selects according to the designing requirement of system.
Further, described multiplexer MUX module, the multiplexing clock adopted is identical with passage E1 sampling clock; The data E1_data of the multiplexing every road E1 of loop cycle, adds every road e1 port number, forms multichannel serial data stream and sends into FIFO.
Further, the multi-channel serial data flow of generation is sent in recurrent wrIting FIFO by described multiplexer MUX module.
Further, during work, the E1 deframer module cycle of FIFO bottom reads the data stored in FIFO; The way of the E1 signal that the selection of E1 deframer module read cycle is selected according to system and setting.
Further, the E1 deframer module cycle reads data fifo, according to data terminal slogan, takes out the data in deframer RAM block, put into common shift register Shift_reg, data shifts, after displacement, data write back in original RAM, deposit each tunnel ends slogan, data, slot count (ts_cnt) in RAM, basic frame count (bf_cnt), multi-frame counting (mf_cnt), position counting (bit_cnt), CRC counts (crc_cnt).Deframer exports LOF, LOM, FAS_ERR, CRC_ERR alarm, port and port solution frame data.Deframer utilizes RAM to deposit all passage ephemeral datas, and such other parts can share, and realize making full use of of logical resource.
Further, separate frame data RAM to output in data buffer storage by Byte and passage.
compared with prior art, beneficial effect of the present invention: it is all the corresponding a set of solution frame system of each road E1 signal that E1 of the prior art separates frame design, namely the E1 signal demand on each road comprises an independently FIFO and E1 deframer module, like this for 16 road E1 signals, just at least need E1 deframer module, and 32 road E1 signals just need 32 E1 deframer modules, along with the increase of system E1 signalling channel, required deframer scale is also more and more huger, and these logical blocks required for huge deframer also increase greatly, and (these deframer functions are all realized by FPGA usually, deframer is more, the logical block of required FPGA inside is more).
The invention provides a kind of multichannel E1 and separate frame system, structure comprises multichannel HDB3 decoder module, multiplexer MUX module, fifo module and E1 deframer module; Wherein multichannel HDB3 decoder module is connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the next device; Multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, the every road E1 of tradition is avoided all to need an independent deframer, greatly saving logical block needed for E1 deframer, for providing highly effective new way based on the bandwidth expansion of E1 signal communication with the speed-raising that communicates, can be applicable in the various communication system based on E1 signal.
Accompanying drawing illustrates:
Fig. 1 is that this multichannel E1 separates frame system structural representation.
Fig. 2 is HDB3 decoder module structural representation.
Fig. 3 is that this multichannel E1 separates frame system method flow schematic diagram.
Fig. 4 is embodiment 1 structural representation.
Fig. 5 is embodiment 2 structural representation.
Embodiment
Below in conjunction with test example and embodiment, the present invention is described in further detail.But this should be interpreted as that the scope of the above-mentioned theme of the present invention is only limitted to following embodiment, all technology realized based on content of the present invention all belong to scope of the present invention.
The object of the invention is to overcome above-mentioned deficiency existing in prior art, a kind of multichannel E1 is provided to separate frame system, multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, avoid the every road E1 of tradition all to need an independent deframer, greatly save logical block needed for E1 deframer.
In order to realize foregoing invention object, the invention provides following technical scheme:
A kind of multichannel E1 separates frame system, as shown in Figure 1, comprises multichannel HDB3 decoder module, multiplexer MUX module, fifo module and E1 deframer module; Wherein multichannel HDB3 decoder module is connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the next device.
Further, described HDB3 decoder module, as shown in Figure 2, comprises HDB3 decoder, Clk-recovery module, cv_check module, Los_det module and ais_det module; Wherein HDB3 decoder is connected with ais_det module respectively with cv_check module, Clk-recovery module, Los_det module;
Zhong Mei road E1 is after HDB3 decoding module decodes in work, detects coded violation, CV respectively, detects dropout (Los) by Los_det module, detect " 1 " (ais) alarm entirely by ais_det module by cv_check module; And directly send alarming processing by above-mentioned loss alarm signal Los, fault alarm signal Cv_err and complete " 1 " alarm signal Ais.
Further, as shown in Figure 2, during work, the Clk-recovery module in HDB3 decoder module, for recovered clock E1_clk_2M rising edge, and then the enable E1_clk_2M_en of the recovered clock generating every road,
Further, the synchronized sampling of E1_clk_2M_en control E1 data E1_data.
The method of work that this kind of multichannel E1 separates frame system comprises following steps as shown in Figure 3:
(1) multi-channel E 1 signal is input to respectively in the HBD3 module on each road;
(2) every road E1 is through HDB3 decoding module decodes, recovers E1 data, detects complete " 1 " alarm signal Ais, loses alarm signal Los, fault alarm signal Cv_err etc., and directly the next device of input processes;
(3) multiplexer MUX module MUX carries out circulating sampling by passage to E1 signal, generates multichannel E1_data serial data stream, and by described E1_data serial data stream write FIFO;
(4) E1 deframer module carries out the process of solution frame from FIFO reading data, detects that the data of LOF, LOM, FAS-ERR, CRC-ERR alarm and passage E1_data output in the next device respectively.
Multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer by native system, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, avoid the every road E1 of tradition all to need an independent deframer, greatly save logical block needed for E1 deframer.
Further, described multiplexer MUX module, the multiplexing clock adopted is identical with passage E1 sampling clock; The data E1_data of the multiplexing every road E1 of loop cycle, adds every road e1 port number, forms multichannel serial data stream and sends into FIFO.
Further, the multi-channel serial data flow of generation is sent in recurrent wrIting FIFO by described multiplexer MUX module.
Further, during work, the E1 deframer module cycle of FIFO bottom reads the data stored in FIFO; The way of the E1 signal that the selection of E1 deframer module read cycle is selected according to system and setting.
Further, the E1 deframer module cycle reads data fifo, according to data terminal slogan, takes out the data in deframer RAM block, put into common shift register Shift_reg, data shifts, after displacement, data write back in original RAM, deposit each tunnel ends slogan, data, slot count (ts_cnt) in RAM, basic frame count (bf_cnt), multi-frame counting (mf_cnt), position counting (bit_cnt), CRC counts (crc_cnt).Deframer exports LOF, LOM, FAS_ERR, CRC_ERR alarm, port and port solution frame data.Deframer utilizes RAM to deposit all passage ephemeral datas, and such other parts can share, and realize making full use of of logical resource.
Further, separate frame data RAM to output in data buffer storage by Byte and passage.
Embodiment 1
System comprises the E1 signal on 16 tunnels, as shown in Figure 4, comprises 16 road HDB3 decoder modules, multiplexer MUX module, fifo module and E1 deframer module; Wherein 16 road HDB3 decoder modules are connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the data cache module of bottom.
Native system comprises 16 road E1 signals.When system comprises 16 road E1 signal, an each channel frequence of 81.92MHz high-frequency clock circulating sampling is adopted to be the E1 signal recuperation Chu Mei road E1 clock E1_clk_2M of 2.048 MHz and every road E1 data E1_data.
Further, when system comprises 16 road E1 signal, described FIFO selects 32*5bit, wherein 4bit port numbers+1 bit data; FIFO selects according to the designing requirement of system.
All the other system configurations and method of work identical with execution mode, repeat no more.
Embodiment 2
System comprises the E1 signal on 32 tunnels, as shown in Figure 5, comprises 32 road HDB3 decoder modules, multiplexer MUX module, fifo module and E1 deframer module; Wherein 32 road HDB3 decoder modules are connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the data cache module of bottom.
Preferably, native system comprises 32 road E1 signals.When system comprises 32 road E1 signals, adopt an each channel frequence of 163.84MHZ high-frequency clock circulating sampling to be the E1 signal of 2.048 MHz, recover every road E1 clock E1_clk_2M and every road E1 data E1_data.
Further, when system comprises 32 road E1 signal, described FIFO selects 32*6bit, wherein 5bit port numbers+1 bit data; FIFO selects according to the designing requirement of system.
All the other system configurations and method of work identical with execution mode, repeat no more.
In a word, it is all the corresponding a set of solution frame system of each road E1 signal that E1 of the prior art separates frame design, namely the E1 signal demand on each road comprises an independently FIFO and E1 deframer module, like this for 16 road E1 signals, just at least need 16 FIFO and 16 E1 deframer modules, and 32 road E1 signals just need at least 32 FIFO and 32 E1 deframer modules, along with the increase of system E1 signalling channel, required deframer scale is also more and more huger, and these logical blocks required for huge deframer also increase greatly, and (these deframer functions are all realized by FPGA usually, deframer is more, the logical block of required FPGA inside is more).
A kind of multichannel E1 separates frame system, and structure comprises multichannel HDB3 decoder module, multiplexer MUX module, fifo module and E1 deframer module; Wherein multichannel HDB3 decoder module is connected with multiplexer MUX module successively; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the next device; Multichannel E1 is separated frame data and is assembled into serial data stream through multiplexer, so only need an E1 deframer, just can carry out E1 and separate frame recovery, reassemble into multi-channel E 1 data, the every road E1 of tradition is avoided all to need an independent deframer, greatly saving logical block needed for E1 deframer, for providing highly effective new way based on the bandwidth expansion of E1 signal communication with the speed-raising that communicates, can be applicable in the various communication system based on E1 signal.
Claims (9)
1. multichannel E1 separates a frame system, it is characterized in that, comprises the HDB3 decoder module of more than 1, multiplexer MUX module, fifo module and E1 deframer module;
Wherein HDB3 decoder module is all connected with multiplexer MUX module; The other end of multiplexer MUX module is connected with one end of fifo module, and the other end of fifo module is connected with one end of E1 deframer module; The other end of E1 deframer module is connected with the next device.
2. a kind of multichannel E1 as claimed in claim 1 separates frame system, it is characterized in that, according to the E1 signalling channel number that system comprises, comprise the HDB3 decoder module of more than 1,2,4,8,16 or 32, wherein said HDB3 decoder module is connected with multiplexer MUX module respectively.
3. a kind of multichannel E1 as claimed in claim 2 separates frame system, it is characterized in that described HDB3 decoder module comprises HDB3 decoder, cv_check module, Los_det module and ais_det module; Wherein HDB3 decoder is connected with ais_det module respectively with cv_check module, Los_det module.
4., in work, every road E1, after HDB3 decoding module decodes, detects whether there is coded violation, CV by cv_check module respectively, detects whether there is Los alarm by Los_det module, detects whether there is full ais alarm signal by ais_det module; And directly send alarming processing by described alarm signal.
5. a kind of multichannel E1 as claimed in claim 3 separates frame system, and it is characterized in that, described HDB3 decoder module also comprises Clk-recovery module, and described Clk-recovery module is connected with HDB3 decoder; When described Clk-recovery module is for the rising edge of recovered clock E1_clk_2M signal being detected, generate the enable E1_clk_2M_en signal of recovered clock.
6. a kind of multichannel E1 as claimed in claim 4 separates frame system, it is characterized in that, system comprises 16 tunnel frequencies when being the E1 signal of 2.048 MHz, adopts 81.92MHz clock frequency to carry out circulating sampling to each channel signal.
7. a kind of multichannel E1 as claimed in claim 6 separates frame system, and it is characterized in that, described FIFO is 5 FIFO; Wherein first 4 is the port numbers of E1 signal, and latter 1 is E1-DATA.
8. a kind of multichannel E1 as claimed in claim 4 separates frame system, it is characterized in that, system comprises 32 tunnel frequencies when being the E1 signal of 2.048 MHz, adopts 163.84MHZ clock frequency to carry out circulating sampling to each channel signal.
9. a kind of multichannel E1 as claimed in claim 7 separates frame system, and it is characterized in that, described FIFO is 6 FIFO; Wherein first 5 is the port numbers of E1 signal, and latter 1 is E1-DATA.
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Application publication date: 20150304 |