CN104393035B - Heterojunction field effect transistor of composite source field plate based on medium modulation - Google Patents
Heterojunction field effect transistor of composite source field plate based on medium modulation Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses a heterojunction field effect transistor of a composite source field plate based on medium modulation. The heterojunction field effect transistor of the composite source filed plate based on the medium modulation is mainly used for solving the problem that the process for realizing high breakdown voltage in the existing field plate technology is complex. The heterojunction field effect transistor comprises a substrate (1), a transitional layer (2), a barrier layer (3), a source electrode (4), a drain electrode (5), a table board (6), a passivation layer (9) and a protective layer (13), wherein a gate slot (7) is etched in the barrier layer between the source electrode and the drain electrode; a grid electrode (8) is deposited in the grid slot (7); a groove (10) is etched in the passivation layer (9) between the grid electrode and the drain electrode; a high dielectric constant medium (11) is completely filled in the groove (10); a source field plate (12) is deposited between the passivation layer (9) and the protective layer (13); the source field plate is electrically connected with a source electrode; and the source field plate (12) and the high dielectric constant medium (11) form a composite source field plate. The heterojunction field effect transistor of the composite source filed plate based on the medium modulation has the advantages of a simple manufacturing process, high breakthrough voltage, high field plate efficiency, high reliability and high yield.
Description
Technical field
The invention belongs to technical field of semiconductor device, more particularly to a kind of multiple source field plate based on medium modulation is heterogeneous
Junction field effect transistor, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years
Come, with becoming increasingly conspicuous for the energy and environmental problem, research and development novel high-performance, low-loss power device become raising electric energy profit
With one of rate, energy saving, the effective way of alleviating energy crisis.However, in power device research, at a high speed, high pressure with it is low
Serious restricting relation is there is between conducting resistance, rationally, to effectively improve this restricting relation be to improve device globality
The key of energy.As market constantly proposes the requirement of higher efficiency, smaller volume, higher frequency, traditional Si base to power system
Semiconductor power device performance has approached its theoretical limit.In order to be able to further reducing chip area, improving operating frequency, improve
Operating temperature, reduction conducting resistance, raising breakdown voltage, reduction machine volume, raising overall efficiency, with gallium nitride as representative
Semiconductor material with wide forbidden band, drifts about by the electronics saturation of its bigger energy gap, higher critical breakdown electric field and Geng Gao
Speed, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioprotective, show one's talent in terms of high performance power device is prepared,
Application potential is huge.Especially with the HEMT of GaN base heterojunction structure, i.e. GaN base HEMT device, more
It is, because of characteristics such as its low on-resistance, senior engineer's working frequencies, electronics of future generation to be met more high-power to power device, higher
The requirement of frequency, smaller volume and more severe hot operation, has wide and special application prospect in economy and military field.
However, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field intensity can be caused in deformity
, especially there is high peak electric field near vicinity in device grids in distribution.Cause hitting for actual GaN base HEMT device
Voltage is worn often far below theoretical eapectation, and there is the integrity problems such as current collapse, inverse piezoelectric effect, seriously constrain
Application and development in field of power electronics.In order to solve problem above, domestic and international researchers propose numerous methods, and field
Hardened structure be wherein effect significantly, one kind for being most widely used.N.Q.Zhang of U.S. UCSB in 2000 et al. is first
Field plate structure is successfully applied in GaN base HEMT power device, overlapping gate device is developed, saturation output current is 500mA/
Mm, up to 570V, this is reported breakdown voltage highest GaN device at that time to breakdown voltage, referring to High
breakdown GaN HEMT with overlapping gate structure,IEEE Electron Device
Letters,Vol.21,No.9,pp.421-423,2000.Subsequently, research institution of various countries expands the research work of correlation one after another
Make, and the U.S. and Japan are the main leaders in the field.In the U.S., mainly UCSB, Nan Ka university, Cornell University with
And famous IR companies of power electronic devices manufacturer etc. are engaged in the research.Japan is relative to start late, but they are to this side
The work in face is paid much attention to, fund input great efforts, and it is numerous to be engaged in mechanism, including：Toshiba, Furukawa, Panasonic, Toyota and Fuji etc.
Major company.With going deep into for research, researchers have found correspondingly to increase field plate length, can improve device electric breakdown strength.But
The increase of field plate length can make field plate efficiency, i.e. breakdown voltage than field plate length, constantly reduce, that is, field plate improves device and hits
The ability of voltage is worn as the increase of field plate length gradually tends to saturation, referring to Enhancement of breakdown
voltage in AlGaN/GaN high electron mobility transistors using a field plate,
IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521,2001, and
Development and characteristic analysis of a field-plated Al2O3/AlInN/GaN MOS
HEMT,Chinese Physics B,Vol.20,No.1,pp.0172031-0172035,2011.Therefore, in order to further carry
High device electric breakdown strength, while taking into account field plate efficiency, Wataru Saito of Toshiba Corp in 2008 et al. adopt grid field
The double-deck field plate structure of plate and source field plate have developed double-deck field plate insulated-gate type GaN base HEMT device, the device electric breakdown strength
Up to 940V, maximum output current are up to 4.4A, referring to A 130-W Boost Converter Operation Using a
High-Voltage GaN-HEMT,IEEE Electron Device Letters,Vol.29,No.1,pp.8-10,2008。
This double-deck field plate structure has become current in the world for improving GaN base power device breakdown characteristics, improves device globality
The main flow field plate techniques of energy.However, the complex process of GaN base bilayer field plate HEMT device, manufacturing cost is higher, each layer of field plate
Making be required for photoetching, deposit metal, the deposit processing step such as dielectric passivation.And dielectric material under each layer field plate will be optimized
Thickness is maximized with realizing breakdown voltage, it is necessary to is carried out loaded down with trivial details process debugging and optimization, therefore is considerably increased device manufacture
Difficulty, reduce the yield rate of device.
The content of the invention
It is an object of the invention to overcome the shortcomings of above-mentioned prior art, there is provided a kind of manufacturing process is simple, breakdown voltage
The high multiple source field plate heterojunction field effect transistor based on medium modulation of high, field plate efficiency high and reliability, to reduce device
The manufacture difficulty of part, improves the breakdown characteristics and reliability of device, improves the yield rate of device.
For achieving the above object, the device architecture that the present invention is provided is different using GaN base semiconductor material with wide forbidden band composition
Matter junction structure, includes from bottom to top：Substrate, transition zone, barrier layer, passivation layer and protective layer, deposit above barrier layer active
Table top is carved with pole, drain electrode, the side of barrier layer, and land depth is more than the thickness of barrier layer, gesture between the source and drain
Grid groove is carved with barrier layer, grid is deposited with grid groove, it is characterised in that：Groove is carved with passivation layer, is filled up completely with groove
There is high dielectric constant；Active field plate is deposited between passivation layer and protective layer, the source field plate is electrically connected with source electrode, and source field
Plate constitutes multiple source field plate structure with high dielectric constant.
Preferably, thickness of depth h of described grid groove less than barrier layer, the distance between grid and grid groove left end r1
For 0～2 μm, the distance between grid and grid groove right-hand member r2For 0～3 μm, and r1≤r2。
Preferably, described depth of groove s is 0.29～10.1 μm, width b is 0.66～8.6 μm.
Preferably, the distance between described bottom portion of groove and barrier layer d is 0.087～0.99 μm.
Preferably, described groove is near close the distance between the lateral edges that drain of one lateral edges of drain electrode and source field plate
C is 0.84～10.4 μm.
Preferably, described groove is near close the distance between the lateral edges a that drains of one lateral edges of grid and grid
For s × (d+s × ε1/ε2)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε1For passivation layer
Relative dielectric constant, ε2For the relative dielectric constant of high dielectric constant.
Preferably, the relative dielectric constant ε of described passivation layer1With the relative dielectric constant ε of high dielectric constant2
Span be 1.5～2000, and ε1<ε2。
For achieving the above object, the present invention makes the multiple source field plate heterojunction field effect transistor based on medium modulation
Method, including following process：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate form transition zone；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone form barrier layer；
3rd step, makes mask on barrier layer for the first time, using the mask barrier layer two ends deposit metal, then
N2Rapid thermal annealing is carried out in atmosphere, source electrode and drain electrode is made respectively；
4th step, second making mask on barrier layer, using barrier layer of the mask on the left of source electrode, on the right side of drain electrode
On perform etching, and etched area depth be more than barrier layer thickness, formed table top；
5th step, makes mask on barrier layer for the third time, using in mask barrier layer between the source and drain
Perform etching, make grid groove, depth h of grid groove is less than the thickness of barrier layer；
6th step, on barrier layer, the 4th making mask, deposits metal in grid groove using the mask, makes grid,
Grid is with grid groove left end apart from r1For 0～2 μm, grid is with grid groove right-hand member apart from r2For 0～3 μm, and r1≤r2；
7th step, respectively in source electrode top, drain electrode top, grid top, other area tops of grid groove and barrier layer
Other area tops deposit passivation layers；
8th step, makes mask the 5th time, in the passivation layer using the mask between grid and drain electrode over the passivation layer
Perform etching, to make depth s as 0.29～10.1 μm, width b is 0.66～8.6 μm of groove, bottom portion of groove and barrier layer
The distance between d be 0.087～0.99 μm, the groove is near one lateral edges of grid and grid between one lateral edges of drain electrode
It is s × (d+s × ε apart from a1/ε2)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε1For blunt
Change the relative dielectric constant of layer, ε2For the relative dielectric constant of high dielectric constant；
9th step, the 6th making mask over the passivation layer, using the mask in the groove depositing high dielectric constant medium,
And high dielectric constant is filled up completely with groove；
Tenth step, makes mask the 7th time, over the passivation layer using on mask passivation layer between the source and drain
With the metal that equal deposition thickness on high dielectric constant is 0.34～2.6 μm, the metal for being deposited is near one lateral edges of drain electrode
It it is 0.84～10.4 μm near drain electrode the distance between one lateral edges c with groove, to form source field plate, then by source field plate and source electrode
Electrical connection, the source field plate form multiple source field plate with high dielectric constant；
11st step, deposits insulating dielectric materials in other area tops of source field plate top and passivation layer, forms protection
Layer, completes the making of whole device.
Device of the present invention with compared with advantages below using the HFET of conventional source field plate：
1. breakdown voltage is further increased.
The present invention due to adopting multiple source field plate structure based on medium modulation, make device it is in running order especially
During working condition in OFF state, barrier layer surface potential is gradually risen from grid to drain electrode, is consumed so as to increased in barrier layer
To the greatest extent area, i.e. high resistance area, area, improve the distribution of depletion region, promote the depletion region between grid and drain electrode in barrier layer to hold
The bigger drain-source voltage of load, so as to substantially increase the breakdown voltage of device.
2. gate leakage current is further reduced, device reliability is improve.
The present invention makes electric field line in device barrier layer depletion region due to adopting the multiple source field plate structure based on medium modulation
Distribution obtained more effective modulation, in device grid near drain electrode one lateral edges, source field plate near drain electrode one lateral edges with
And groove can all produce a peak electric field near one lateral edges of drain electrode, and by adjusting the thickness of source field plate underlying passivation layer
Degree, depth of groove and width, the type of high dielectric constant, groove are near one lateral edges of grid and grid near drain electrode side
The distance between edge and source field plate near one lateral edges of drain electrode with groove near the distance between one lateral edges of drain electrode, can be with
So that above-mentioned each peak electric field is equal and less than the breakdown electric field of GaN base semiconductor material with wide forbidden band, so as to greatest extent
The electric field line collected by edge of the grid near drain electrode side is reduced, the electric field at this is significantly reduced, is substantially reduced
Gate leakage current so that the reliability and breakdown characteristics of device is significantly increased.
3. process is simple, it is easy to accomplish, improve yield rate.
The making of source field plate in device architecture of the present invention only needs a step process just can complete, it is to avoid traditional stack layers field plate
The process complications problem brought by structure, substantially increases the yield rate of device.
Simulation result shows that the breakdown voltage of device of the present invention is far longer than the hetero junction field effect using conventional source field plate
Transistor.
The technology contents and effect of the present invention are further illustrated below in conjunction with drawings and Examples.
Description of the drawings
Fig. 1 is the structure chart of the HFET using conventional source field plate；
Fig. 2 is structure chart of the present invention based on the multiple source field plate heterojunction field effect transistor of medium modulation；
Fig. 3 is Making programme figure of the present invention based on the multiple source field plate heterojunction field effect transistor of medium modulation；
Fig. 4 is to electric field curve diagram in the barrier layer obtained by traditional devices and device simulation of the present invention；
Fig. 5 is to puncturing curve chart obtained by traditional devices and device simulation of the present invention.
Specific embodiment
With reference to Fig. 2, the present invention is which includes based on GaN base wide bandgap semiconductor heterojunction structure：Substrate 1, transition zone 2,
Barrier layer 3, source electrode 4, drain electrode 5, table top 6, grid groove 7, grid 8, passivation layer 9, groove 10, high dielectric constant 11, source field plate
12 with protective layer 13., with barrier layer 3 to be distributed from bottom to top, source electrode 4 and drain electrode 5 are deposited on barrier layer 3 for substrate 1, transition zone 2
On, table top 6 is produced on the left of source electrode and drains right side, and the land depth is more than barrier layer thickness, and grid groove 7 is located at source electrode with drain electrode
Between barrier layer in, its depth h be less than barrier layer thickness, grid 8 is deposited in grid groove 7, between grid and grid groove left end
Apart from r1For 0～2 μm, the distance between grid and grid groove right-hand member r2For 0～3 μm, and r1≤r2；Passivation layer 9 is respectively overlay in
Other area tops of source electrode top, drain electrode top, grid top, other area tops of grid groove 7 and barrier layer.Groove 10
In passivation layer 9, depth of groove s is 0.29～10.1 μm, and width b is 0.66～8.6 μm, 10 bottom of groove and barrier layer
The distance between d be 0.087～0.99 μm, high dielectric constant 11 is completely filled in groove 10, and groove 10 is near grid
One lateral edges and grid are near the distance between one lateral edges of drain electrode between a, 10 depth s of groove, 10 bottom of groove and barrier layer
Meet relation a=s × (d+s × ε apart from d1/ε2)0.5, wherein ε1For the relative dielectric constant of passivation layer, ε2It is normal for high dielectric
The relative dielectric constant of number medium.Source field plate 12 is deposited between passivation layer 9 and protective layer 13, and the source field plate 12 is electric with source electrode 4
Gas connects.Source field plate is 0.84～10.4 μm near close the distance between the lateral edges c that drains of one lateral edges of drain electrode and groove,
The source field plate 12 constitutes multiple source field plate structure with high dielectric constant 11.Protective layer 13 is located at 12 top of source field plate and blunt
Change other area tops of layer 9.
The substrate 1 of above-mentioned device adopts sapphire or carborundum or silicon materials；If transition zone 2 is identical or different by dried layer
GaN base semiconductor material with wide forbidden band is constituted, and its thickness is 1～5μm；If barrier layer 3 is prohibited by the identical or different GaN base width of dried layer
Carrying semiconductor material is constituted, and its thickness is 5～50nm；Passivation layer 9 can adopt SiO with protective layer 132、SiN、Al2O3、
HfO2、La2O3、TiO2In any one or other insulating dielectric materials, the thickness of passivation layer is depth s of groove 10 and recessed
The distance between 10 bottom of groove and barrier layer 3 d sums, i.e., 0.377～11.09μm；The thickness of protective layer 13 is 0.36～6.4μm；
High dielectric constant 11 can adopt Al2O3、HfO2、La2O3、TiO2、SrTiO3In any one or other high dielectric it is normal
Number insulating dielectric materials；The relative dielectric constant ε of passivation layer 91With the relative dielectric constant ε of high dielectric constant 112Value
Scope is 1.5～2000, and ε1<ε2；Source field plate 12 is constituted using the combination of three layers of different metal, and its thickness is 0.34～2.6 μ
m。
With reference to Fig. 3, the present invention makes the process of the multiple source field plate heterojunction field effect transistor based on medium modulation, gives
Go out following three kinds of embodiments：
Embodiment one：Making substrate is sapphire, and passivation layer is Al2O3, protective layer is SiO2, high dielectric constant 11
For HfO2, multiple source field plate heterojunction field effect transistor based on medium modulation of the source field plate for Ti/Mo/Au metallic combinations.
In Sapphire Substrate 1, extension GaN material makes transition zone 2, such as Fig. 3 a to step 1. from bottom to top.
Using metal organic chemical vapor deposition technology, in Sapphire Substrate 1, epitaxial thickness is 1 μm of undoped p mistake
Layer 2 is crossed, the GaN material that the transition zone is respectively 30nm and 0.97 μm by thickness from bottom to top is constituted.Extension lower floor GaN material is adopted
Process conditions are：Temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is
4400sccm, gallium source flux are 22 μm of ol/min；The process conditions that extension upper strata GaN material is adopted for：Temperature is 960 DEG C, pressure
It is by force 45Torr, hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 130 μm of ol/min.
Step 2. deposits unadulterated Al in GaN transition layer 20.5Ga0.5N makes barrier layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, in GaN transition layer 2, deposition thickness is 5nm, and al composition is
0.5 undoped p Al0.5Ga0.5N barrier layers 3, the process conditions which adopts for：Temperature is 980 DEG C, and pressure is 45Torr, hydrogen
Flow is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and silicon source flow is 7 μm of ol/min.
Step 3. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
In Al0.5Ga0.5Make mask on N barrier layers 3 for the first time, using electron beam evaporation technique in its two ends deposit gold
Category, then in N2Rapid thermal annealing is carried out in atmosphere, source electrode 4 and drain electrode 5 is made, wherein the metal for being deposited is Ti/Al/Ni/Au
Metallic combination, i.e., be respectively Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μ
m.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket be 200～1000W, evaporation rate
It is less thanThe process conditions that rapid thermal annealing is adopted for：Temperature is 850 DEG C, and the time is 35s.
Step 4. performs etching making table top 6, such as Fig. 3 d on the barrier layer on the right of the source electrode left side with drain electrode.
In Al0.5Ga0.5Second making mask on N barrier layers 3, using reactive ion etching technology in the source electrode left side and leakage
Perform etching on the barrier layer on ultra-Right side, form table top 6, etching depth is 10nm.The process conditions that adopt of etching for：Cl2Stream
Measure as 15sccm, pressure is 10mTorr, and power is 100W.
Making grid groove 7, such as Fig. 3 e are performed etching in step 5. barrier layer between the source and drain.
In Al0.5Ga0.5Make mask on N barrier layers 3 for the third time, using reactive ion etching technology in source electrode and drain electrode
Between barrier layer in perform etching, make grid groove 7, etching depth h is 2nm.The process conditions that adopt of etching for：Cl2Flow is
15sccm, pressure are 10mTorr, and power is 100W.
Step 6. deposits W metal/Au in grid groove 7 and makes grid 8, such as Fig. 3 f.
In Al0.5Ga0.54th making mask on N barrier layers 3, deposits gold using electron beam evaporation technique in grid groove 7
Category, makes grid 8, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni, upper strata be Au, its thickness is
0.039 μm/0.24 μm, the distance between grid and grid groove left end r1For 0 μm, the distance between grid and grid groove right-hand member r2For 0 μ
m.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket be 200～1000W, evaporation rate
It is less than
Step 7. source electrode top, drain electrode top, grid top, other area tops of grid groove and barrier layer other
Area top deposits Al2O3Passivation layer 9, such as Fig. 3 g.
Using atomic layer deposition technology be covered each by source electrode top, drain electrode top, grid top, on other regions of grid groove
Other area tops of portion and barrier layer, complete the Al that deposition thickness is 0.377 μm2O3Passivation layer 9.Deposit passivation layer is adopted
Process conditions be：With TMA and H2O is reaction source, and carrier gas is N2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, gas
Press as 700Pa.
Step 8. performs etching making groove 10, such as Fig. 3 h in the passivation layer between grid 8 and drain electrode 5.
The 5th making mask on passivation layer 9, it is blunt between grid 8 and drain electrode 5 using reactive ion etching technology
Change and perform etching in layer, to make groove 10, its 10 depth s of further groove is 0.29 μm, and width b is 0.66 μm, 10 bottom of groove
It it is 0.087 μm with the distance between barrier layer d, groove 10 is near one lateral edges of grid and grid between one lateral edges of drain electrode
Apart from a be 0.127 μm.The process conditions that adopt of etching for：CF4Flow is 45sccm, O2Flow is 5sccm, and pressure is
15mTorr, power are 250W.
Step 9. deposits HfO in groove 102High dielectric constant 11, and groove 10 is filled up completely with, such as Fig. 3 i.
The 6th making mask on passivation layer 9, deposits HfO using superconducting RF technology in groove 102
High dielectric constant 11, deposited HfO2High dielectric constant 11 will be filled up completely with groove 10.Deposit HfO2High-k
The process conditions that medium 11 is adopted for：Reative cell sputtering pressure is maintained at 0.1Pa or so, O21sccm is respectively with the flow of Ar
And 8sccm, substrate temperature is fixed on 200 DEG C, and Hf targets radio-frequency power is 150W.
Step 10. passivation layer top between the source and drain and 11 top of high dielectric constant deposit metal Ti/
Mo/Au makes source field plate 12, such as Fig. 3 j.
The 7th making mask on passivation layer 9, using electron beam evaporation technique passivation layer between the source and drain
Top and 11 top of high dielectric constant deposit metal, the metal is near one lateral edges of drain electrode with groove near one side of drain electrode
The distance between edge c is 0.84 μm, and it is Mo, upper strata for Ti, middle level that the metal for being deposited is Ti/Mo/Au metallic combinations, i.e. lower floor
For Au, its thickness is 0.15 μm/0.12 μm/0.07 μm, to form source field plate 12, then source field plate is electrically connected with source electrode, should
Source field plate 12 constitutes multiple source field plate with high dielectric constant 11.The process conditions that adopt of deposit metal for：Vacuum is less than
1.8×10-3Pa, power bracket are 200～1000W, and evaporation rate is less than
Step 11. deposits SiO in other area tops of 12 top of source field plate and passivation layer 92Protective layer 13 is made, such as
Fig. 3 k.
Using plasma enhanced CVD technology on other regions of 12 top of source field plate and passivation layer 9
Portion deposits SiO2Protective layer 13 is made, its thickness is 0.36 μm, so as to complete the making of whole device, deposit what protective layer was adopted
Process conditions are：N2O flows are 850sccm, SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is
1100mTorr。
Embodiment two：Making substrate is carborundum, and passivation layer is SiO2, protective layer is SiN, and high dielectric constant 11 is
Al2O3, multiple source field plate heterojunction field effect transistor based on medium modulation of the source field plate for Ti/Ni/Au metallic combinations.
Step one. in silicon carbide substrates 1, extension AlN makes transition zone 2, such as Fig. 3 a with GaN material from bottom to top.
1.1) using metal organic chemical vapor deposition technology, in silicon carbide substrates 1, epitaxial thickness is not mixing for 50nm
Miscellaneous AlN materials；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm,
Ammonia flow is 4600sccm, and silicon source flow is 5 μm of ol/min；
1.2) using metal organic chemical vapor deposition technology, on AlN materials, epitaxial thickness is 2.45 μm of GaN materials
Material, completes the making of transition zone 2；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow are 4600sccm, and gallium source flux is 130 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 20.3Ga0.7N and GaN material make barrier layer 3, such as Fig. 3 b.
2.1) using metal organic chemical vapor deposition technology, on transition zone 2, deposition thickness is that 27nm, al composition are
0.3 Al0.3Ga0.7N materials；The process conditions of its extension are：Temperature is 1300 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow are 4600sccm, and gallium source flux is 16 μm of ol/min, and silicon source flow is 8 μm of ol/min；
2.2) using metal organic chemical vapor deposition technology in Al0.3Ga0.7GaN of the epitaxial thickness for 3nm on N materials
Material, completes the making of barrier layer 3；The process conditions of its extension are：Temperature is 1200 DEG C, and pressure is 46Torr, hydrogen flowing quantity
For 4650sccm, ammonia flow is 4650sccm, and gallium source flux is 18 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 3. source electrode 4 and drain electrode 5, such as Fig. 3 c are made in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
3.1) mask is made for the first time on barrier layer 3, deposit metal, deposit at its two ends using electron beam evaporation technique
Metal be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135 μm/0.046 μm/0.052 μm, its deposit smithcraft condition be：Vacuum is less than 1.8 × 10-3Pa, power bracket is
200～1000W, evaporation rate are less than
3.2) in N2Rapid thermal annealing is carried out in atmosphere, the making of source electrode 4 and drain electrode 5, the work of its rapid thermal annealing is completed
Skill condition is：Temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 4. making table top 6, such as Fig. 3 d are performed etching on barrier layer 3 of the left side of source electrode with the right of drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology on the right of the source electrode left side with drain electrode
Perform etching on barrier layer 3, form table top 6, wherein etching depth is 100nm；Reactive ion etching technology etching table top 6 is adopted
Process conditions be：Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 5. making grid groove 7, such as Fig. 3 e are performed etching in barrier layer between the source and drain.
Make mask on barrier layer 3 for the third time, using reactive ion etching technology potential barrier between the source and drain
Perform etching in layer, make grid groove 7, etching depth h is 20nm.The process conditions that adopt of etching for：Cl2Flow is 15sccm,
Pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 6. W metal/Au is deposited in grid groove 7 and makes grid 8, such as Fig. 3 f.
The 4th making mask on barrier layer 3, in grid groove 7 deposits metal using electron beam evaporation technique, makes grid
Pole 8, wherein the metal for being deposited is Ni/Au metallic combinations, its thickness is 0.039 μm/0.24 μm, between grid and grid groove left end
Apart from r1For 1 μm, the distance between grid and grid groove right-hand member r2For 2 μm.The work that electron beam evaporation technique deposit Ni/Au is adopted
Skill condition is：Vacuum is less than 1.8 × 10-3Pa, power bracket are 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 7. source electrode top, drain electrode top, grid top, other area tops of grid groove 7 and barrier layer its
He deposits SiO by area top2Make passivation layer 9, such as Fig. 3 g.
Source electrode top, drain electrode top, grid top, grid are covered each by using plasma enhanced CVD technology
Other area tops of other area tops and barrier layer of groove 7, complete the SiO that deposition thickness is 6.3 μm2Passivation layer 9；Its
The process conditions for adopting for：N2O flows are 850sccm, SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, is pressed
It is by force 1100mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Step 8. making groove 10, such as Fig. 3 h are performed etching in the passivation layer 9 between grid 8 and drain electrode 5.
The 5th making mask on passivation layer 9, it is blunt between grid 8 and drain electrode 5 using reactive ion etching technology
Change layer in perform etching, to make groove 10, its 10 depth s of further groove be 5.8 μm, width b be 4.5 μm, 10 bottom of groove with
The distance between barrier layer d is 0.5 μm, groove 10 near one lateral edges of grid and grid between one lateral edges of drain electrode away from
It it is 10.068 μm from a；The process conditions that reactive ion etching technology etched recesses 10 are adopted for：CF4Flow is 45sccm, O2Stream
Measure as 5sccm, pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 9. Al is deposited in groove 102O3High dielectric constant 11, and groove 10 is filled up completely with, such as Fig. 3 i.
The 6th making mask on passivation layer 9, deposits Al using atomic layer deposition technology in groove 102O3High dielectric
Constant medium 11, deposited Al2O3High dielectric constant 11 will be filled up completely with groove 10.Deposit Al2O3High dielectric constant
11 process conditions for adopting for：With TMA and H2O is reaction source, and carrier gas is N2, carrier gas flux is 200sccm, and underlayer temperature is 300
DEG C, air pressure is 700Pa.
The deposit of the high dielectric constant of this step is not limited to atomic layer deposition technology, it would however also be possible to employ evaporation technique
Or plasma enhanced CVD technology or sputtering technology or molecular beam epitaxy technique.
Step 10. passivation layer top between the source and drain and 11 top of high dielectric constant deposit metal Ti/
Ni/Au makes source field plate 12, such as Fig. 3 j.
The 7th making mask on passivation layer 9, using electron beam evaporation technique passivation layer between the source and drain
Top and 11 top of high dielectric constant deposit metal, the metal is near one lateral edges of drain electrode with groove near one side of drain electrode
The distance between edge c is 7.1 μm, and it is Ni, upper strata for Ti, middle level that the metal for being deposited is Ti/Ni/Au metallic combinations, i.e. lower floor
For Au, its thickness is 0.8 μm/0.6 μm/0.4 μm, to form source field plate 12, then source field plate is electrically connected with source electrode, the source field
Plate 12 constitutes multiple source field plate with high dielectric constant 11.The process conditions that electron beam evaporation technique deposit Ti/Ni/Au is adopted
For：Vacuum is less than 1.8 × 10-3Pa, power bracket are 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 11. in source, other area tops deposit SiN of 12 top of field plate and passivation layer 9 makes protective layer 13,
Such as Fig. 3 k.
Using plasma enhanced CVD technology on other regions of 12 top of source field plate and passivation layer 9
Portion deposit SiN makes protective layer 13, and its thickness is 3.8 μm, so as to complete the making of whole device；Its process conditions for adopting
For：Gas is NH3、N2And SiH4, gas flow respectively 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure
Respectively 300 DEG C, 25W and 950mTorr.
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Embodiment three：Making substrate is silicon, and passivation layer is SiN, and protective layer is SiO2, high dielectric constant 11 is HfO2,
Multiple source field plate heterojunction field effect transistor based on medium modulation of the source field plate for Ti/Pt/Au metallic combinations.
On silicon substrate 1, extension AlN makes transition zone 2, such as Fig. 3 a with GaN material to step A. from bottom to top.
A1 the use of metal organic chemical vapor deposition technology it is) 800 DEG C in temperature, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and silicon source flow is under the process conditions of 25 μm of ol/min, on silicon substrate 1 outward
Prolong the AlN materials that thickness is 200nm；
A2 the use of metal organic chemical vapor deposition technology it is) 980 DEG C in temperature, pressure is 45Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 130 μm of ol/min, on AlN materials outward
Prolong the GaN material that thickness is 4.8 μm, complete the making of transition zone 2.
Step B. deposits Al on transition zone from bottom to top0.1Ga0.9N makes barrier layer 3, such as Fig. 3 b with GaN material.
B1 the use of metal organic chemical vapor deposition technology it is) 1000 DEG C in temperature, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 13 μm of ol/min, and silicon source flow is the technique of 13 μm of ol/min
Under the conditions of, on transition zone 2, epitaxial thickness is 46nm, the Al that al composition is 0.10.1Ga0.9N materials；
B2 the use of metal organic chemical vapor deposition technology it is) 1000 DEG C in temperature, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, in Al0.1Ga0.9N materials
Upper epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in 3 two ends of barrier layer deposit metal Ti/Al/Ni/Au.
C1 mask is made for the first time on barrier layer 3), is less than 1.8 × 10 in vacuum using electron beam evaporation technique- 3Pa, power bracket are 200～1000W, and evaporation rate is less thanProcess conditions under, deposit metal, wherein institute at its two ends
The metal of deposit be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135μm/0.046μm/0.052μm；
C2) in N2Atmosphere, temperature are 850 DEG C, and the time, to carry out rapid thermal annealing under the process conditions of 35s, completes source electrode 4
With the making of drain electrode 5.
Step D. performs etching making table top 6, such as Fig. 3 d on the barrier layer 3 on the right of the source electrode left side with drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology in Cl2Flow is 15sccm, pressure
For 10mTorr, under power is for the process conditions of 100W, performs etching on the barrier layer 3 on the right of the source electrode left side with drain electrode, formed
Table top 6, wherein etching depth are 200nm.
Making grid groove 7, such as Fig. 3 e are performed etching in step E. barrier layer between the source and drain.
Make mask on barrier layer 3 for the third time, using reactive ion etching technology in Cl2Flow is 15sccm, pressure
For 10mTorr, under power is for the process conditions of 100W, perform etching in barrier layer between the source and drain, make grid groove
7, its depth h is 30nm.
Step F. deposits W metal/Au in grid groove 7 and makes grid 8, such as Fig. 3 f.
On barrier layer 3, the 4th making mask, is less than 1.8 × 10 in vacuum using electron beam evaporation technique-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, the deposit metal in the grid groove 7 makes grid 8,
The metal for being deposited be Ni/Au metallic combinations, i.e. lower floor be Ni, upper strata be Au, its thickness be 0.039 μm/0.24 μm, grid with
The distance between grid groove left end r1For 2 μm, the distance between grid and grid groove right-hand member r2For 3 μm.
Step G. source electrode top, drain electrode top, grid top, other area tops of grid groove and barrier layer other
Area top deposit SiN materials make passivation layer 9, such as Fig. 3 g.
Using plasma enhanced CVD technology gas be NH3、N2And SiH4, gas flow is respectively
2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, the process conditions of 25W and 950mTorr
Under, form sediment in other area tops of source electrode top, drain electrode top, grid top, other area tops of grid groove and barrier layer
Product thickness is that 11.09 μm of SiN makes passivation layer 9.
Step H. performs etching making groove 10, such as Fig. 3 h in the passivation layer 9 between grid 8 and drain electrode 5.
The 5th making mask on passivation layer 9, using reactive ion etching technology in CF4Flow is 45sccm, O2Flow
For 5sccm, pressure is 10mTorr, under power is for the process conditions of 100W, is carried out in the passivation layer between grid 8 and drain electrode 5
Etching, to make groove 10, its 10 depth s of further groove is 10.1 μm, and width b is 8.6 μm, between 10 bottom of groove and barrier layer
Be 0.99 μm apart from d, groove 10 near one lateral edges of grid and grid near the distance between the lateral edges a that drains is
19.735μm。
Step I. deposits HfO in groove 102High dielectric constant 11, and groove is filled up completely with, such as Fig. 3 i.
On passivation layer 9, the 6th making mask, is protected in reative cell sputtering pressure using superconducting RF technology
Hold in 0.1Pa or so, O21sccm and 8sccm is respectively with the flow of Ar, substrate temperature is fixed on 200 DEG C, Hf target radio-frequency powers
Under for the process conditions of 150W, HfO is deposited in groove 102High dielectric constant 11, deposited HfO2High dielectric constant
11 will be filled up completely with groove 10.
Passivation layer top of step J. between source electrode and drain electrode deposits metal Ti/ with 11 top of high dielectric constant
Pt/Au, makes source field plate 12, such as Fig. 3 j.
On passivation layer 9, the 7th making mask, is less than 1.8 × 10 in vacuum using electron beam evaporation technique-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, the passivation layer top between source electrode and drain electrode
Deposit metal with 11 top of high dielectric constant, the metal near drain electrode one lateral edges and groove near one lateral edges of drain electrode it
Between be 10.4 μm apart from c, it is that Pt, upper strata are that metallic combination of the metal for being deposited for Ti/Pt/Au, i.e. lower floor are Ti, middle level
Au, its thickness are 1.1 μm/0.9 μm/0.6 μm, to form source field plate 12, then source field plate are electrically connected with source electrode, source field plate with
High dielectric constant 11 constitutes multiple source field plate.
Step K. deposits SiO in other area tops of 12 top of source field plate and passivation layer 92, protective layer 13 is made, such as
Fig. 3 k.
Using plasma enhanced CVD technology gas be N2O and SiH4, gas flow is respectively
850sccm and 200sccm, temperature are 250 DEG C, and RF power is 25W, under pressure is for the process conditions of 1300mTorr, in source field plate
Other area tops of 12 tops and passivation layer 9 deposit SiO2Protective layer 13 is made, its thickness is 6.4 μm, whole so as to complete
The making of individual device.
The effect of the present invention can be further illustrated by following emulation.
Emulation 1：Potential barrier to the barrier layer and device of the present invention of the HFET using conventional source field plate
Electric field in layer is emulated, as a result such as Fig. 4, wherein conventional source field plate effective length L and the effective total length of source field plate of the present invention
It is equal.
As seen from Figure 4：Using electric field curve of the HFET of conventional source field plate in barrier layer
2 approximately equalised peak electric fields have been only formed, the area very little covered by its electric field curve in barrier layer, and it is of the invention
Electric field curve of the device in barrier layer defines 3 approximately equalised peak electric fields so that device of the present invention is in barrier layer
The area that covered of electric field curve greatly increase, as the area approximation covered by the electric field curve in barrier layer is equal to device
The breakdown voltage of part, illustrates that the breakdown voltage of device of the present invention is far longer than the hetero junction field effect crystal using conventional source field plate
The breakdown voltage of pipe.
Emulation 2：Breakdown characteristics of the HFET using conventional source field plate with device of the present invention are carried out
Emulation, as a result such as Fig. 5.
As seen from Figure 5, punctured using the HFET of conventional source field plate, i.e., drain current is fast
Speed increases, when drain-source voltage about in 620V, and drain-source voltage of device of the present invention when puncturing is demonstrate,proved about in 1710V
The breakdown voltage of bright device of the present invention is far longer than the breakdown voltage of the HFET using conventional source field plate, should
Conclusion is consistent with the conclusion of accompanying drawing 4.
For those skilled in the art, after present invention and principle has been understood, can be without departing substantially from this
In the case of bright principle and scope, the method according to the invention carries out various amendments and change in form and details, but
These amendments and change based on the present invention are still within the claims of the present invention.
Claims (9)
1. a kind of multiple source field plate heterojunction field effect transistor based on medium modulation, includes from bottom to top：Substrate (1), mistake
Layer (2), barrier layer (3), passivation layer (9) and protective layer (13) are crossed, source electrode (4) is deposited with above barrier layer (3) with drain electrode
(5), table top (6) is carved with the side of barrier layer (3), and land depth is more than the thickness of barrier layer, between the source and drain
Grid groove (7) is carved with barrier layer, grid (8) is deposited with grid groove (7), it is characterised in that：
It is carved with passivation layer (9) in groove (10), groove (10) and is completely filled with high dielectric constant (11)；
Active field plate (12) is deposited between passivation layer (9) and protective layer (13), the source field plate (12) is electrically connected with source electrode (4),
And source field plate (12) constitutes multiple source field plate structure with high dielectric constant (11)；
Groove (10) is s × (d+s × ε near close the distance between the lateral edges a that drains of one lateral edges of grid and grid (8)1/
ε2)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer, ε1For the relative dielectric constant of passivation layer,
ε2For the relative dielectric constant of high dielectric constant.
2. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, its feature exist
The thickness of barrier layer, the distance between grid and grid groove left end r are less than in depth h of grid groove (7)1For 0～2 μm, grid and grid
The distance between groove right-hand member r2For 0～3 μm, and r1≤r2。
3. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, its feature exist
It it is 0.29～10.1 μm in depth s of groove (10), width b is 0.66～8.6 μm；Groove (10) bottom and barrier layer (3) it
Between be 0.087～0.99 μm apart from d, source field plate (12) is near drain electrode one lateral edges and groove (10) near one lateral edges of drain electrode
The distance between c be 0.84～10.4 μm.
4. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, its feature exist
In the relative dielectric constant ε of passivation layer1With the relative dielectric constant ε of high dielectric constant2Span be 1.5～
2000, and ε1<ε2。
5. the multiple source field plate heterojunction field effect transistor based on medium modulation according to claim 1, its feature exist
In substrate (1) using sapphire or carborundum or silicon materials.
6. a kind of method for making the multiple source field plate heterojunction field effect transistor based on medium modulation, comprises the steps：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate (1) form transition zone (2)；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone (2) form barrier layer (3)；
3rd step, makes mask on barrier layer (3) for the first time, deposits metal at the two ends of barrier layer (3) using the mask, then
In N2Rapid thermal annealing is carried out in atmosphere, source electrode (4) and drain electrode (5) is made respectively；
4th step, second making mask on barrier layer (3), using barrier layer of the mask on the left of source electrode, on the right side of drain electrode
On perform etching, and etched area depth be more than barrier layer thickness, formed table top (6)；
5th step, makes mask on barrier layer (3) for the third time, the potential barrier using the mask between source electrode (4) and drain electrode (5)
Perform etching in layer (3), make grid groove (7), depth h of grid groove (7) is less than the thickness of barrier layer；
6th step, the 4th making mask on barrier layer (3), in grid groove (7) deposits metal using the mask, makes grid
(8), grid and grid groove left end apart from r1For 0～2 μm, grid is with grid groove right-hand member apart from r2For 0～3 μm, and r1≤r2；
7th step, respectively source electrode top, drain electrode top, grid top, other area tops of grid groove and barrier layer its
He deposits passivation layer (9) by area top；
8th step, the 5th making mask, the passivation layer (9) using the mask between grid and drain electrode on passivation layer (9)
Inside perform etching, to make depth s as 0.29～10.1 μm, width b is 0.66～8.6 μm of groove (10), groove (10) bottom
The distance between portion and barrier layer (3) d is 0.087～0.99 μm, and the groove is near one lateral edges of grid with grid near drain electrode
The distance between one lateral edges a is s × (d+s × ε1/ε2)0.5, wherein s is depth of groove, and d is between bottom portion of groove and barrier layer
Distance, ε1For the relative dielectric constant of passivation layer, ε2For the relative dielectric constant of high dielectric constant；
9th step, the 6th making mask on passivation layer (9), is situated between in the interior depositing high dielectric constant of groove (10) using the mask
Matter (11), and high dielectric constant (11) is filled up completely with groove (10)；
Tenth step, the 7th making mask on passivation layer (9), using mask passivation layer (9) between the source and drain
On upper and high dielectric constant (11), deposition thickness is 0.34～2.6 μm of metal, and the metal for being deposited is near drain electrode one
Lateral edges a drain lateral edges the distance between c close with groove (10) is 0.84～10.4 μm, to form source field plate (12), then
Source field plate (12) is electrically connected with source electrode (4), the source field plate (12) forms multiple source field plate with high dielectric constant (11)；
11st step, in source, other area tops of field plate (12) top and passivation layer (9) deposit insulating dielectric materials, are formed and are protected
Sheath (13), completes the making of whole device.
7. method according to claim 6, it is characterised in that the passivation layer in the tenth step between the source and drain
The metal of top and the deposit of high dielectric constant top combines Ti/Mo/Au, i.e. lower floor using three-layer metal
Mo, upper strata are Au, and its thickness is 0.15～1.1 μm/0.12～0.9 μm/0.07～0.6 μm.
8. method according to claim 6, it is characterised in that the passivation layer in the tenth step between the source and drain
The metal deposited by top and high dielectric constant top, using three-layer metal combination, Ti/Ni/Au, i.e. lower floor are Ti, middle level
It is Au for Ni, upper strata, its thickness is 0.15～1.1 μm/0.12～0.9 μm/0.07～0.6 μm.
9. method according to claim 6, it is characterised in that the passivation layer in the tenth step between the source and drain
Top and high dielectric constant top deposit metal, further using three-layer metal combination Ti/Pt/Au, i.e. lower floor be Ti,
Middle level is Pt, upper strata is Au, and its thickness is 0.15～1.1 μm/0.12～0.9 μm/0.07～0.6 μm.
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