CN104377181A - Semiconductor packaging part and manufacturing method thereof - Google Patents
Semiconductor packaging part and manufacturing method thereof Download PDFInfo
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- CN104377181A CN104377181A CN201310356276.9A CN201310356276A CN104377181A CN 104377181 A CN104377181 A CN 104377181A CN 201310356276 A CN201310356276 A CN 201310356276A CN 104377181 A CN104377181 A CN 104377181A
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- connection pad
- substrate
- conductive pole
- solder
- corresponding conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a semiconductor packaging part and a manufacturing method of the semiconductor packaging part. The semiconductor packaging part comprises a first substrate, first connecting pads, second connecting pads, a second substrate, a plurality of conductive columns and a plurality of welding fluxes. The second connecting pads and the first connecting pads are formed on the upper surface of the first substrate; the conductive columns are formed on the lower surface of the second substrate; the welding fluxes are formed at the ends of the corresponding conductive columns and are in abutting joint with the second connecting pads and the first connecting pads, and the volumes of the welding fluxes are equal. The distance between the second connecting pads and the conductive columns is larger than that between the first connecting pads and the corresponding conductive columns.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to a kind of semiconductor package part and the manufacture method thereof with conductive pole especially.
Background technology
Conventional semiconductors stacking structure comprises two docking substrates.Each substrate comprises electrical contact.The electrical contact of one substrate docks with the electrical contact of another substrate, and two electrical property of substrates are connected.But each substrate through thermal process, as reflow, and can cause substrate buckling deformation before docking usually.So, after two substrates docking, some electrical contact cannot accurately dock, or the construction profile of electrical contact after docking is good and chap.
Summary of the invention
The invention relates to a kind of semiconductor package part and manufacture method thereof, the electrical contact that can improve between two substrates cannot dock the problem of accurately docking.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a first substrate, one first connection pad, one second connection pad, a second substrate, several conductive pole and several solder.First substrate has a upper surface.Second connection pad is formed on the upper surface of first substrate.The width of the first connection pad is greater than the width of the second connection pad.First connection pad is formed on the upper surface of first substrate.Second substrate has a lower surface.Conductive stud is formed on the lower surface of second substrate.Several solder is formed at the end face of corresponding conductive pole and docks with the second connection pad and the first connection pad, and the volume of each solder is equal.Wherein, the second connection pad and the spacing of corresponding conductive pole are greater than the spacing of the first connection pad and corresponding conductive pole.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.There is provided a first substrate, the upper surface of first substrate is formed with one first connection pad and one second connection pad, wherein the width of the first connection pad is greater than the width of the second connection pad; One second substrate is provided, the lower surface of second substrate is formed with several conductive pole and several solder, each solder is formed at the end face of corresponding conductive pole, and the volume of each solder is equal, and wherein the second connection pad and the spacing of corresponding conductive pole are greater than the spacing of the first connection pad and corresponding conductive pole; And docking first substrate and second substrate, make the second connection pad and the first connection pad dock with conductive pole.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Fig. 2 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 6 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7 A to 7C illustrates the process drawing of the semiconductor package part of Fig. 1.
Main element symbol description:
100,200,300,400,500,600: semiconductor package part
110: first substrate
110u: upper surface
120: the first connection pads
120 ': maximum connection pad
120s, 130s: lateral surface
120u: upper surface
130: the second connection pads
130 ': minimum connection pad
140: second substrate
140b: lower surface
150: conductive pole
150e: end face
160: solder
170: packaging body
H: highly
S1, S2: spacing
Embodiment
Please refer to Fig. 1, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
First substrate 110 is such as chip, wafer, interposer substrate or other kind substrate.First substrate 110 has upper surface 110u, and the first connection pad 120 and the second connection pad 130 are formed on the upper surface 110u of first substrate 110.The width W 1 of the first connection pad 120 is greater than the width W 2 of the second connection pad 130.The plan view shape of the first connection pad 120 can be circle, ellipse, rectangle, trapezoidal or other polygon.In addition, the section shape of the first connection pad 120 can be a circular part (as semicircle), oval a part (as half elliptic), rectangle, trapezoidal or other polygon.The geometric properties of the second connection pad 130, similar in appearance to the first connection pad 120, holds this and repeats no more.In the present embodiment, the amount of warpage of first substrate 110 is close to zero; In other words, the amount of warpage of first substrate 110 is the deformation patterns being not enough to the solder 160 after affecting docking.
Second substrate 140 is such as chip, wafer, interposer substrate, circuit board or other kind substrate.Second substrate 140 has lower surface 140b, and conductive pole 150 is formed on the lower surface 140b of second substrate 140.The height H of each conductive pole 150 can be designed to identical haply, so can reduce design and technologic complexity.Say further, before first substrate 110 docks with second substrate 140, can under after not considering to dock, whether solder 160 there is side direction evagination or necking, height of formation haply mutually level conductive pole 150, on second substrate 140, does not so need the difference design considered especially between each conductive pole 150.
Solder 160 is formed on the end face 150e of corresponding conductive pole 150.The volume of each solder 160 is equal or equal within the scope of foozle haply, so can reduce design and technologic complexity.Say further, before first substrate 110 docks with second substrate 140, can under after not considering to dock, whether solder 160 there is side direction evagination or necking, the identical haply solder 160 of precoating volume, on the end face 150e of conductive pole 150, does not so just need the difference design considered especially between solder 160.
Conductive pole 150 is docked with the first connection pad 120 by solder 160 and docks with the second connection pad 130.With regard to the present embodiment, the middle part of second substrate 140 is given prominence to toward the direction warpage away from first substrate 110, make the spacing of the conductive pole 150 more near second substrate 140 middle part and corresponding connection pad larger, and more away from the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the second connection pad 130 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad (first connection pad 120 and the second connection pad 130) is arrange in ascending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.
Due to the second connection pad 130 that the place's configuration compared with Large space S1 is less, and first connection pad 120 larger compared with place's configuration of Small Distance S2, make solder 160 that constriction or side direction evagination phenomenon not easily occur.Specifically, this a little second connection pad 130 comprises a minimum connection pad 130 ', and with regard to conductive pole 150 and minimum connection pad 130 ', the place due to maximum spacing S1 ' configures the second minimum connection pad 130 ', make solder 160 can be coated to the lateral surface 130s of minimum connection pad 130 ', and avoid constriction to occur.With regard to structure, the external diameter of the solder 160 between minimum connection pad 130 ' and conductive pole 150 is from the end face 150e of conductive pole 150 toward the direction convergent of the bottom of minimum connection pad 130 '.
This little first connection pad 120 comprises a maximum connection pad 120 '.With regard to conductive pole 150 and maximum connection pad 120 ', because minimum spacing part configures maximum connection pad 120 ', make solder 160 can be coated to the lateral surface 120s of maximum connection pad 120 ', and avoid solder 160 that the problem of side direction evagination occurs.With regard to structure, the external diameter of the solder 160 between maximum connection pad 120 ' and conductive pole 150 is from the end face 150e of conductive pole 150 toward the direction flaring of the bottom of maximum connection pad 120 '.
If when constriction or side direction evagination occur solder 160, solder 160 easily chaps, and causes reliability to decline.Can not be there is excessive constriction or excessive sideways evagination in the solder 160 due to the present embodiment, therefore can reduce the probability that be full of cracks occurs solder 160, and then promote the reliability of electrical quality and semiconductor package part 100.
In first substrate 110 with second substrate 140 docking operation, conductive pole 150 is minimum with the spacing of maximum connection pad 120 ', and the solder 160 being therefore positioned at the end face 150e of conductive pole 150 contacts with maximum connection pad 120 ' at first.After contact, because the width of maximum connection pad 120 ' is large, the more volume of solder of tolerable is laterally toward two sides of the upper surface 120u of maximum connection pad 120 ' to extending (namely, the quantitative change of caving in of solder is large) and be coated to the lateral surface 120s of maximum connection pad 120 ', and then make first substrate 110 and second substrate 140 more easily straightly close.Thus, the solder 160 on conductive pole 150 is larger with the second connection pad 130(spacing) just can contact and successfully dock.
Packaging body 170 is formed between first substrate 110 and second substrate 140, and coated with conductive post 150 and solder 160, to protect this little element.Packaging body 170 can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.Packaging body 170 also can comprise suitable filler, such as, be the silicon dioxide of powdery.Several encapsulation technologies can be utilized to form packaging body 170, such as, be compression forming (compression molding), liquid encapsulation type (liquid encapsulation), injection moulding (injection molding) or metaideophone shaping (transfer molding).
Please refer to Fig. 2, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
In the present embodiment, second substrate 140 is given prominence to toward the direction warpage close to first substrate 110, make more near the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the first connection pad 120 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in descending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.Due to the second connection pad 130 that the place's configuration compared with Large space S1 is less, and first connection pad 120 larger compared with place's configuration of Small Distance S2, make solder 160 that constriction or side direction evagination phenomenon not easily occur.
Please refer to Fig. 3, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 300 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
In the present embodiment, the amount of warpage of second substrate 140 is close to zero; In other words, the amount of warpage of second substrate 140 is the deformation patterns being not enough to affect solder 160.
The middle part of first substrate 110 is given prominence to toward the direction warpage away from second substrate 140, make the spacing of the conductive pole 150 more near the middle part of second substrate 140 and corresponding connection pad larger, and more away from the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the second connection pad 130 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in ascending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.Due to the second connection pad 130 that the place's configuration compared with Large space S1 is less, and first connection pad 120 larger compared with place's configuration of Small Distance S2, make solder 160 that constriction or side direction evagination phenomenon not easily occur.
Please refer to Fig. 4, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 400 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
With the first substrate 110 of Fig. 3 unlike, the first substrate 110 of the present embodiment is given prominence to toward the direction warpage close to second substrate 140, make more near the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the first connection pad 120 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in descending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.Due to the second connection pad 130 that the place's configuration compared with Large space S1 is less, and first connection pad 120 larger compared with place's configuration of Small Distance S2, make solder 160 that constriction or side direction evagination phenomenon not easily occur.
Please refer to Fig. 5, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 500 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
In the present embodiment, the middle part of first substrate 110 and the middle part of second substrate 140 are given prominence to toward direction warpage away from each other, make the spacing of the conductive pole 150 more near the middle part of second substrate 140 and corresponding connection pad larger, and more away from the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the second connection pad 130 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in ascending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.Due to second connection pad 130 less compared with the configuration of Large space S1 part, and first connection pad 120 larger compared with the configuration of Small Distance S2 part, make solder 160 that constriction or side direction evagination phenomenon not easily occur.
Please refer to Fig. 6, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 600 comprises first substrate 110, several first connection pad 120, several second connection pad 130, second substrate 140, several conductive pole 150, several solder 160 and packaging body 170.
With the semiconductor package part 500 of Fig. 5 unlike, give prominence in the middle part of the middle part of the first substrate 110 of the present embodiment and second substrate 140 toward close to direction warpage each other, make more near the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.In the present embodiment, more the first connection pad 120 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in descending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.Due to second connection pad 130 less compared with the configuration of Large space S1 part, and first connection pad 120 larger compared with the configuration of Small Distance S2 part, make solder 160 that constriction or side direction evagination phenomenon not easily occur.
Please refer to Fig. 7 A to 7C, it illustrates the process drawing of the semiconductor package part 100 of Fig. 1.
As shown in Figure 7 A, first substrate 110 is provided.First substrate 110 has upper surface 110u, upper surface 110u is formed with several first connection pad 120 and several second connection pad 130, and wherein this little first connection pad 120 comprises a maximum connection pad 120 ', and this little second connection pad 130 comprises a minimum connection pad 130 '.
As shown in Figure 7 A, second substrate 140 is provided.Second substrate 140 has lower surface 140b, lower surface 140b is formed with several conductive pole 150 and several solder 160, and wherein each solder 160 is formed on the end face 150e of corresponding conductive pole 150.The height of each conductive pole 150 is equal or equal in foozle haply, and the volume of each solder 160 is equal or equal in foozle haply.
In the present embodiment, the middle part of second substrate 140 is given prominence to toward the direction warpage away from first substrate 110, make the spacing of the conductive pole 150 more near the middle part of second substrate 140 and corresponding connection pad larger, and more away from the conductive pole 150 of second substrate 140 middle part and the spacing of corresponding connection pad less.Therefore, more the second connection pad 130 is configured near the middle part of first substrate 110, and more configure the second connection pad 130 away from first substrate 110 middle part, that is, connection pad is arrange in ascending mode from first substrate 110 middle part to edge, makes the second connection pad 130 and the interval S 1 of corresponding conductive pole 150 be greater than the interval S 2 of the first connection pad 120 and corresponding conductive pole 150.
As shown in Figure 7 B, docking first substrate 110 and second substrate 140, make solder 160 dock with connection pad.Because maximum connection pad 120 ' is nearest with the spacing of conductive pole 150, therefore maximum connection pad 120 ' contacts at first with the solder 160 ' on corresponding conductive pole 150.Because the external surface area of maximum connection pad 120 ' is large, therefore the more volume of solder of tolerable is laterally toward two sides of the upper surface 120u of maximum connection pad 120 ' to extending (quantitative change of caving in of solder 160 is large), makes first substrate 110 and second substrate 140 more easily straightly close.Thus, when first substrate 110 continues closer to each other with second substrate 140, the solder 160 on conductive pole 150 just can contact with minimum connection pad 130 ' and successfully dock.
As seen in figure 7 c, due to second connection pad 130 less compared with the configuration of Large space S1 part, and first connection pad 120 larger compared with the configuration of Small Distance S2 part, making first substrate 110 and second substrate 140 after docking, not easily there is constriction or side direction evagination phenomenon in solder 160.
Then, the packaging body 170 of Fig. 1 can be formed between first substrate 110 and second substrate 140, and coated first connection pad 120, second connection pad 130, conductive pole 150 and solder 160.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (10)
1. a semiconductor package part, is characterized in that, comprising:
One first substrate, has a upper surface;
One first connection pad, is formed on this upper surface of this first substrate;
One second connection pad, is formed on this upper surface of this first substrate, and the width of this second connection pad is less than the width of this first connection pad;
One second substrate, has a lower surface; And
Several conductive pole, is formed on this lower surface of this second substrate; And
Several solder, be formed at the end face of this corresponding conductive pole and dock with this second connection pad and this first connection pad, respectively the volume of this solder is equal;
Wherein, this second connection pad and the spacing of this corresponding conductive pole are greater than the spacing of this first connection pad and this corresponding conductive pole.
2. semiconductor package part as claimed in claim 1, is characterized in that, this second substrate and this second substrate at least one warpage.
3. semiconductor package part as claimed in claim 2, is characterized in that, the middle part of the middle part of this first substrate and this second substrate is given prominence to toward close to direction each other.
4. semiconductor package part as claimed in claim 2, is characterized in that, the middle part of the middle part of this first substrate and this second substrate is given prominence to toward direction away from each other.
5. semiconductor package part as claimed in claim 2, is characterized in that, the amount of warpage of the one of this first substrate and this second substrate close to zero, and the middle part of the another one of this first substrate and this second substrate past away from or close to the direction warpage of this person.
6. semiconductor package part as claimed in claim 1, it is characterized in that, comprise this second connection pad several, those second connection pads comprise a minimum connection pad, and the external diameter of this solder between this minimum connection pad and this corresponding conductive pole is from the end face of this corresponding conductive pole toward the direction convergent of the bottom of this minimum connection pad.
7. semiconductor package part as claimed in claim 1, it is characterized in that, comprise this first connection pad several, those first connection pads comprise a maximum connection pad, and the external diameter of this solder between this maximum connection pad and this corresponding conductive pole is from the end face of this corresponding conductive pole toward the direction flaring of the bottom of this maximum connection pad.
8. a manufacture method for semiconductor package part, is characterized in that, comprising:
There is provided a first substrate, the upper surface of this first substrate is formed with one first connection pad and one second connection pad, wherein the width of this second connection pad is less than the width of this first connection pad;
One second substrate is provided, the lower surface of this second substrate is formed with several conductive pole and several solder, respectively this solder is formed at the end face of this corresponding conductive pole, respectively the volume of this solder is equal, and wherein this second connection pad and the spacing of this corresponding conductive pole are greater than the spacing of this first connection pad and this corresponding conductive pole; And
Dock this first substrate and this second substrate, this second connection pad and this first connection pad are docked with those conductive poles.
9. manufacture method as claimed in claim 8, is characterized in that, this second substrate and this second substrate at least one warpage.
10. manufacture method as claimed in claim 8, it is characterized in that, this upper surface of this first substrate is formed with this second connection pad several and this first connection pad several, those second connection pads comprise a minimum connection pad, and the external diameter of this solder between this minimum connection pad and this corresponding conductive pole is from the end face of this corresponding conductive pole toward the direction convergent of the bottom of this minimum connection pad; Those first connection pads comprise a maximum connection pad, and the external diameter of this solder between this maximum connection pad and this corresponding conductive pole is from the end face of this corresponding conductive pole toward the direction flaring of the bottom of this maximum connection pad.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310356276.9A CN104377181B (en) | 2013-08-15 | 2013-08-15 | Semiconductor package assembly and a manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310356276.9A CN104377181B (en) | 2013-08-15 | 2013-08-15 | Semiconductor package assembly and a manufacturing method thereof |
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| CN104377181A true CN104377181A (en) | 2015-02-25 |
| CN104377181B CN104377181B (en) | 2018-06-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298731A (en) * | 2015-06-24 | 2017-01-04 | 三星电子株式会社 | Circuit board and the semiconductor package part including this circuit board |
| CN107591383A (en) * | 2017-09-15 | 2018-01-16 | 中国电子科技集团公司第五十八研究所 | The detachable curved surface encapsulated structure of BGA device |
| US20210066228A1 (en) * | 2019-08-30 | 2021-03-04 | Advanced Semiconductor Engineering, Inc. | Package structure and method for manufacturing the same |
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