CN104376814A - Driving circuit, driving method, display panel and display device - Google Patents
Driving circuit, driving method, display panel and display device Download PDFInfo
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- CN104376814A CN104376814A CN201410692009.3A CN201410692009A CN104376814A CN 104376814 A CN104376814 A CN 104376814A CN 201410692009 A CN201410692009 A CN 201410692009A CN 104376814 A CN104376814 A CN 104376814A
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Abstract
The invention provides a driving circuit and a driving method thereof, a display panel and a display device, wherein the driving circuit comprises a first transistor, a second transistor, a third transistor and a coupling capacitor; the display panel comprises a plurality of shift register circuits and a plurality of light-emitting driving circuit units which are connected in series, wherein each light-emitting driving circuit unit comprises a driving circuit of 3T1C, and an input end of each light-emitting driving circuit unit is coupled to an output end of the corresponding shift register circuit. The driving circuit provided by the invention has a simple structure and is easy to realize the narrow frame of the display panel; after being coupled with the corresponding shift register circuit, the scanning signal of the line is accessed, and then an Emit control signal can be generated, so that the positive and negative scanning functions can be realized.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of driving circuit and driving method, display panel, display device.
Background technology
In order to compensate between OLED pixel efferent duct, the difference such as threshold value and mobility is on the impact of display characteristic, and OLED pixel needs to design various compensating circuit.And compensating circuit needs peripheral driving circuit to provide input signal according to certain sequential.
When OLED pixel circuit is PMOS circuit, Emit control signal is generally low level signal, mainly contains two kinds of Emit signal generating modes at present: 1. cascade negative pulse shift circuit directly generates; 2. cascade positive pulse shift circuit connects phase inverter and generates.And general cascade negative pulse shift circuit directly generates circuit structure complexity needed for reverse impulse, if can more take up space for the Oxide semiconductor device circuit of the NMOS of bottom gate, narrow frame is caused to be difficult to realize.Use positive pulse shift circuit to connect the design of phase inverter, need the serial connection of two functional circuits, take up space also very large.And if do not add front crystal drive circuit, with the sweep signal of the VSR input end as phase inverter, just need to get sweep signal from next line, thus cannot realize positive and negatively sweeping function.
Summary of the invention
The embodiment of the present invention provides a kind of driving circuit, comprises the first transistor, transistor seconds, third transistor and coupling capacitance, and wherein, the grid of the first end of the first transistor, the first pole plate of coupling capacitance and transistor seconds is connected to first node;
The first end of transistor seconds and the first end of third transistor are connected to Section Point;
The grid of the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input end;
Second end of transistor seconds is coupled to second clock signal end;
The grid of third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal end;
Second pole plate of coupling capacitance is coupled to the 4th clock signal terminal;
Section Point is as the output terminal of described driving circuit.
On the other hand, the embodiment of the present invention also provides the driving method of above-mentioned driving circuit, comprising:
To the first clock signal terminal, the 3rd clock signal terminal input high level, control the first transistor, third transistor are opened, and described the first transistor transferring input signal is to first node, and described third transistor transmission high level signal is to Section Point;
To the 4th clock signal terminal input low level;
The signal generation saltus step of the first clock signal terminal and the input of the 3rd clock signal terminal is low level by high level saltus step, controls the first transistor, third transistor is closed;
To second clock signal end input low level;
4th clock signal generation saltus step, by low transition to high level, is drawn high the current potential of first node, transistor seconds is opened by the boot strap of coupling capacitance, transmission second clock signal is to Section Point.
On the other hand, the embodiment of the present invention also provides a kind of display panel, comprise the multi-stage shift register circuit of series connection and multiple light emission drive circuit unit, light emission drive circuit unit comprises above-mentioned driving circuit, wherein, the input end of described driving circuit is coupled to the output terminal of corresponding shift-register circuit.
On the other hand, the embodiment of the present invention also provides a kind of display device, comprises above-mentioned display panel.
The driving circuit that the embodiment of the present invention provides, only has 3T1C, and structure is simple, is easy to realize narrow frame; After coupling with corresponding shift-register circuit, the sweep signal of access one's own profession, can generate Emit control signal, therefore can realize positive and negatively sweeping function.
Accompanying drawing explanation
Fig. 1 is the driving circuit structure schematic diagram that the embodiment of the present invention one provides;
Fig. 2 is the drive singal sequential chart of the driving circuit that the embodiment of the present invention one provides;
Fig. 3 is the another kind of drive singal sequential chart of the driving circuit that the embodiment of the present invention one provides;
Fig. 4 is the another kind of embodiment of the driving circuit that the embodiment of the present invention one provides;
Fig. 5 is the another kind of driving circuit structure schematic diagram that the embodiment of the present invention two provides;
Fig. 6 is the driving method schematic flow sheet of the driving circuit that the embodiment of the present invention three provides;
Fig. 7 is the display panel schematic diagram that the embodiment of the present invention four provides;
Fig. 8 is the enlarged schematic partial view of the embodiment of the present invention four.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing and not all.
Embodiment one
Figure 1 shows that the driving circuit that the preferred embodiment of the present invention one provides, as shown in Figure 1, comprise the first transistor M1, transistor seconds M2, third transistor M3 and coupling capacitance C1, concrete, the grid of the first end of the first transistor M1, first pole plate of coupling capacitance C1 and transistor seconds M2 is connected to first node Q; The first end of transistor seconds M2 and the first end of third transistor M3 are connected to Section Point N; The grid of the first transistor M1 is coupled to the first clock signal terminal CK1, and the second end is coupled to input end IN; Second end of transistor seconds M2 is coupled to second clock signal end CK2; The grid of third transistor M3 is coupled to the 3rd clock signal terminal CK3, and the second end is coupled to high level signal end VGH; Second pole plate of coupling capacitance C1 is coupled to the 4th clock signal terminal CK4; Section Point N is as the output terminal OUT of described driving circuit.Wherein, the first transistor M1, transistor seconds M2, third transistor M3 are N-type TFT, and first end refers to the source electrode of NTFT, and the second end refers to the drain electrode of NTFT.
Figure 2 shows that a kind of driver' s timing figure of above-mentioned driving circuit, as shown in Figure 2, the first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 can input identical clock signal.Therefore, the annexation of above-mentioned driving circuit, further can the grid of the first transistor M1, second end of transistor seconds M2, the grid of third transistor M3 is coupled to same point, as shown in Figure 4, is the another kind of embodiment of the driving circuit that the embodiment of the present invention one provides.Drive singal sequential shown in composition graphs 2, the principle of work of the driving circuit that embodiment one provides is as follows:
The T1 moment shown in Fig. 2, first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 input high level signal, wherein, first clock signal C K1 controls the first transistor M1 and opens, 3rd clock signal C K3 controls third transistor M3 and opens, signal input part IN input high level signal, first node Q is transferred to through the first transistor M1, third transistor M3 transmits high level signal VGH to Section Point N, make output terminal OUT export high level, and complete high level IN Signal transmissions to Q point.Now, the 4th clock signal terminal CK4 input low level signal.
In the T2 moment, the signal generation saltus step that first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 input, become low level from high level, the first clock signal C K1 controls the first transistor M1 and closes, and the 3rd clock signal C K3 controls third transistor M3 and closes.Due to the existence of the stray capacitance of the first transistor M1 or transistor seconds M2, the current potential of Q point is slightly dragged down with the negative edge arrival of CK1, CK2, is not enough to open M2 completely.Afterwards, the signal generation saltus step that the 4th clock signal terminal CK4 inputs, becomes high level from low level, due to the boot strap of coupling capacitance C1, the current potential of first node Q is driven high along with the arrival of the rising edge of CK4.
In the T3 moment, because the current potential of first node Q is driven high, be enough to transistor seconds M2 is opened, now second clock signal end CK2 still input low level.Transistor seconds M2 transfers to Section Point N the low level signal that second clock signal end CK2 inputs, the also output low level of output terminal OUT.
In the T4 moment, the signal generation saltus step that first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal terminal CK3 input, become high level from low level, the first clock signal C K1 controls the first transistor M1 and opens, and the 3rd clock signal C K3 controls third transistor M3 and opens.Third transistor M3 transmits high level VGH to Section Point N, makes output terminal OUT export high level.Afterwards, the signal generation saltus step that the 4th clock signal terminal CK4 inputs, by high level saltus step to low level.
From the principle of work of above-mentioned driving circuit, the negative edge of the output signal OUT of this driving circuit is controlled by the rising edge of the 4th clock signal C K4, and the rising edge outputing signal OUT is determined by the rising edge of the 3rd clock signal C K3.Coupling capacitance C1 in driving circuit for compensate the first clock signal C K1 or second clock signal CK2 drop-down time, Q point because the first transistor M1 or transistor seconds M2 stray capacitance and by drop-down factor, if electric capacity is too small, transistor seconds M2 may be caused fully to open; If electric capacity crosses the shake that conference causes outputing signal.
Figure 3 shows that the another kind of driver' s timing figure of embodiment one drive circuit.Wherein, the first clock signal terminal CK1 and the 3rd clock signal terminal CK3 of driving circuit input identical clock signal, and second clock signal end CK2 inputs constant low level.
Under the driver' s timing shown in Fig. 3, its principle of work substantially drive principle is as shown in Figure 2 similar, distinctive points is, when the first clock signal terminal CK1 is in the T2 moment, when being low level by high level saltus step, only by the stray capacitance of the first transistor M1, drag down the current potential of first node Q, make Q point current potential be not enough to open transistor seconds M2.The 4th clock signal terminal CK4 input signal by low transition to high level time, by coupling capacitance C1 boot strap, draw high the current potential of first node Q, the capacitance of required coupling capacitance C1 can be more smaller.The drive principle process that driver' s timing shown in other with Fig. 2 is identical does not repeat them here.
Embodiment two
The another kind of driving circuit structure that Fig. 5 provides for the embodiment of the present invention two, as shown in Figure 5, comprise the first transistor M1, transistor seconds M2, third transistor M3 and coupling capacitance C1, concrete, the grid of the first end of the first transistor M1, first pole plate of coupling capacitance C1 and transistor seconds M2 is connected to first node Q; The first end of transistor seconds M2 and the first end of third transistor M3 are connected to Section Point N; The grid of the first transistor M1 is coupled to the first clock signal terminal CK1, and the second end is coupled to input end IN; Second end of transistor seconds M2 is coupled to second clock signal end CK2; The grid of third transistor M3 is coupled to the 3rd clock signal terminal CK3, and the second end is coupled to high level signal end VGH; Second pole plate of coupling capacitance C1 is coupled to the 4th clock signal terminal CK4; Section Point N is as the output terminal OUT of described driving circuit.Wherein, the first transistor M1, third transistor M3 are P type TFT, and transistor seconds M2 is N-type TFT.Transistor seconds M2DE first end refers to source electrode, and the second end refers to the drain electrode of NTFT.The first end of the first transistor M1 and third transistor M3 refers to drain electrode, and the second end refers to source electrode.
Because the first transistor M1 and third transistor M3 is P type TFT, therefore control its first clock signal C K1 opened and closed and the 3rd clock signal C K3, contrary with the signal of driving circuit shown in embodiment one.
Equally, the driving circuit shown in embodiment two, its first clock signal terminal CK1 and the 3rd clock signal terminal CK3 can be coupled to same point.Therefore it also can have another kind of embodiment.
Further, the driver' s timing of the driving circuit shown in embodiment two, wherein second clock signal CK2, as embodiment one, can be pulsating wave, also can be constant low level value.The drive principle of driving circuit shown in embodiment two is roughly the same with the drive principle of driving circuit shown in embodiment one, and difference is only: the type of the first transistor M1 and third transistor M3 is PTFT, therefore controls its signal value opened and closed contrary.Therefore, the driver' s timing figure of embodiment two is not described in detail.
Embodiment three
As shown in Figure 6, for the driving method of the driving circuit that the preferred embodiment of the present invention provides, wherein, driving circuit structure as shown in Figure 1, comprise the first transistor M1, transistor seconds M2, third transistor M3 and coupling capacitance C1, described first ~ third transistor is N-type TFT, and the grid of the first end of the first transistor M1, first pole plate of coupling capacitance C1 and transistor seconds M2 is connected to first node Q; The first end of transistor seconds M2 and the first end of third transistor M3 are connected to Section Point N; The grid of the first transistor M1 is coupled to the first clock signal terminal CK1, and the second end is coupled to input signal end IN; Second end of transistor seconds M2 is coupled to second clock signal end CK2; The grid of third transistor M3 is coupled to the 3rd clock signal terminal CK3, and the second end is coupled to high level signal VGH; Second pole plate of described coupling capacitance C1 is coupled to the 4th clock signal terminal CK4; Section Point N is as the output signal end OUT of driving circuit.Driving method comprises:
(1) to the first clock signal terminal CK1, the 3rd clock signal terminal CK3 input high level, control the first transistor M1, third transistor M3 open, described the first transistor M1 transferring input signal IN is to first node Q, and described third transistor M3 transmits high level signal VGH to Section Point N; To the 4th clock signal input low level;
The signal generation saltus step that (2) first clock signal terminal CK1 and the 3rd clock signal terminal CK3 input is low level by high level saltus step, controls the first transistor M1, third transistor M3 and closes; To second clock signal end CK2 input low level;
The signal generation saltus step that (3) the 4th clock signal terminal CK4 input, by low transition to high level, drawn high the current potential of first node Q by the boot strap of coupling capacitance C1, transistor seconds M2 is opened, transmission second clock signal CK2 is to Section Point N;
The signal generation saltus step that (4) first clock signal terminal CK1 and the 3rd clock signal terminal CK3 input is high level by low transition, controls the first transistor M1, third transistor M3 and opens.The signal that 4th clock signal terminal CK4 inputs is low level by high level saltus step.
Wherein, in (2) and (3) stage, the first clock signal C K1 to low level, occurs in the 4th clock signal C K4 by before low transition to high level by high level saltus step.And in (4) stage, the first clock signal C K1 to high level, occurs in the 4th clock signal C K4 by before high level saltus step to low level by low transition.The negative edge of output signal OUT is controlled by the rising edge of the 4th clock signal C K4, and the rising edge outputing signal OUT is determined by the rising edge of the 3rd clock signal C K3.
Embodiment four
Figure 7 shows that the display panel that the preferred embodiment of the present invention provides, peripheral in display panel AA district, be provided with panel drive circuit, panel drive circuit comprises multi-stage shift register circuit VSR1, VSR2, VSR3 of series connection ... also comprise multiple light emission drive circuit unit Emit1, Emit2, Emit3 ..., each light emission drive circuit unit comprises the driving circuit that previous embodiment provides.Wherein, every grade of mutual cascade of shift-register circuit VSR, each light emission drive circuit unit is corresponding with every grade of shift-register circuit, and also namely the input end of each light emission drive circuit unit is coupled to the output terminal of every grade of shift-register circuit.
In display panel, the annexation of shift-register circuit VSR and light emission drive circuit unit Emit as shown in Figure 8, wherein, a corresponding shift-register circuit VSR of light emission drive circuit unit Emit, namely the output terminal of shift-register circuit VSR is coupled to the input end of light emission drive circuit unit Emit, light emission drive circuit unit Emit is under the driving of the first clock signal terminal CK1, second clock signal end CK2, the 3rd clock signal C K3, the 4th clock signal C K4 and high level signal VGH, and output terminal OUT exports corresponding low level Emit signal.
Due to, each light emission drive circuit unit is coupled to the shift-register circuit of one's own profession, and therefore, as long as the cascade connection of shift-register circuit itself can realize positive and negatively sweeping function, then this integral panels driving circuit still can realize positive and negatively sweeping function.Moreover the driving circuit structure that light emission drive circuit unit comprises, as shown in embodiment one or embodiment two, only comprises 3T1C, structure is simple, is easy to realize narrow frame design.
Embodiment five
The embodiment of the present invention five provides a kind of display device, and it comprises the display panel described in embodiment four.
It is significant to note that " coupling " of mentioning above, comprises direct or indirect electrical connection.
Obviously, above-described embodiment only for stating the present invention in detail, does not form limiting the scope of the invention.Under design of the present invention, those of ordinary skill in the art is any does not have creative work and the various change carried out and modification, all belongs to the protection domain of the claims in the present invention.
Claims (11)
1. a driving circuit, comprises the first transistor, transistor seconds, third transistor and coupling capacitance, wherein,
The grid of the first end of described the first transistor, the first pole plate of coupling capacitance and transistor seconds is connected to first node;
The first end of described transistor seconds and the first end of third transistor are connected to Section Point;
The grid of described the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input end;
Second end of described transistor seconds is coupled to second clock signal end;
The grid of described third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal end;
Second pole plate of described coupling capacitance is coupled to the 4th clock signal terminal;
Described Section Point is as the output terminal of described driving circuit.
2. driving circuit as claimed in claim 1, it is characterized in that, described the first transistor, transistor seconds and third transistor are N-type TFT.
3. driving circuit as claimed in claim 2, it is characterized in that, the first described clock signal terminal, second clock signal end, the 3rd clock signal terminal input identical clock signal; Or described first clock signal terminal, the 3rd clock signal terminal input identical clock signal, and described second clock signal inputs constant low level.
4. driving circuit as claimed in claim 1, it is characterized in that, described transistor seconds is N-type TFT, and described the first transistor, third transistor are P type TFT.
5. driving circuit as claimed in claim 4, it is characterized in that, described first clock signal terminal, the 3rd clock signal terminal input identical clock signal.
6. a driving method for driving circuit, described driving circuit comprises the first transistor, transistor seconds, third transistor and coupling capacitance, and described first ~ third transistor is N-type TFT, wherein,
The grid of the first end of described the first transistor, the first pole plate of coupling capacitance and transistor seconds is connected to first node;
The first end of described transistor seconds and the first end of third transistor are connected to Section Point;
The grid of described the first transistor is coupled to the first clock signal terminal, and the second end is coupled to input signal end;
Second end of described transistor seconds is coupled to second clock signal end;
The grid of described third transistor is coupled to the 3rd clock signal terminal, and the second end is coupled to high level signal;
Second pole plate of described coupling capacitance is coupled to the 4th clock signal terminal;
Described Section Point is as the output signal end of described driving circuit.
Described driving method comprises:
To the first clock signal terminal, the 3rd clock signal terminal input high level, control the first transistor, third transistor are opened, and described the first transistor transferring input signal is to first node, and described third transistor transmission high level signal is to Section Point;
To the 4th clock signal terminal input low level;
The signal generation saltus step of the first clock signal terminal and the input of the 3rd clock signal terminal is low level by high level saltus step, controls the first transistor, third transistor is closed;
To second clock signal end input low level;
4th clock signal generation saltus step, by low transition to high level, is drawn high the current potential of first node, transistor seconds is opened by the boot strap of coupling capacitance, transmission second clock signal is to Section Point.
7. driving method as claimed in claim 6, is characterized in that, after the saltus step of described 4th clock signal occurs in the saltus step of the first clock signal.
8. driving method as claimed in claim 6, it is characterized in that, described first clock signal terminal, second clock signal end, the 3rd clock signal terminal input identical clock signal; Or described first clock signal terminal, the 3rd clock signal terminal input identical clock signal, and described second clock signal end inputs constant low level.
9. a display panel, comprise the multi-stage shift register circuit of series connection and multiple light emission drive circuit unit, described light emission drive circuit unit comprises as weighed 1 ~ weighs the driving circuit as described in 5 any one, wherein, the input end of described driving circuit is coupled to the output terminal of corresponding shift-register circuit.
10. display panel as claimed in claim 9, is characterized in that, described multi-stage shift register circuit can realize positive and negatively sweeping function.
11. 1 kinds of display device, is characterized in that, comprise display panel as claimed in claim 10.
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| CN201410692009.3A CN104376814B (en) | 2014-11-25 | 2014-11-25 | Driving circuit, driving method, display panel and display device |
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| CN201410692009.3A CN104376814B (en) | 2014-11-25 | 2014-11-25 | Driving circuit, driving method, display panel and display device |
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| CN104952420A (en) * | 2015-07-29 | 2015-09-30 | 武汉华星光电技术有限公司 | Multiplexer, as well as data driving circuit and liquid crystal display panel applying multiplexer |
| CN104977768A (en) * | 2015-07-30 | 2015-10-14 | 武汉华星光电技术有限公司 | Liquid crystal display panel and pixel charging circuit thereof |
| CN107564466A (en) * | 2016-06-30 | 2018-01-09 | 乐金显示有限公司 | Organic light-emitting display device |
| CN108615494A (en) * | 2016-12-13 | 2018-10-02 | 乐金显示有限公司 | Shift register and the gate drivers including shift register and display device |
| WO2020113516A1 (en) * | 2018-12-06 | 2020-06-11 | 深圳市柔宇科技有限公司 | Eoa circuit, display panel, and terminal |
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| CN104952420A (en) * | 2015-07-29 | 2015-09-30 | 武汉华星光电技术有限公司 | Multiplexer, as well as data driving circuit and liquid crystal display panel applying multiplexer |
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| WO2020113516A1 (en) * | 2018-12-06 | 2020-06-11 | 深圳市柔宇科技有限公司 | Eoa circuit, display panel, and terminal |
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| Publication number | Publication date |
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| CN104376814B (en) | 2017-12-26 |
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