CN104362138A - Circuit layout structure - Google Patents
Circuit layout structure Download PDFInfo
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- CN104362138A CN104362138A CN201410488513.1A CN201410488513A CN104362138A CN 104362138 A CN104362138 A CN 104362138A CN 201410488513 A CN201410488513 A CN 201410488513A CN 104362138 A CN104362138 A CN 104362138A
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- metal
- dielectric layer
- circuit layout
- layout structure
- metallic pattern
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Abstract
The invention discloses a circuit layout structure. The circuit layout structure comprises a metal interlayer dielectric layer and a metal pattern, wherein the metal interlayer dielectric layer surrounds a metal inner connecting wire; the metal pattern is positioned in a cutting path; the cutting path is adjacent to the metal interlayer dielectric layer and the metal inner connecting wire; and the metal inner connecting wire or the metal pattern is isolated properly so as to reduce capacitance effect.
Description
The divisional application that the application is the applying date is on November 23rd, 2009, application number is 200910225937.8, denomination of invention is the application for a patent for invention of " a kind of circuit layout structure ".
Technical field
The present invention relates to a kind of circuit layout structure.In specific words, the present invention relates to a kind of special circuit layout structure.In these circuit layout structures, be covered, typically with metal layers a dielectric layer around metal interconnecting suitably isolated with the metallic pattern being arranged in Cutting Road, to lower bad capacity effect.
Background technology
In the manufacture process of semiconductor element, etch process often to be used to set up predetermined figure in predetermined material layer.Fig. 1-Fig. 3 is illustrated in known technology, and the conventional etching procedures of use to set up the process of predetermined pattern in predetermined material layer.First, please refer to Fig. 1, wafer 100 is provided.The material layer having multilayer is set up in advance above wafer 100.Such as, interlayer dielectric layer 110 is positioned on silicon substrate 101, and Metal Contact connector (contact plug) 111, be then arranged in interlayer dielectric layer 110 also by interlayer dielectric layer 110 is surrounded.Dielectric layer between metal layers 120 is positioned at above Metal Contact connector 111, and covers interlayer dielectric layer 110.Etching mask 130 is formed in above dielectric layer between metal layers 120, and has predetermined pattern 131.Etching mask 130 can be the conductive mask of composite layer, such as, containing the metal mask of titanium nitride and tetraethoxysilane (Tetraethoxysilane, TEOS) and/or advanced low-k materials ... etc. composite layer.
Secondly, please refer to Fig. 2, use suitable etchant under plasma environment, etch the dielectric layer between metal layers 120 of below, well predetermined pattern 131 is transferred in dielectric layer between metal layers 120 groove 121 being formed and be used for defining plain conductor downwards, and expose the Metal Contact connector 111 being arranged in interlayer dielectric layer 110, as shown in Figure 2.The groove 121 that these etching programs are formed can be used for being formed the electrical connection of Metal Contact connector 111.
But inventor observes and the groove 121 of not all can expose the Metal Contact connector 111 being arranged in interlayer dielectric layer 110 smoothly, as shown in Figure 3.Some region, some is with the etch residues 113 of electric charge, and such as macromolecular compound cannot leave groove 121 under suitable etchant and plasma environment, has therefore just piled up too much etch residues 113 in groove 121.Too much etch residues 113 blocks the bottom of groove 121, the Metal Contact connector 111 being arranged in interlayer dielectric layer 110 cannot be come out, cause the result of blind window (opening fail).
Inventor infers that one of reason that too much etch residues 113 is piled up is, when carrying out etching step, usually uses electrostatic equipment (not shown) to fix wafer 100.Due to the electrostatic that electrostatic equipment produces, just very possible metal mask 130 of inducing conduction through base material 101, such as titanium nitride mask, the metallic pattern 114 of Cutting Road 103 is arranged in induction, and form a disadvantageous electric capacity, and then bottom the groove 121 attracting too much to be deposited in chip region 102 with the etch residues of electric charge in, and then the Metal Contact connector 111 below it cannot be exposed, more effectively cannot form electrical connection.
So still need a kind of circuit layout structure of novelty, particularly when the contiguous arrangement of metal interconnecting has the Cutting Road of metallic pattern, too much etch residues more to be avoided to block groove and the potential problems of Metal Contact connector of below cannot be exposed, to improve the yield of etching step.
Summary of the invention
The present invention is namely at the circuit layout structure proposing a kind of novelty, too much etch residues can be avoided to block in the trench, the Metal Contact connector of below is made to be difficult to the difficulty come out, especially when the contiguous arrangement of metal mask has the Cutting Road of metallic pattern, too much etch residues can be avoided to be blocked in will be formed in the groove of metal interconnecting, make metal interconnecting and the Metal Contact of below be difficult to form the problem be electrically connected.
First the present invention proposes a kind of circuit layout structure, comprises metal interconnecting, dielectric layer between metal layers, Cutting Road and metallic pattern.Dielectric layer between metal layers, around metal interconnecting, makes in given area, and the area of dielectric layer between metal layers is greater than 9 times of metal interconnecting area.Meanwhile, metallic pattern is arranged in Cutting Road and adjacent metal interlayer dielectric layer and metal interconnecting, makes Cutting Road distance metal interconnecting more than 250 microns.
Secondly the present invention proposes a kind of circuit layout structure, comprises metal interconnecting, dielectric layer between metal layers, Cutting Road and metallic pattern.Dielectric layer between metal layers, around metal interconnecting, makes in given area, and the area of dielectric layer between metal layers is greater than 9 times of metal interconnecting area.Meanwhile, metallic pattern is arranged in Cutting Road, and metallic pattern is positioned at the given area of adjacent metal interlayer dielectric layer and metal interconnecting, and the area of metallic pattern is less than 1/4 times of given area area.
The present invention reintroduces again a kind of circuit layout structure, comprise base material, shallow trench isolation from, metallic pattern, Cutting Road and interlayer dielectric layer.Shallow trench isolation is offed normal in base material, and the metallic pattern being arranged in again Cutting Road is then located immediately at shallow trench isolation from upper, interlayer dielectric layer is positioned on base material and around metallic pattern.
Multiple circuit layout structure proposed by the invention, all can suitably isolate be covered, typically with metal layers a dielectric layer around metal interconnecting region be arranged in the metallic pattern of Cutting Road, so the capacity effect between metal mask and contiguous metallic pattern effectively can be reduced.
Accompanying drawing explanation
Fig. 1-Fig. 3 is illustrated in known technology, and the conventional etching processes of use to set up the process of predetermined pattern in predetermined material layer.
Fig. 4 A illustrates the cutaway view of the first embodiment of circuit layout structure of the present invention.
Fig. 4 B illustrates the vertical view of the first embodiment of circuit layout structure of the present invention.
The cutaway view of structure when Fig. 4 C illustrates the etching of the first embodiment of circuit layout structure of the present invention.
Fig. 5 A illustrates the cutaway view of the second embodiment of circuit layout structure of the present invention.
Fig. 5 B illustrates the vertical view of the second embodiment of circuit layout structure of the present invention.
The cutaway view of structure when Fig. 5 C illustrates the etching of the second embodiment of circuit layout structure of the present invention.
Fig. 6 illustrates the cutaway view of the 3rd embodiment of circuit layout structure of the present invention.
Description of reference numerals
100: wafer
101: base material
102: chip region
103: Cutting Road
110: interlayer dielectric layer
111: metallic pattern
121: contact hole
113: etch residues
114: metallic pattern
120: dielectric layer between metal layers
130: etching mask
131: predetermined pattern
200/300/400: circuit layout structure
201/301/401: base material
210/310/410: interlayer dielectric layer
220/320/420: Metal Contact
230/330/430: Cutting Road
240340/440: metallic pattern
250/350/450: dielectric layer between metal layers
251/351/451: metal interconnecting
252/352: metal mask
253/353: groove
260/360/370: given area
280/380/480: chip region
354: pseudo-ring
402: shallow trench isolation from
Embodiment
The invention provides the circuit layout structure of multiple novelty.In circuit layout structure provided by the present invention, can suitably isolating metal mask be arranged in the metallic pattern of Cutting Road, reduce well the electric charge induction between metal mask and metallic pattern.Therefore can avoid in an etching step, too much etch residues blocks in the trench, hinders etch process to carry out, and makes the Metal Contact connector of below be difficult to the difficulty come out.Especially when the contiguous arrangement of metal mask has the Cutting Road of metallic pattern, not having too much etch residues is blocked in the groove of the dielectric layer between metal layers preparing metal interconnecting, thus can effectively prevent metal interconnecting and be difficult to form the problem be electrically connected with the Metal Contact connector of below.
Fig. 4 A illustrates the cutaway view of the first embodiment of circuit layout structure of the present invention.In the first embodiment of the invention, circuit layout structure 200 comprises base material 201, interlayer dielectric layer (ILD) 210, Metal Contact connector 220, Cutting Road 230, metallic pattern 240, dielectric layer between metal layers (IMD) 250 and metal interconnecting 251.Base material 201 can be semiconductor substrate, such as silicon.Metal interconnecting 251 can be mosaic, such as single mosaic or double-mosaic pattern, and for dielectric layer between metal layers 250 institute around.
In circuit layout structure 200, there is among Cutting Road 230 metallic pattern 240.Interlayer dielectric layer 210 is positioned on base material 210, and around metallic pattern 240.Metallic pattern 240 can comprise metal, particularly tungsten.In addition, interlayer dielectric layer 210 and the dielectric layer between metal layers 250 be positioned on interlayer dielectric layer 210 can comprise one or more dielectric material, such as silica, silicon oxynitride, silicon nitride, tetraethoxysilane and advanced low-k materials respectively, etc.
Although the position of metallic pattern 240 is positioned among Cutting Road 230, contiguous interlayer dielectric layer 210 and metal interconnecting 251.Circuit layout structure of the present invention arranges less metal interconnecting, for example, as shown in Figure 4 B, in given area 260, the area of dielectric layer between metal layers 250 is greater than more than 9 times of metal interconnecting 251 area, metal interconnecting 251 only accounts for less than 10% of given area 260, in the case, if use traditional etching mode, the area of the conductive mask (not shown) used is very big, cause between conductive mask and metallic pattern 240 and serious capacity effect occurs, and then when making to etch, etch residues blocks.
Therefore, for solving capacity effect problem, one of feature of circuit layout structure of the present invention is, arranges metal interconnecting 251, makes metal interconnecting 251 be at least 250 microns from the distance d of Cutting Road 230.Thus, enough large distance makes groove when etching, and what namely the metal interconnecting 251 of Fig. 4 A was affected by capacity effect may reduce to minimum.
Analysis result shows, as shown in Figure 4 C, if the metal mask 252 during etching is positioned at the chip region 280 of contiguous Cutting Road 230, and there is metallic pattern 240 position in Cutting Road 230 near adjacent metal mask 252, particularly bulk or the high tungsten of clustering quantity, because distance d is at least the structural design of 250 microns, reduce electric charge induction, so can not bottom groove 253 in piled up too much etch residues, and the result of the Metal Contact connector 220 being arranged in interlayer dielectric layer 210 can be exposed.
Secondly the present invention proposes another kind of circuit layout structure.Fig. 5 A illustrates the cutaway view of the second embodiment of circuit layout structure of the present invention.In second embodiment of the invention, circuit layout structure 300 comprises base material 301, interlayer dielectric layer (ILD) 310, Metal Contact connector 320, Cutting Road 330, metallic pattern 340, dielectric layer between metal layers (IMD) 350 and metal interconnecting 351.Base material 301 can be semiconductor substrate, such as silicon.Metal interconnecting 351 can be mosaic texture, such as single mosaic or double-mosaic pattern, and dielectric layer between metal layers 350 for institute around.
In circuit layout structure 300, in Cutting Road 330, there is metallic pattern 340.Interlayer dielectric layer 310 is respectively around Metal Contact connector 320 and metallic pattern 340.Metallic pattern 340 can comprise metal, particularly tungsten.In addition, interlayer dielectric layer 310 and dielectric layer between metal layers 350 can comprise one or more dielectric material, such as silica, silicon oxynitride, silicon nitride, tetraethoxysilane and advanced low-k materials respectively, etc.
Further, please refer to Fig. 5 B, illustrate the vertical view of the second embodiment of circuit layout structure of the present invention.Metal interlevel dielectric 350 is around metal interconnecting 351.Metal interconnecting 351 is exactly use conductive mask (not shown) etching metal interlayer dielectric 350 step to add the patterned metal layer that plated metal and planarisation step are formed.Metal interconnecting layer 351 has the shape of bending.The position of metallic pattern 340 is positioned among Cutting Road 330, and the metallic pattern 340 of part likely can adjacent metal interlayer dielectric 350 and metal interconnecting 351.Circuit layout structure of the present invention arranges less metal interconnecting, for example, as shown in Figure 5 B, in given area 360, the area of dielectric layer between metal layers 350 is greater than more than 9 times of metal interconnecting 351 area, metal interconnecting 351 only accounts for less than 10% of given area 360, in the case, if use traditional etching mode, the area of the conductive mask used is very big, by capacity effect serious for the generation caused between conductive mask and metallic pattern 340, and then when making to etch, etch residues blocks.
Therefore, circuit layout structure of the present invention takes the mode reducing metallic pattern 340 area occupied, lower capacity effect, as shown in Figure 5 B, the metallic pattern 340 of adjacent metal interlayer dielectric layer 350 and metal interconnecting 351 again in given area 370, the area of metallic pattern 340 is much smaller than the area of given area 370.Thus, too much metallic pattern 340 is not just had can to produce bad capacity effect with contiguous metal mask (not shown) in given area 370.Preferably, the area of metallic pattern 340 is less than or equal to 1/4 times of given area 370 area.So-called given area 370, refers to the presumptive area including metallic pattern 340.Given area 370 preferably person is rectangle.
Analysis result shows, as shown in Figure 5 C, if the metal mask 352 during etching is positioned at the chip region 380 of contiguous Cutting Road 330, and there is metallic pattern 340 position in Cutting Road 330 near adjacent metal mask 352, may be because aforesaid capacity effect is the most obvious, so the etch residues of the easiest overheap bottom groove 353.But structural design of the present invention, does not have such problem, the Metal Contact 320 in interlayer dielectric layer 310 can come out.Depending on the circumstances or the needs of the situation, the metal mask 352 in Cutting Road 330 can also be designed with pseudo-ring (dummy ring) 354, lowers aforesaid capacity effect.
Metallic pattern 340 can be the metallic pattern that any meeting is arranged in Cutting Road 330, usually formed by metal.Such as metallic pattern 340 can be indicate (activearea box logo), CD bar mark (critical dimension bar logo) or other metal figures for the mark (contact alignmentmark) of contact float, contact mark (contact AIM mark), optics mark (SCM mark), AA, such as cross mark, etc.Above multiple figure can use different modes to reduce the gross area.
Such as, the mark (contact alignment mark) of contact float is quantitatively numerous, such as, during 9 marks, just suitably can reduce the quantity of mark, such as, be reduced to 7 from 9, and under the prerequisite not affecting function, reduce the gross area of mark, or remove it completely.On the other hand, for AA mark or CD bar mark, font can be reduced, or the mode replacing solid object with point-like figure is to reduce the gross area.Further, similarly be cross mark, then hollow figure can be used to replace solid object, reduce the gross area.In other words, as long as under the prerequisite not affecting function, multiple different possible method can be used to reduce the gross area of mark.
The present invention proposes again another kind of circuit layout structure.Fig. 6 illustrates the cutaway view of the 3rd embodiment of circuit layout structure of the present invention.In third embodiment of the invention, circuit layout structure 400 comprise base material 401, shallow trench isolation from 402, interlayer dielectric layer 410, Metal Contact connector 420, Cutting Road 430, metallic pattern 440, dielectric layer between metal layers 450 and metal interconnecting 451.Base material 401 can be semiconductor substrate, such as silicon.
In circuit layout structure 400, shallow trench isolation is positioned among base material 401 from 402.In addition, circuit layout structure 400 li also has Cutting Road 430, makes there is metallic pattern 440 among Cutting Road 430.Namely metallic pattern 440 is located immediately at shallow trench isolation from 402.Metallic pattern 440 can comprise metal, particularly tungsten.Interlayer dielectric layer 410 is positioned on base material 401, and surrounds metallic pattern 440 and Metal Contact connector 420 respectively.Known step can be used to set up shallow trench isolation from 402, and only need revise for setting up the optical mask pattern of shallow trench isolation from 402, this makes circuit layout structure 400 of the present invention compatible with traditional semiconductor technology.
Namely metal interconnecting 451 is positioned on interlayer dielectric layer 410, and adjacent metal figure 440.Metal interconnecting 451 also can by be positioned at equally on interlayer dielectric layer 410 dielectric layer between metal layers 450 institute around.Metal interconnecting 451 and dielectric layer between metal layers 450 may also can together with form mosaic texture, such as single mosaic or double-mosaic pattern.
Interlayer dielectric layer 410 and dielectric layer between metal layers 450 can comprise one or more dielectric material, such as silica, silicon oxynitride, silicon nitride, tetraethoxysilane and advanced low-k materials respectively, etc.It is then Metal Contact connector 420 between base material 401 and metal interconnecting 451.Metal Contact connector 420 can direct contacting metal intraconnections 451.
Analysis result shows, if the metal interconnecting 451 in dielectric layer between metal layers 450 is positioned at the chip region 480 of contiguous Cutting Road 430, and there is metallic pattern 440 position in Cutting Road 430 near adjacent metal intraconnections 451, may be because aforesaid capacity effect is the most obvious, and cause the result that the Metal Contact connector 420 that is arranged in interlayer dielectric layer 410 cannot expose.
In addition, when carrying out etching step, electrostatic equipment (not shown) is usually used to fix wafer.Due to the electrostatic that electrostatic equipment produces, just probably conductive mask (not shown) is induced through base material 401, form a disadvantageous electric capacity with the metallic pattern 440 be positioned among Cutting Road 430, and then attract too much to be deposited in groove (not shown) with the etch residues of electric charge.Because metallic pattern 440 of the present invention is located immediately at shallow trench isolation from 402, namely shallow trench isolation can isolate base material 401 and metallic pattern 440 from 402, makes metallic pattern 440 be not easy to be induced by base material 401.
Thus, due to shallow trench isolation from 402 electrically isolated, conductive mask (not shown), is just not easy to form electric capacity with the metallic pattern 440 be positioned among Cutting Road 430.Even if conductive light mask (not shown) and metallic pattern 440 form electric capacity, also because the thickness of shallow trench isolation from 402, the capacity effect produced is also relatively very little.
The invention provides the multiple circuit layout structure that can lower capacity effect between metal interconnecting and contiguous metallic pattern.Circuit layout structure of the present invention has increases etching yield, avoids etch residues to pile up, causes the advantage of blind window.
The foregoing is only the preferred embodiments of the present invention, all equivalent variations of doing according to the claims in the present invention and modification, all should belong to covering scope of the present invention.
Claims (5)
1. a circuit layout structure, comprises:
Base material;
Shallow trench isolation from, be arranged in this base material;
Metallic pattern, is arranged in Cutting Road, and directly contact this shallow trench isolation from;
And
Interlayer dielectric layer, to be positioned on this base material and around this metallic pattern.
2. circuit layout structure as claimed in claim 1, also comprises:
Metal interconnecting, is positioned on this interlayer dielectric layer and is also close to this metallic pattern; And
Dielectric layer between metal layers, to be positioned on this interlayer dielectric layer and around this metal interconnecting.
3. circuit layout structure as claimed in claim 2, wherein this metal interconnecting forms mosaic texture together with this dielectric layer between metal layers.
4. circuit layout structure as claimed in claim 2, also comprises:
Metal Contact connector, also directly contacts this metal interconnecting between this base material with this metal interconnecting.
5. circuit layout structure as claimed in claim 1, wherein this shallow trench isolation is from this base material of isolation and this metallic pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410488513.1A CN104362138B (en) | 2009-11-23 | 2009-11-23 | Circuit layout structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410488513.1A CN104362138B (en) | 2009-11-23 | 2009-11-23 | Circuit layout structure |
| CN200910225937.8A CN102074548B (en) | 2009-11-23 | 2009-11-23 | Circuit layout structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910225937.8A Division CN102074548B (en) | 2009-11-23 | 2009-11-23 | Circuit layout structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104362138A true CN104362138A (en) | 2015-02-18 |
| CN104362138B CN104362138B (en) | 2017-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410488513.1A Active CN104362138B (en) | 2009-11-23 | 2009-11-23 | Circuit layout structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020037651A1 (en) * | 1999-11-12 | 2002-03-28 | Tzung-Han Lee | Method for minimizing damage of process charging phenomena |
| US20040164418A1 (en) * | 2003-02-25 | 2004-08-26 | Fujitsu Limited | Semiconductor device having a pillar structure |
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| CN1933144A (en) * | 2005-09-13 | 2007-03-21 | 联华电子股份有限公司 | Test key for checking up intraconnection and method for checking intraconnection |
-
2009
- 2009-11-23 CN CN201410488513.1A patent/CN104362138B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020037651A1 (en) * | 1999-11-12 | 2002-03-28 | Tzung-Han Lee | Method for minimizing damage of process charging phenomena |
| US20040164418A1 (en) * | 2003-02-25 | 2004-08-26 | Fujitsu Limited | Semiconductor device having a pillar structure |
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| CN1933144A (en) * | 2005-09-13 | 2007-03-21 | 联华电子股份有限公司 | Test key for checking up intraconnection and method for checking intraconnection |
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| Publication number | Publication date |
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| CN104362138B (en) | 2017-04-12 |
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