CN104355286A - All-silicon MEMS device structure and manufacture method thereof - Google Patents
All-silicon MEMS device structure and manufacture method thereof Download PDFInfo
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Abstract
The invention relates to an all-silicon MEMS (Micro Electro-Mechanical Systems) device. The all-silicon MEMS device consists of a liner SOI silicon chip (17), a structural layer silicon chip (10) and a nut cap SOI silicon chip (16) which are subjected to direct silicon-silicon bonding, and is characterized in that a top silicon (6) of the structural layer silicon chip (10) and the nut cap SOI silicon chip are low-resistance silicon; the top silicon (6) of the nut cap SOI silicon chip is made into an electric interconnection wire and subjected to direct silicon-silicon bonding with the structural layer silicon through a bonding face (5); an electrical signal of the structural layer is led to a silicon electrode (9) in the nut cap SOI silicon chip through the electric interconnection wire and is electrically connected with a pressure welding point (3) on the silicon electrode (9); the silicon electrode (9) is subjected to direct silicon-silicon bonding with the structural layer silicon. The all-silicon MEMS device has the advantages that as the nut cap layer bulk silicon wires are adopted, the structural layer is prevented from pickling splash damage; as twice direct silicon-silicon bonding is adopted, residual stress is eliminated; the direct silicon-silicon bonding is good in airtightness; a getter does not need to be additionally added during vacuum packaging, so that the cost is effectively reduced.
Description
Technical field
The invention belongs to micro-electronic mechanical skill field, particularly a kind of total silicon MEMS structure by block body silicon lead-in wire and manufacture method thereof.
Background technology
MEMS (Micro Electro-Mechanical Systems, MEMS) be the new branch of science grown up on semiconductor integrated circuit basis, MEMS has attracted the extensive concern of people with plurality of advantages such as its miniaturization, low-power consumption, mass productions, is widely used in fields such as automotive electronics, consumer electronics, biomedicine, Aero-Space, information technologies.MEMS market development is in recent years swift and violent, has become a new growth engines.
MEMS processing technology grows up on semiconductor integrated circuit basis, is developed so far the manufacturing process that to be formed with bulk silicon technological and surface sacrificial process be representative.Compared with semiconductor integrated circuit, MEMS generally comprises movable mechanical structure, for bulk silicon technological, bonding techniques generally combines with deep reaction ion etching technology by the processing of movable structure, bonding techniques realizes frame for movement and supports and electric interconnects effect, and deep reaction ion etching technology realizes the release of movable structure etching.Movable mechanical structure is often more fragile, and movable structure volume is small, and skin effect accounts for leading role, and therefore extraneous damping can produce material impact to the forms of motion of movable structure.In order to protect movable structure, avoid environmental damage and provide suitable damping environment, MEMS generally can carry out wafer-level vacuum packaged.For Vacuum Package, its difficult point is the closed environment that namely will ensure movable structure, facilitates electric interconnection line to draw again.
In MEMS technology, the lead-out mode of electricity interconnection line is varied, usually the mode of substrate lead or block lead-in wire can be adopted, substrate lead form is generally the glass substrate splash-proofing sputtering metal gage system based on silicon glass bonding technology or the substrate S OI silicon chip top layer silicon gage system based on Si-Si bonding process, finally utilizes the bonding pattern such as gold silicon eutectic or glass paste to realize Vacuum Package; The block lead-in wire cap splash-proofing sputtering metal be generally based on Si-Si bonding process goes between, and realizes Vacuum Package and electric interconnects by modes such as gold silicon eutectic bondings.MEMS technology method based on silicon glass bonding is simple, but the residual stress after silicon chip and bond glass affects device performance; Based in the processing method of Si-Si bonding process; utilize substrate S OI silicon chip top layer silicon as interconnection line; substrate surface need be covered by silicon dioxide layer of protection; after suspension structure is carved and is led to; backwash phenomenon can be there is in etching Ions Bombardment substrate surface silicon dioxide layer; easily cause the suspension structure back side to produce backwash damage, and utilize the mode of block metal lead wire need add getter when Vacuum Package, cause processing cost greatly to increase.
Summary of the invention
The present invention proposes a kind of total silicon MEMS and its implementation, optimize electric interconnecting pins method in MEMS wafer-level vacuum packaged, this kind of method has simple possible, is easy to the feature realized.
For achieving the above object, the present invention adopts following technical scheme:
A kind of total silicon MEMS, be made up of after Si-Si direct bonding substrate S OI silicon chip, structure sheaf silicon chip and block soi wafer, wherein substrate S OI silicon chip comprises substrate layer, oxygen buried layer and top layer silicon, and block soi wafer comprises substrate layer, oxygen buried layer and top layer silicon, it is characterized in that:
The top layer silicon of structure sheaf silicon chip and block soi wafer adopts N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm;
The top layer silicon of block soi wafer makes electric interconnection line, Si-Si direct bonding is carried out by bonding face and structure sheaf silicon, the signal of telecommunication of this place's structure sheaf is drawn out to the silicon electrode in block soi wafer by electric interconnection line, be connected with the pressure welding point electricity be arranged on silicon electrode, silicon electrode and structure sheaf Si-Si direct bonding;
Structure sheaf carves logical region, corresponding with the shallow slot in the substrate layer that substrate S OI silicon chip is exposed.
In technique scheme, structure sheaf silicon chip and block soi wafer top layer silicon adopt N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm, can be used as electric interconnect conductors, general capacitive device all can adopt this low-resistance silicon as contact conductor, also can adopt this structure to other devices that contact conductor resistivity is not strict with.
Block soi wafer top layer silicon is as electric interconnection line, Si-Si direct bonding is carried out by bonding face and structure sheaf silicon, the signal of telecommunication of this place's structure sheaf is drawn out to silicon electrode by silicon interconnection line, and then be drawn out to pressure welding point, silicon electrode and structure sheaf Si-Si direct bonding, not only ensure pressure welding point sealing but also the signal of telecommunication can be made to draw, chip entirety forms sealing ring by peripheral Si-Si direct bonding, ensures air-tight packaging; Substrate adopts soi wafer, can ensure that device architecture anchor height is consistent; Bottom anchor point, oxygen buried layer plays electric isolution effect between lead-in wire; It is exposed that structure sheaf carves logical sections bottom SOI substrate silicon, and after structure is carved and led to, etching Ions Bombardment substrate silicon, forms shallow slot, can not produce backwash damage to structure sheaf.
The present invention also comprises a kind of MEMS structure implementation method, it is characterized in that comprising following steps:
(1) substrat structure makes: substrate adopts soi wafer, utilizes photoetching technique, ICP deep etching technology forms bonding anchor point, and corrode exposed oxygen buried layer on substrate S OI silicon chip;
(2) structure sheaf makes: structure sheaf soi wafer top layer silicon adopts N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm, Si-Si direct bonding technology is utilized to realize substrate S OI silicon chip and structure sheaf soi wafer bonding, thinning machine or chemical-mechanical polishing mathing is utilized structure sheaf soi wafer substrate silicon to be removed after bonding, subsequently structure sheaf soi wafer oxygen buried layer is eroded, finally utilize photoetching technique, ICP deep etching technology realizes structure release;
(3) block makes: block soi wafer top layer silicon adopts N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm, photoetching technique, ICP deep etching technology is utilized to make shallow chamber and electric interconnection line on block soi wafer top layer silicon surface respectively successively, shallow chamber ensures that movable structure has enough spaces, region etch between interconnection line, to oxygen buried layer, ensures electric isolution between lead-in wire;
(4) to block a shot soi wafer and structure sheaf wafer bonding: utilize Si-Si direct bonding technology to realize blocking a shot the bonding of soi wafer and structure sheaf silicon chip;
(5) open fairlead: utilize photoetching technique, ICP deep etching technology pressure welding point arrange regional block soi wafer substrate silicon is etched to 100 μm ~ 200 μm thick, form deep trouth 18, reduce fairlead vertical height, facilitate later stage wire bonding, again utilize photoetching technique, ICP deep etching technology by clean for substrate silicon etching in fairlead region 2, to oxygen buried layer, fairlead area is less than bottom silicon electrode area, to ensure sealing structure, by clean for oxygen buried layer corrosion in fairlead region, expose pressure welding point.
(6) pressure welding point metallization: utilize magnetron sputtering or evaporation technique to make metal level, utilize photoetching technique, metal erosion technology realizes pressure welding point metal patternization, described metal level can be aluminium lamination or layer gold etc., in described photoetching technique, utilizes glue spraying technology to realize photoresist coating.
MEMS provided by the invention adopts complete silicon structure, and substrate adopts soi wafer, accurately can control anchor height, and around anchor point, oxygen buried layer corrosion is clean, exposed soi wafer substrate silicon, and when can ensure structure release, the structure sheaf back side is without the damage of etching backwash.Utilize Si-Si direct bonding technology layers unsettled, utilize ICP deep etching technology to realize structure release.Block adopts soi wafer to make, and block soi wafer top layer silicon, as electric interconnecting pins, avoids the shortcoming utilizing metal lead wire cannot experience subsequent high temperature processes.The vacuum bonding adopting Si-Si direct bonding technology to realize block soi wafer and structure sheaf encapsulates, without the need to adding getter.Open fairlead from block SOI substrate silicon layer, fairlead area is less than bottom silicon electrode area, can ensure that electrode is drawn and can ensure sealing structure again.
The present invention's advantage compared with traditional MEMS device architecture is: adopt cap body silicon to go between, during the release of structure etching, can exposed substrate silicon bottom structure sheaf, and avoid structure sheaf to etch backwash damage; Adopt twice Si-Si direct bonding to realize device architecture and device wafers level Vacuum Package, complete silicon structure, without residual stress, have essence to improve to device performance; Si-Si direct bonding air-tightness is good, without the need to additionally adding getter during Vacuum Package, can effectively reduce costs; Device architecture implementation method is simple, feasible, is convenient to form standard technology.
Accompanying drawing explanation
Fig. 1 is total silicon MEMS structure sectional view of the present invention;
Fig. 2 is A-A direction view of Fig. 1;
Fig. 3 a-Fig. 3 n is total silicon MEMS structure fabrication processes flow chart of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is described further.
One, MEMS structure:
As shown in Figure 1 and Figure 2, MEMS is formed by substrate S OI silicon chip 17, soi wafer top layer silicon structure sheaf 10, cap soi wafer 16 form.Wherein substrate S OI silicon chip 17 comprises substrate layer 15, oxygen buried layer 12 and top layer silicon 11, and block soi wafer 16 comprises substrate layer 8, oxygen buried layer 4 and top layer silicon 6.
Substrate S OI silicon chip 17 comprises anchor point 11, plays movable structure supporting role, and bottom anchor point 11, oxygen buried layer 12 plays electric isolution effect.
Device structure layer 10 and substrate S OI silicon chip 17 Si-Si direct bonding, in structure etch release process, carve logical region 13 and etch Ions Bombardment substrate silicon 15 surface, form shallow slot structure 14, avoid the backwash damaged structure layer back side.Block soi wafer 16 comprises bonding face 5, electric interconnection line 6, structure such as lead-in wire isolation channel 7, silicon electrode 9 etc., wherein bonding face 5 plays and structure sheaf electricity connection function, the signal of telecommunication is drawn out to pressure welding point by electricity interconnection line 6, isolation channel 7 is etched to oxygen buried layer, ensure the electric isolution between body silicon lead-in wire, silicon electrode 9 plays contact conductor and sealing function, and provides pressure welding point supporting zone; Block soi wafer substrate silicon pressure welding region etch deep trouth 18, reduce fairlead 2 vertical height, facilitate later stage wire bonding, fairlead 2 area is less than bottom silicon electrode area 9, thus ensures sealing structure, and carries out metallization 3 to pressure welding area; Sealed by bonding ring 1 around device.
Two, MEMS structure fabrication processes flow process:
The technical process schematic diagram that in Fig. 3, (a)-(n) is MEMS structure fabrication, specific as follows:
A ()-(c) is the processing process of substrate S OI silicon chip 17, first utilize photoetching, ICP deep etching technology formation anchor point 11, utilize BOE wet etching to remove oxygen buried layer 12 subsequently, make substrate silicon 15 exposed.
D () is device structure layer soi wafer 10 and substrate S OI silicon chip 17 Si-Si direct bonding processed.
E ()-(f) utilizes thinning machine or chemical-mechanical polishing mathing or wet etching to be removed by device structure layer SOI silicon substrate silicon, then eroded by oxygen buried layer.
(g) for utilizing photoetching, ICP lithographic technique carries out structure release etching, forms movable structure after etching.
(h)-be (i) the processing process of block soi wafer 16, first utilize photoetching, ICP deep etching technology forms shallow chamber 16a, ensure movable structure space, recycling photoetching, ICP deep etching technology form the body silicon electricity interconnecting pins 6 of keeping apart.
J () realizes Vacuum Package for device architecture 10 carries out Si-Si direct bonding with block soi wafer 16.
K ()-(m) is that fairlead makes, utilize photoetching respectively, ICP deep etching technology carries out deep etching and fairlead etching to pressure welding point arrange regional, and corrode fairlead oxygen buried layer, expose pressure welding silicon electrode.
Open fairlead: utilize photoetching technique, ICP deep etching technology pressure welding point arrange regional block soi wafer substrate silicon is etched to 100 μm ~ 200 μm thick, form deep trouth 18, reduce fairlead vertical height, facilitate later stage wire bonding, again utilize photoetching technique, ICP deep etching technology by clean for substrate silicon etching in fairlead region 2, to oxygen buried layer, fairlead area is less than bottom silicon electrode area, to ensure sealing structure, by clean for oxygen buried layer corrosion in fairlead region, expose pressure welding point.
N () is pressure welding point metallization, utilize magnetron sputtering to form metal film, utilize photoetching, metal erosion technology realizes pressure welding point metal patternization.
Through above-mentioned technological process, achieve the making of MEMS structure.
Claims (2)
1. a total silicon MEMS, be made up of after Si-Si direct bonding substrate S OI silicon chip (17), structure sheaf silicon chip (10) and block soi wafer (16), wherein substrate S OI silicon chip (17) comprises substrate layer (15), oxygen buried layer (12) and top layer silicon (11), block soi wafer (16) comprises substrate layer (8), oxygen buried layer (4) and top layer silicon (6), it is characterized in that:
The top layer silicon (6) of structure sheaf silicon chip (10) and block soi wafer adopts N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm;
The top layer silicon (6) of block soi wafer makes electric interconnection line, Si-Si direct bonding is carried out by bonding face (5) and structure sheaf silicon, the signal of telecommunication of this place's structure sheaf is drawn out to the silicon electrode (9) in block soi wafer by electric interconnection line, be connected with pressure welding point (3) electricity be arranged on silicon electrode (9), silicon electrode (9) and structure sheaf Si-Si direct bonding;
Structure sheaf (10) carves logical region (13), and the shallow slot (14) in the substrate layer (15) exposed with substrate S OI silicon chip is corresponding.
2. a manufacture method for total silicon MEMS, is characterized in that comprising the following steps:
(1) substrat structure makes: substrate adopts soi wafer, utilizes photoetching technique, ICP deep etching technology forms bonding anchor point, and corrode exposed oxygen buried layer on substrate S OI silicon chip;
(2) structure sheaf makes: structure sheaf soi wafer top layer silicon adopts N-type or P type low-resistance silicon, and typical resistivity 0.001 Ω cm ~ 0.1 Ω cm, utilizes Si-Si direct bonding technology to realize substrate S OI silicon chip and structure sheaf soi wafer bonding;
Thinning machine or chemical-mechanical polishing mathing is utilized structure sheaf soi wafer substrate silicon to be removed after bonding, subsequently structure sheaf soi wafer oxygen buried layer is eroded, finally utilize photoetching technique, ICP deep etching technology carries out structure release etching, after etching, form movable structure;
(3) block makes: block soi wafer top layer silicon adopts N-type or P type low-resistance silicon, typical resistivity 0.001 Ω cm ~ 0.1 Ω cm, first utilize photoetching, ICP deep etching technology forms shallow chamber, ensure movable structure space, recycling photoetching, ICP deep etching technology form the body silicon electricity interconnecting pins of keeping apart, region etch between electricity interconnection line, to oxygen buried layer, ensures electric isolution between electric interconnection line;
(4) to block a shot soi wafer and structure sheaf wafer bonding: utilize Si-Si direct bonding technology to realize blocking a shot the bonding of soi wafer and structure sheaf silicon chip;
(5) fairlead makes: utilize photoetching respectively, ICP deep etching technology carries out deep etching and fairlead etching to pressure welding point arrange regional, and corrode fairlead oxygen buried layer, expose pressure welding silicon electrode;
(6) pressure welding point metallization: utilize magnetron sputtering to form metal film, utilize photoetching, metal erosion technology realizes pressure welding point metal patternization.
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| CN106082108A (en) * | 2015-04-29 | 2016-11-09 | 台湾积体电路制造股份有限公司 | For reducing the structure that dorsal part silicon damages |
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