CN104347762A - Preparation method of LED (Light-Emitting Diode) film chip with meltback layer and structure - Google Patents
Preparation method of LED (Light-Emitting Diode) film chip with meltback layer and structure Download PDFInfo
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- CN104347762A CN104347762A CN201410483425.2A CN201410483425A CN104347762A CN 104347762 A CN104347762 A CN 104347762A CN 201410483425 A CN201410483425 A CN 201410483425A CN 104347762 A CN104347762 A CN 104347762A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 239000012895 dilution Substances 0.000 claims abstract description 13
- 238000010790 dilution Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 7
- 239000000956 alloy Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 180
- 239000010408 film Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 25
- 239000011241 protective layer Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 13
- 229910052697 platinum Inorganic materials 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000009966 trimming Methods 0.000 claims description 3
- 229910019263 Sn—Cu—In Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 238000013517 stratification Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 5
- 230000000903 blocking effect Effects 0.000 abstract 1
- 238000010309 melting process Methods 0.000 abstract 1
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007499 fusion processing Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a preparation method of an LED (Light-Emitting Diode) film chip with a meltback layer and a structure. The preparation method is characterized in that an LED film can be self-flattened in the melting process of the meltback layer by designing the meltback layer which is formed by low-melting-point metal below the LED film and melting the meltback layer through annealing processing after an original growing substrate is removed, so that the effect of sufficiently releasing the residual stress in the LED film is achieved, the reliability and the stability of an LED chip are improved, and the service life of the LED chip is prolonged. Meanwhile, the invention discloses a structure which is obtained from the preparation method, and the structure comprises a substrate, wherein the LED film which comprises a buffer layer, an n-type layer, a luminous layer and a P-type layer is arranged on the substrate, a reflecting contact layer, a blocking layer, a dilution protecting layer and an alloy layer are sequentially deposited on the LED film, and a base-plate front-surface protecting layer, a base plate, a base-plate back-surface protecting layer and a contact layer are arranged on the alloy layer.
Description
Technical field
The invention belongs to semiconductor photoelectric device manufacturing technology field, especially relate to a kind of preparation method and the structure thereof with the LED thin film chip of melt back layer.
Background technology
Semiconductor light-emitting-diode (LED) is that having the advantages such as efficiency is high, the life-span is long, volume is little, voltage is low, is desirable energy saving environmental protection product as the solid-state cold light source of a new generation.At present, LED has been widely used in mobile phone backlight, state instruction, traffic lights, and the field such as large scale display, outdoor lighting, along with the raising of its luminous efficiency and unfailing performance, illumination GaN base LED enters into huge numbers of families gradually.
The epitaxial growth of current GaN base LED film is all adopt metal-organic chemical vapor deposition equipment technology (MOCVD) to carry out in foreign substrate usually.The usual extinction of above-mentioned growth substrates and heat conductivility is poor, therefore has a significant impact the brightness of LED chip and heat radiation.LED film transfer to heat conduction, electric conductivity all preferably substrate will remove former growth substrates according to film transferring technique, then effectively can improving the heat dispersion of LED chip, greatly can also improve the light extraction efficiency of LED chip by preparing the mode such as speculum, surface coarsening.
Because current business-like GaN base LED film grows in foreign substrate usually, and between substrate and epitaxial loayer, there is comparatively Macrolattice mismatch and thermal mismatching, thus in epitaxial loayer, introduce larger stress.For the preparation of LED thin film chip, because former growth substrates removed by needs, make the change of the stress state of LED film in this preparation process more complicated, be difficult to control.If the residual stress in LED film is excessive, the yield of follow-up chip manufacturing and reliability will be subject to larger impact; If the residual stress of obtained LED chip is excessive, can be subject to the impact of expanding with heat and contract with cold that temperature causes in the use procedure of chip, chip is also easy to lose efficacy.Therefore, when preparing LED thin film chip, how effectively the residual stress discharged in LED film needs a technical barrier of solution badly.CN201110026143 patent adopts the way release stress repeatedly shifted, this way repeatedly shifted fully can discharge stress really, but bring the problem that some are new, as: chip moves the problems such as a problem (causing subsequent device photoetching etc. to be difficult to aim at completely) and single chips bulge (causing chip subsequent technique to break),, this all can affect yield and the reliability of chip.
summary of the invention:
First object of the present invention is to provide a kind of preparation method with the LED thin film chip of melt back layer, effectively to discharge residual stress in LED film, improves the stability of LED chip, reliability, life-span and yield, reduces production cost.
Second object of the present invention is the structure providing a kind of LED thin film chip, effectively to discharge residual stress in LED film, improves the stability of LED chip, reliability, life-span and yield, reduces production cost.
First object of the present invention is achieved in that
Have a preparation method for the LED thin film chip of melt back layer, feature is: comprise the following steps:
A, provide substrate, growth comprises the LED film of resilient coating, n-layer, luminescent layer and P-type layer successively over the substrate;
B, on described LED film deposition of reflective contact layer, barrier layer, dilution protective layer, melt back layer and the first bonded layer successively;
C, provide substrate, deposition substrate front protecting layer, the second bonded layer successively in the front of described substrate, at reverse side deposition substrate reverse side protective layer, the contact layer successively of substrate;
D, on described first bonded layer and/or the second bonded layer depositing inter-layer;
E, adopt wafer thermocompression bonding method LED film and substrate to be bound together by intermediate layer, the first bonded layer and the second bonded layer, the temperature of described wafer thermocompression bonding is lower than the fusing point of melt back layer;
F, remove described substrate (complete film transfer, LED film is upside down on substrate);
The convered structure of G, described LED film step F obtained and substrate carries out annealing in process, melt back layer is melted, to discharge stress;
After H, annealing in process, then carry out N-type layer surface coarsening, trimming, passivation, Ohmic electrode preparation, obtained LED thin film chip.
In step B and step D, the fusing point in described intermediate layer is less than the fusing point of melt back layer, and described melt back layer and intermediate layer are the metal or alloy that fusing point is less than the low melting point of 400 DEG C simultaneously.
Preferably, when carrying out step e, below fusing point temperature being risen to more than the fusing point in intermediate layer, melt back layer, making intermediate layer be in molten state when binding, namely melting binding.In binding procedure, make intermediate layer and the first bonded layer, the abundant Reaction-diffusion terms of the second bonded layer, form secondary alloy-layer.
Preferably, when carrying out step G, temperature is raised to more than the fusing point exceeding melt back layer 0 to 150 DEG C, and keeps 1 to 100min.
Preferably, in the annealing process of step G, described melt back layer and described secondary alloy-layer, dilute protective layer and react to each other or diffuseed to form alloy-layer, the physical and chemical performance of described alloy-layer keeps stable at 600 DEG C.
Preferably, the material on described barrier layer is the laminated construction of two or more materials arbitrarily in Cr, Ti, Pt, Au, Ni, W single-layer metal and metal alloy TiW, FeNiCr, FeCoCr, as: Cr/Pt, Cr/Au, Pt/Au/TiW, Pt/Au.
Preferably, described dilution protective layer is the laminated construction of one or more metals in Ag, Ti, Pt, Ni, W, Cu.
Preferably, described melt back layer and described first bonded layer have good wettability and adhesiveness.
Preferably, the material in described intermediate layer is In, and the material of described melt back layer is any one in Sn, Au20Sn80.
Preferably, the material in described intermediate layer is Sn, and the material of described melt back layer is Au20Sn80.
Preferably, the material of described first bonded layer be in Cu, Au, Ag, Al any one.
Preferably, described second bonded layer be in Ti, Cu, Pt, Au, Al, Ag any one.
Described reflecting contact layer in step B, C, barrier layer, dilution protective layer, melt back layer, the first bonded layer, intermediate layer, the second bonded layer, substrate front side protective layer, substrate back side protective layer and contact layer all obtain by evaporation, sputtering, electric plating method.
Second object of the present invention is achieved in that
A kind of structure with the LED thin film chip of melt back layer; comprise substrate; feature is: be formed with the LED film comprising resilient coating, n-layer, luminescent layer and P-type layer over the substrate; LED film is formed reflecting contact layer, barrier layer, dilution protective layer, alloy-layer successively, described alloy-layer is formed substrate front side protective layer, substrate, substrate back side protective layer and contact layer.
Preferably, the material of described alloy-layer is any one in Ag-Sn-Au-In, Ag-Sn-Cu-In or Ag-Sn-Cu-In-Ti.
Preferably, the thickness on described barrier layer is 0.2um ~ 5um.
Preferably, the thickness of described dilution protective layer is 0.5um ~ 5um.
Preferably, the thickness of described mixed layer is 2um ~ 15um.
The present invention is by there being the melt back layer formed by low-melting-point metal at the envisaged underneath of LED film, and by annealing in process, melt back layer is melted after the former growth substrates of removal, make LED film can self-planarization in melt back layer fusion process, thus the effect of residual stress in reaching abundant release LED film.The present invention only increase melt back layer evaporation with together with annealing operation, technique is simple, cost is low.
Why the present invention designs the metal or alloy that melt back layer is low melting point, is because if the fusing point of melt back layer is too high, then, when carrying out annealing in process to LED chip and making melt back layer melt, can affect the photoelectric properties of LED chip because annealing temperature is too high.
Why the present invention selects intermediate layer to be that fusing point is less than the material of melt back layer fusing point and wafer hot pressing key and carrying out at the temperature lower than melt back layer fusing point, be in order to avoid melt back layer carry out wafer hot pressing key and time just react to each other with adjacent metal spread/form high-melting-point alloy.Otherwise the effect of melt back layer release stress just fails, design melt back Rotating fields also just loses meaning.
Therefore, the present invention has and simply, fully effectively can discharge residual stress in LED film, the photoelectric properties improving LED chip, reliability, stability and life-span, simplification manufacture process, the advantage of production cost of reducing.
accompanying drawing illustrates:
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the section of structure of step 1 in embodiment 1;
Fig. 3 is the section of structure of step 2 in embodiment 1;
Fig. 4 is the section of structure of step 3 in embodiment 1;
Fig. 5 is the section of structure of step 4 in embodiment 1;
Fig. 6 is the section of structure of step 5 in embodiment 1;
Fig. 7 is the section of structure of step 5 in embodiment 1;
Fig. 8 is the section of structure of step 6 in embodiment 1;
Fig. 9 is the section of structure of step 7 in embodiment 1.
embodiment:
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.It should be noted that, accompanying drawing of the present invention all adopts the non-accurate ratio simplified very much, only in order to convenient, distinct aid illustration the present invention.
Embodiment 1:
(1): as shown in Figure 2, provide substrate 10, grow LED film 11 over the substrate, wherein LED film 11 comprises resilient coating, n-layer, luminescent layer and P-type layer.Preferably, described substrate 10 is sapphire, and described LED film is Al-Ca-In-N film, adopts metallochemistry vapour deposition (MOCVD) method gained.In other embodiments of the invention, described substrate 10 also to can be in Si, SiC, GaN, GaAs or AlN any one, described LED film 11 is not limited to Al-Ca-In-N film, also can be that other semiconductive thin films needing to discharge stress are as the AlGaInP film of extension in gallium arsenide substrate.
(2): as shown in Figure 3, adopt the method for electron beam evaporation on LED film 11, form reflecting contact layer 12, barrier layer 13, dilution protective layer 14, melt back layer 15 and the first bonded layer 16 successively.Described reflecting contact layer 12, as the term suggests namely have good ohm contact performance with GaN base LED film, have high reflectance again, had both the effect in reflector and contact layer, in the present embodiment, its material is Ag, and thickness is 0.05um ~ 0.5um.The effect of described barrier layer 13 and dilution protective layer 14 is to stop that the melt back layer metal of low melting point and metallic intermediate layer diffuse to reflecting contact layer 12 and destroy contact performance and reflectivity; in the present embodiment; the material on barrier layer 13 is Cr/Pt or Pt/Au/Pt/TiW; thickness is 0.2um ~ 2um; the material of described dilution protective layer 14 is Ag or Cu, and thickness is 2um ~ 3 um.The material of the layer of melt back described in the present embodiment 15 is Sn, and the material of described first bonded layer 16 is Au.
(3): as shown in Figure 4, substrate 20 is provided, at the front of described substrate 20 successively deposition substrate front protecting layer 21, second bonded layer 22, at reverse side deposition substrate reverse side protective layer 23, the contact layer 24 successively of described substrate.Described second bonded layer be in Ti, Cu, Pt, Au, Al, Ag any one, in the present embodiment, the material of the second bonded layer 22 is Ag.
(4): as shown in Figure 5, depositing inter-layer 25 on described first bonded layer 16 and/or the second bonded layer 22.Especially, the fusing point in described intermediate layer 25 is less than the fusing point of melt back layer 15, and its material is be no more than the metal or alloy of 400 degrees Celsius.Surface deposition intermediate layer 25 only at the second key and layer 22 in the present embodiment, the material in intermediate layer 25 is In.
(5): adopt wafer thermocompression bonding method to be bound together with substrate 20 by described LED film 11 by intermediate layer 25, first bonded layer 16 and the second bonded layer 22.As shown in Figure 6, when carrying out described (5), need LED film 11 and substrate 20 to fit together, then complete under certain temperature and pressure.Especially, described (5) carry out at the temperature lower than melt back layer 16 fusing point.In the present embodiment wafer thermocompression bonding in temperature more than the fusing point of intermediate layer, below melt back layer fusing point, when namely carrying out described (5), intermediate layer is in molten state.After completing described (5), intermediate layer 25 and the first bonded layer 16, second bonded layer 22 fully Reaction-diffusion terms, forms secondary alloy-layer 30, as shown in Figure 7;
(6): as shown in Figure 8, described substrate 10 is removed.(so far; complete film transfer, LED film 11 to be upside down on substrate 20) owing to losing tensile stress or the compression of substrate 10 pairs of LED films, remove before and after described substrate 10; the stress state of LED film 11 there occurs great changes, usually has and bends.
(7): as described in Figure 9, the LED film 11 obtain described (6) and the convered structure of substrate 20 carry out annealing in process, and melt back layer 16 is melted.In described (7) annealing process, described melt back layer 16 and described secondary alloy-layer 30, dilute protective layer 14 and react to each other or diffuseed to form alloy-layer 40.The physical and chemical performance of described alloy-layer 40 keeps stable at 600 DEG C.
Along with the fusing of melt back layer 16, be positioned at LED film 11 self-planarization on melt back layer 16, stress thus obtain abundant release.
(8) N-type layer surface coarsening, trimming, passivation, Ohmic electrode preparation: continued to prepare the follow-up work step of light emitting diode (LED) chip with vertical structure, is comprised.The LED chip finally made as shown in Figure 1,50 be passivation layer, 60 is wherein surface coarsening layer, 70 for N electrode.
Claims (15)
1. there is a preparation method for the LED thin film chip of melt back layer, it is characterized in that: comprise the following steps:
A, provide substrate, growth comprises the LED film of resilient coating, n-layer, luminescent layer and P-type layer successively over the substrate;
B, on described LED film deposition of reflective contact layer, barrier layer, dilution protective layer, melt back layer and the first bonded layer successively; Described melt back layer is the metal or alloy that fusing point is less than the low melting point of 400 DEG C;
C, provide substrate, deposition substrate front protecting layer, the second bonded layer successively in the front of described substrate, at reverse side deposition substrate reverse side protective layer, the contact layer successively of substrate;
D, on described first bonded layer and/or the second bonded layer depositing inter-layer, the fusing point in described intermediate layer is less than the fusing point of melt back layer;
E, adopt wafer thermocompression bonding method LED film and substrate to be bound together by intermediate layer, the first bonded layer and the second bonded layer, the temperature of described wafer thermocompression bonding is lower than the fusing point of melt back layer;
F, remove described substrate (complete film transfer, LED film is upside down on substrate);
The convered structure of G, described LED film step F obtained and substrate carries out annealing in process, melt back layer is melted, to discharge stress;
After H, annealing in process, then carry out N-type layer surface coarsening, trimming, passivation, Ohmic electrode preparation, the LED thin film chip of obtained vertical stratification.
2. preparation method according to claim 1, is characterized in that: when carrying out step e, below fusing point temperature being risen to more than the fusing point in intermediate layer, melt back layer, making intermediate layer be in molten state when binding, namely melting binding; In binding procedure, make intermediate layer and the first bonded layer, the abundant Reaction-diffusion terms of the second bonded layer, form secondary alloy-layer.
3. according to claim 1 and preparation method according to claim 3; it is characterized in that: in the annealing process of step G; described melt back layer and described secondary alloy-layer, dilute protective layer and react to each other or diffuseed to form alloy-layer, the physical and chemical performance of described alloy-layer keeps stable at 600 DEG C.
4. preparation method according to claim 1, is characterized in that: temperature is raised to more than the fusing point exceeding melt back layer 0 to 150 DEG C when carrying out step G, and keeps 5 to 100min.
5. preparation method according to claim 1, it is characterized in that: the material on described barrier layer is the laminated construction of two or more materials arbitrarily in Cr, Ti, Pt, Au, Ni, W single-layer metal and metal alloy TiW, FeNiCr, FeCoCr, as: Cr/Pt, Cr/Au, Pt/Au/TiW, Pt/Au.
6. preparation method according to claim 1, is characterized in that: described dilution protective layer is the laminated construction of one or more metals in Ag, Ti, Pt, Ni, W, Cu.
7. preparation method according to claim 1, is characterized in that: the material in described intermediate layer is In, and the material of described melt back layer is any one in Sn, Au20Sn80.
8. preparation method according to claim 1, is characterized in that: the material in described intermediate layer is Sn, and the material of described melt back layer is Au20Sn80.
9. preparation method according to claim 1, is characterized in that: the material of described first bonded layer be in Cu, Au, Ag, Al any one.
10. preparation method according to claim 1, is characterized in that: described second bonded layer be in Ti, Cu, Pt, Au, Al, Ag any one.
11. 1 kinds of structures with the LED thin film chip of melt back layer; comprise substrate; it is characterized in that: be provided with the LED film comprising resilient coating, n-layer, luminescent layer and P-type layer over the substrate; LED film deposits reflecting contact layer, barrier layer, dilution protective layer, alloy-layer successively, described alloy-layer is provided with substrate front side protective layer, substrate, substrate back side protective layer and contact layer.
12. structures according to claim 1, is characterized in that: the material of described alloy-layer is any one in Ag-Sn-Au-In, Ag-Sn-Cu-In or Ag-Sn-Cu-In-Ti.
13. structures according to claim 1, is characterized in that: the thickness on described barrier layer is 0.2um ~ 5um.
14. structures according to claim 1, is characterized in that: the thickness of described dilution protective layer is 0.5um ~ 5um.
15. structures according to claim 1, is characterized in that: the thickness of described alloy-layer is 2um ~ 15um.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489717A (en) * | 2016-01-11 | 2016-04-13 | 西安交通大学 | Fabrication process for vertically structured light emitting diode (LED) chip |
| CN108767083A (en) * | 2018-05-30 | 2018-11-06 | 河源市众拓光电科技有限公司 | A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694089A (en) * | 2012-06-06 | 2012-09-26 | 杭州士兰明芯科技有限公司 | Bonding method for light-emitting diode (LED) chip and LED chip |
| US20130334561A1 (en) * | 2012-06-19 | 2013-12-19 | Hsiu-Jen Lin | Method for bonding led wafer, method for manufacturing led chip and bonding structure |
| CN103560193A (en) * | 2013-08-29 | 2014-02-05 | 南昌黄绿照明有限公司 | Vertical structure light emitting diode chip with low cost and preparation method thereof |
-
2014
- 2014-09-22 CN CN201410483425.2A patent/CN104347762B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694089A (en) * | 2012-06-06 | 2012-09-26 | 杭州士兰明芯科技有限公司 | Bonding method for light-emitting diode (LED) chip and LED chip |
| US20130334561A1 (en) * | 2012-06-19 | 2013-12-19 | Hsiu-Jen Lin | Method for bonding led wafer, method for manufacturing led chip and bonding structure |
| CN103560193A (en) * | 2013-08-29 | 2014-02-05 | 南昌黄绿照明有限公司 | Vertical structure light emitting diode chip with low cost and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489717A (en) * | 2016-01-11 | 2016-04-13 | 西安交通大学 | Fabrication process for vertically structured light emitting diode (LED) chip |
| CN108767083A (en) * | 2018-05-30 | 2018-11-06 | 河源市众拓光电科技有限公司 | A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof |
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| Publication number | Publication date |
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| CN104347762B (en) | 2017-03-22 |
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