CN104333720B - High frame per second overall situation pixel cmos image sensor and its method for transmitting signals - Google Patents
High frame per second overall situation pixel cmos image sensor and its method for transmitting signals Download PDFInfo
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Abstract
The invention discloses a kind of global pixel cmos image sensor, including：The pel array being made up of multiple global pixels；First tail current module, including multiple first tail current sources of each row configuration of the pel array are corresponded to respectively；First decoding module, it controls each global pixel to be exposed simultaneously, signal sampling, chooses each row of the pel array successively, and read the signal of each global pixel of selected line simultaneously；Second decoding module, the signal of each global pixel of the first decoding module institute selected line is sequentially output by it；Output driving module, the signal Serial output that second decoding module is sequentially output.The present invention can not only realize global exposure, and have high frame per second.
Description
Technical field
The present invention relates to field of image sensors, more particularly to a kind of high frame per second overall situation pixel cmos image sensor and its
Method for transmitting signals.
Background technology
Imaging sensor is the important component for forming digital camera.According to the difference of element, can be divided into CCD and
The major classes of CMOS two.Cmos sensor obtain wide variety of one on condition that its own higher sensitivity, compared with short exposure when
Between and the Pixel Dimensions that increasingly reduce.
As a rule, the frame per second of a cmos image sensor depends on the ability of rear digital signal processor (DSP),
At present, common digital signal processor possesses the processing energy of full HD frames video flowing lower each second 30 (30fps) of 1080p
Power, this frame per second ability are enough for high definition video steaming.
But for some special applications, each second 30 frame or 60 frames video stream frame rate it is just far from much of that.Example
Such as, for some scientific application cameras, it usually needs the object of shooting ultrahigh speed motion, such as shooting ultrahigh speed motion
Bullet, hundred meters of sportsmen spurt etc., therefore it is required that its imaging sensor can possess the IMAQ ability of high frame per second.It is general next
Say, the imaging sensor of high frame per second needs to have data flow ability more than full HD frames video flowing lower each second 200 of 1080p.
, can be one due to possessing the characteristics of highly integrated under CMOS technology for the imaging sensor of high frame per second
Collect pixel sum word processing circuit on chips, therefore be highly suitable for effectively improving the frame per second of imaging sensor.It is so high
The cmos image sensor of frame per second is the emphasis of current high frame per second sensor field research.
On the other hand, traditional 4T pixels generally fall into roller exposure pixel (Rolling Shutter Pixel), including
This four transistors of transfer tube, reset transistor, source follower and row gate tube.Its signal-obtaining principle is the grid when reset transistor
When signal RX moves high level to, suspension node FD electric charge is emptied and resetted, then the signal RX of reset transistor is put
When for low level and the signal TX of transfer tube being put into high, light sensitive diode PD signal will be transferred to FD points, then complete
Read into signal.That is, for the pixel array of the imaging sensor x rows y row of traditional 4T pixels composition, the first row
The time for exposure of time for exposure of first row and xth row y row is not simultaneously.This non-concurrent property is come for general camera application
Saying has no problem, but during for high frame per second shooting image, then can cause obvious image fault and deformation.So for high frame
The imaging sensor of rate by global pixel (Global Shutter Pixel), it is necessary to be realized.
The content of the invention
A kind of the defects of it is a primary object of the present invention to overcome prior art, there is provided the global pixel CMOS figures of high frame per second
As sensor.
To reach above-mentioned purpose, the present invention provides a kind of global pixel cmos image sensor, including by multiple global pictures
The pel array of member composition；First tail current module, including correspond to respectively the pel array the configuration of each row multiple the
One tail current source；First decoding module, it controls each global pixel to be exposed simultaneously, signal sampling, chooses institute successively
Each row of pel array is stated, and reads the signal of each global pixel of selected line simultaneously；Second decoding module, it is by institute
The signal for stating each global pixel of the first decoding module institute selected line is sequentially output；Output driving module, by described second
The signal Serial output that decoding module is sequentially output.
Preferably, each global pixel include light sensitive diode, transfer tube, suspension node, reset transistor, the first source with
With device, preliminary filling fulgurite, the first sampling holding capacitor, the second sampling holding capacitor, first switch pipe, second switch pipe, the second source
Follower and row gate tube；The source electrode of the transfer tube connects the light sensitive diode, and drain electrode connects first source follower
Grid and the reset transistor source electrode in the suspension node；The drain electrode of the preliminary filling fulgurite and first source follower
Source electrode is connected in the source electrode of the first switch pipe, source ground；The drain electrode of the reset transistor connects supply voltage, first source
The drain electrode of follower connects supply voltage；Drain electrode and the source electrode of the second switch pipe of the first switch pipe are connected to described the
One end of one sampling holding capacitor, the other end ground connection of the first sampling holding capacitor；The drain electrode of the second switch pipe with
The grid of second source follower is connected to one end of the second sampling holding capacitor, the second sampling holding capacitor
The other end is grounded；Drain electrode connection supply voltage, the source electrode of second source follower connect the source electrode of the row gate tube；It is described
Output end of the drain electrode of row gate tube as the pixel；The leakage of the row gate tube of same row overall situation pixel in the pel array
First tail current source corresponding to extremely common connection；
Transfer tube, reset transistor, preliminary filling fulgurite, first switch pipe, second switch pipe and the row choosing of each global pixel
The signal of siphunculus is sent by first decoding module, so that the second sampling of each global pixel of selected line
Holding capacitor successively exports the reset signal and the reset signal and the light sensitive diode signal of the global pixel of the global pixel
Mixed signal, wherein the difference of the reset signal and the mixed signal characterizes the signal of the global pixel.
Preferably, the global pixel cmos image sensor also includes the second tail current module, including corresponds to institute respectively
State the second tail current source of multiple ground connection of each row configuration of pel array；The leakage of the row gate tube of each global pixel
Pole connects second tail current source corresponding to it by a controlling switch.
Preferably, the opening and closing signal that the open and-shut mode of the controlling switch is sent by first decoding module controls, and makes
Described controlling switch corresponding to it is closed after opening before obtaining the second switch pipe output signal every time.
Preferably, first decoding module sends second switch signal each global pixel into the pel array
Second switch pipe, the second switch signal has flag bit, when first decoding module sends the second switch letter
The flag bit is set as 1 or 0 during number controlling all second switch pipes, when first decoding module sends described the
Two switching signals are correspondingly arranged the mark to control in the pel array during the only second switch pipe of the global pixel of selected line
Will position is 0 or 1.
Present invention also offers a kind of method for transmitting signals of above-mentioned global pixel cmos image sensor, including：
Step S1：Make each global pixel while exposure and signal sampling in the pel array；
Step S2：Certain a line of the pel array is chosen, the signal of each global pixel of the row is read simultaneously；
Step S3：The signal that each global pixel of the row is read is sequentially output；
Repeat step S2 and step S3 up to the signal output of whole global pixels in the pel array.
Preferably, each global pixel include light sensitive diode, transfer tube, suspension node, reset transistor, the first source with
With device, preliminary filling fulgurite, the first sampling holding capacitor, the second sampling holding capacitor, first switch pipe, second switch pipe, the second source
Follower and row gate tube；The source electrode of the transfer tube connects the light sensitive diode, and drain electrode connects first source follower
Grid and the reset transistor source electrode in the suspension node；The drain electrode of the preliminary filling fulgurite and first source follower
Source electrode is connected in the source electrode of the first switch pipe, source ground；The drain electrode of the reset transistor connects resetting voltage, first source
The drain electrode of follower connects supply voltage；Drain electrode and the source electrode of the second switch pipe of the first switch pipe are connected to described the
One end of one sampling holding capacitor, the other end ground connection of the first sampling holding capacitor；The drain electrode of the second switch pipe with
The grid of second source follower is connected to one end of the second sampling holding capacitor, the second sampling holding capacitor
The other end is grounded；Drain electrode connection supply voltage, the source electrode of second source follower connect the source electrode of the row gate tube；It is described
Output end of the drain electrode of row gate tube as the pixel；The leakage of the row gate tube of same row overall situation pixel in the pel array
First tail current source corresponding to extremely common connection；Wherein,
Step S1 includes：
Step S11：The reset transistor and transfer tube of all global pixels are opened, it is clear to carry out electric charge to the suspension node
Empty and reset；
Step S12：Each transfer tube is turned off, makes each global pixel start to expose；
Step S13：Preliminary filling fulgurite, first switch pipe and the second switch pipe of all global pixels are opened, makes each institute
State the first sampling holding capacitor and the second sampling holding capacitor samples the reset signal that each preliminary filling fulgurite is exported；
Step S14：Turning off each second switch pipe makes each second sampling holding capacitor keep each described reset to believe
Number；
Step S15：Each transfer tube is opened, each global pixel exposure finishes, and each first sampling keeps electricity
Hold and sample the light sensitive diode signal that each preliminary filling fulgurite is exported；
Step S16：Turning off each first switch pipe makes each first sampling holding capacitor keep each described photosensitive two
Pole pipe signal.
Preferably, step S2 includes：
Step S21：Certain a line of the pel array is chosen, each second sampling holding capacitor for reading the row is protected
Each reset signal held；
Step S22：Each second switch pipe of the row is opened, is protected each first sampling holding capacitor of the row
The light sensitive diode signal held mixes with each reset signal that each second sampling holding capacitor is kept and makes the row
Each second sampling holding capacitor keep the blended mixed signal formed；
Step S23：Read each mixed signal that each second sampling holding capacitor of the selected line is kept.
Preferably, the global pixel cmos image sensor also includes the second tail current module, including corresponds to institute respectively
State the second tail current source of multiple ground connection of each row configuration of pel array；The leakage of the row gate tube of each global pixel
Pole connects second tail current source corresponding to it by a controlling switch；Before step S21 and step S23 is performed every time,
Each controlling switch of the selected line is set to be closed after opening.
Preferably, what the opening and closing of second switch pipe described in step S1 and S2 was sent by first decoding module second opens
OFF signal controls, and the second switch signal has flag bit, when first decoding module sends the second switch signal
The flag bit is set as 1 or 0 during controlling all second switch pipes, when first decoding module sends described second
Switching signal is correspondingly arranged the mark to control in the pel array during the only second switch pipe of the global pixel of selected line
Position is 0 or 1.
The advantage of the invention is that by the setting of two decoding modules, realize cmos image sensor global exposure and
High frame per second data flow ability.
Brief description of the drawings
Fig. 1 show the block diagram of the global pixel cmos image sensor of one embodiment of the invention；
The circuit that Fig. 2 show a global pixel in the global pixel cmos image sensor of one embodiment of the invention shows
It is intended to；
Fig. 3 show the global pixel signal transmission of global pixel cmos image sensor one of one embodiment of the invention
Timing diagram.
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Fig. 1 is the block diagram of the global pixel cmos image sensor of the present invention, as illustrated, cmos image sensor bag
Include pel array 10, the first tail current module 20, the first decoding module 30, the second decoding module 40 and output driving module 50.
Pel array 10 is made up of multiple global pixels, and the present embodiment includes the perfectly sound office's pixels of 4000 × 2000=800.First tail electricity
Flow module 20 includes the first tail current source of multiple ground connection of each row configuration of respective pixel array respectively, therefore the present embodiment
In the first tail current source be also corresponding with 2000.First decoding module 30 performs following action：Control the whole of pel array 10
Global pixel is exposed simultaneously, signal sampling, chooses each row of pel array 10, and each global picture to selected line successively
The signal of member is read simultaneously.Second decoding module 40 is by the global pixel of each reading of 30 selected lines of the first decoding module
Signal is sequentially output to output driving module 50, and output driving module 50 is again by these signal Serial outputs to external circuit.It is logical
Cross the setting of these above-mentioned modules so that whole pixels of pel array are exposed simultaneously, afterwards pel data a line one again
Row is sequentially output, it is achieved thereby that the global exposure of cmos image sensor.
As with reference to shown in Fig. 1 and Fig. 2, each global pixel of the present embodiment is 8T (8 transistor) pixel, including for inciting somebody to action
The optical signal of reception be converted to the light sensitive diode PD of electric signal, transfer tube M1, suspension node FD, reset transistor M2, the first source with
Electricity is kept with device M3, preliminary filling fulgurite M4, first switch pipe M5, second switch pipe M6, the first sampling holding capacitor C1, the second sampling
Hold C2, the second source follower M7 and row gate tube M8.The annexation of each transistor is as follows：
Transfer tube M1 source electrode connection light sensitive diode, drain and the first source follower M3 grid and reset transistor M2 source
Pole is commonly connected to suspension node FD, grid is controlled by control signal TX；
Preliminary filling fulgurite M4 drain electrode and the first source follower M3 source electrode be connected to the source electrode of first switch pipe, source electrode connects
Ground, grid are controlled by control signal PC；
Reset transistor M2 drain electrode meets supply voltage VDD, and grid is controlled by control signal RST；
First source follower M3 drain electrode meets supply voltage VDD；
First switch pipe M5 drain electrode and one end phase of second switch pipe M6 source electrode and the first sampling holding capacitor C1
Even, grid is controlled by first switch signal S1；First sampling holding capacitor C1 other end ground connection；
Second switch pipe M6 drain electrode and one end of the second source follower M7 grid and the second sampling holding capacitor C2
It is connected, grid is controlled by second switch signal S2；Second sampling holding capacitor C2 other end ground connection；
Second source follower M7 drain electrode connects supply voltage VDD, source electrode connection row gate tube M8 source electrode；
Row gate tube M8 drain electrode is the output end of global pixel, and the second decoding module is connected to by row DBMS line,
The first tail current source I1, the first tail current source I1 provides the normal work that excitation ensures global pixel be also connected to simultaneously corresponding to
Make.
Wherein, signal TX, RST, PC, S1, S2 and RS is sent by the first decoding module 20, passes through these signal controls
Make the conducting of each transistor and cut-off state chooses the row of pel array, and cause second of each global pixel in selected line
Sampling holding capacitor C2 can successively export the reset signal and mixed signal of the global pixel, and the mixed signal is reset signal
Mixed with light sensitive diode signal, and the difference of reset signal and mixed signal can characterize the signal of global pixel.
Specifically, control signal TX, RST, PC, S1 is overall signal, and that is to say can control in pel array entirely
The grid of the corresponding transistor of portion's pixel, the size of its low and high level are controlled by input and output pin PAD.In the present embodiment,
Pin PAD shares 130, as in Fig. 1 marked as 0~129, this 130 pin PAD coordinate according to standard probe card coordinate
It is designed, so that the global pixel cmos image sensor, which can pass through ATE automatic probers platform, carries out automatic measurement, increases
Add the efficiency of follow-up test and system development.On the other hand, control signal RS is row signal, that is to say the picture that can only control a line
The grid of the row gate tube of member.Control signal S2, which has, is used as overall signal and row signal both of which, in overall situation exposure and letter
The second switch pipe of whole pixels is controlled during number sampling as overall signal, then choosing is only controlled as row signal in signal output
The second switch pipe of the pixel of middle row so that the signal of the only global pixel of selected line is output to the second decoding module.In order to
The switching of second switch signal S2 both of which can be realized, a flag bit is set in signal S2, if controlling whole pixels
Second switch pipe M6 opening and closing flag bit is then set to 1 (or 0), otherwise second when the control only global pixel of selected line opens
Flag bit is set to 0 (or 1) when closing pipe M6 opening and closing.Flag bit can be signal S2 first or last position；Can also
It is signal S2 whole positions, when such as signal S2 whole positions being 1, switches to global schema to open whole second switch pipes,
Although it may so cause the second switch pipe of certain a line in pel array uncontrollable, for the high-resolution of such as the present embodiment
The cmos image sensor of rate (4000 rows × 2000 arrange), the influence for only sacrificing the data of one-row pixels are smaller.
Cmos image sensor may also include biasing and excitation module 60, to provide standard mains voltage VDD.
In addition, the major function of output driving module has two, first, signal is carried out into simulation output, second, eliminating simulation
The parasitic capacitance (as having buffer) of signal, the parasitic capacitance includes PAD electric capacity, nation's line (bonding wire) electric capacity, piece
Outer apparatus measures electric capacity etc., wherein, PAD electric capacity is about 200fF, nation's line capacitance is about 100fF, the outer apparatus measures electric capacity of piece is about
20pF。。
Next Fig. 2 current diagram and Fig. 3 signal transmission time sequence figure will be combined to pass the cmos image of the present invention
The operation principle of sensor is illustrated.
First, step S1 is carried out：Carry out exposure and signal sampling while whole pixels.
Specifically, control signal RST and TX first are put into height, the reset transistor M2 and transfer tube M1 of all global pixels are opened,
Charging reset is carried out to light sensitive diode PD, electric charge is carried out to suspension node FD and empties and resets, suspension node FD voltage is drawn
Up to supply voltage VDD.
Then, control signal TX is set low, turns off the transfer tube M1 of whole pixels, these global pixels start simultaneously at exposure
Light.
Afterwards, control signal PC is put into height, opens the preliminary filling fulgurite M4 of all global pixels；Next by control signal
S1, S2 put height, and control signal S2 is global schema so that the first switch pipe and second switch pipe of whole pixels are opened, all
Global holding sampling capacitance C1 and C2 maintains reset signal Vreset (being supply voltage VDD in the present embodiment).This
After PC signals put high 0.2us in embodiment, control signal S1, S2 puts height.
The control signal S2 of global schema is set low so that the second switch pipe M6 of each global pixel is turned off, thus multiple
Position signal Vreset is maintained in electric capacity C2.
Then, control signal TX is put into height, the transfer tube M1 of each global pixel is opened, and exposure terminates simultaneously.Due to each biography
Defeated pipe M1 is opened, and the analog electrical signal Vsignal of light sensitive diode PD conversions is transmitted to suspension node FD, then is followed through the first source
Device M3 is exported into sampling holding capacitor C1.
Then, control signal S1 is set low, the first switch pipe M5 of each global pixel is turned off so that all global pixels
Light sensitive diode signal Vsignal be respectively held in each sampling holding capacitor C1.
Accordingly, for each global pixel, sampling holding capacitor C1 stores its light sensitive diode signal Vsignal, adopts
Sample holding capacitor C2 stores its reset signal Vreset.
After the completion of above-mentioned steps, step S2 is carried out：Certain a line of pel array is chosen, to the letter of each global pixel of the row
Number read simultaneously.
Specifically, the control signal RS of each global pixel of wherein a line of pel array is put into height, other row overall situation pictures
The control signal RS of member is set low to choose the row.The reset letter stored on second sampling holding capacitor C2 of each global pixel of the row
Number the second decoding module is output to by row gate tube M8 and row DBMS line.
Then, the control signal S2 of the row overall situation pixel is put into height, opens each second switch pipe M6 of the row.Control now
Signal S2 processed switches to row signal mode.Because first switch pipe M5 is still off, only second switch pipe M6 conductings so that electric capacity C1
Reset signal Vreset that the light sensitive diode signal Vsignal and electric capacity C2 kept is kept mixing, final electric capacity C1 and
The mixed signal that signal value is 1/2 (Vignal+Vreset) is kept in C2；
Then, each second switch pipe M6 of the row is turned off, the row respectively samples the mixed signal stored on holding capacitor C2 and led to
Space gate tube M8 and row DBMS line are output to the second decoding module.
As known from the above, the present invention carries out signal-obtaining twice to each global pixel of selected line, reads for the first time
For reset signal Vreset, mixed signal 1/2 (Vignal+Vreset) is read as the second time, and the difference of twi-read signal is
1/2 (Vreset-Vignal), to characterize the signal of global pixel.The data read for each selected line overall situation pixel, the
Two decoding modules are sequentially output to output driving module, then are sequentially output by output driving module to outer treatment circuit,
So as to complete the output of a line overall situation pixel signal.
First decoding module chooses each row of pel array successively, and carries out above-mentioned signal output to the global pixel of every row
SECO, whole signal of global pixels in the final output pel array.
In a preferred embodiment, global pixel cmos image sensor also includes the second tail current module, and it includes point
Second tail current source I2 of multiple ground connection of each row configuration of other respective pixel array；The row gate tube of each global pixel
M8 drain electrode connects its corresponding second tail current source I2 by a controlling switch.First decoding module sends control signal S3 controls
The open and-shut mode of the switch is made, control signal S3 is similarly row signal, that is to say that the controlling switch of same a line overall situation pixel is equal
Controlled by same control signal S3.Before control signal S3 causes each read reset signal or mixed signal, controlling switch
Closed after S3 conductings, and by the row gate tube M8 of short duration ground connection of drain electrode so that row gate tube M8 when each signal-obtaining starts
Drain electrode is in a reference potential level (i.e. GND), can avoid because a preceding signal-obtaining is to a rear signal-obtaining
Parasitic effects, i.e., so-called " Image Leg " effects.As illustrated, control signal S3 produces two in total read access time
Subpulse, for the first time for read reset signal before, second makes electric capacity C2 keep mixed to produce second switch signal S2 pulses
After conjunction signal, before reading mixed signal.
In the present embodiment, it is 2~10us, preferably 5us that control signal RST, which sets low the time,；
The control signal TX high time of putting is 0.5~10us, preferably 2us；
Time for exposure can pass through system sets itself；
It is 0.5~20us, preferably 6us that control signal PC, which puts the high time,；
It is 0.5~10us, preferably 5us that first switch signal S1, which puts the high time,；
It is 0.5~10us that second switch signal S2, which puts the high time for the first time and (puts the high time when i.e. in global schema),
It is preferred that 3us；It is 0.5~5us, preferably 1us to put for the second time the high time and (put the high time when i.e. in row mode), be for the second time
RS signals put the rearmounted height of high 0.7us；
The high time of putting of RS signals is 1~10us, preferably 2.5us；
The switching signal S3 high time of putting every time is 0.5us, and pulse interval is 1us twice.
Pass through above-mentioned SECO, it is possible to achieve 4K (pixels of 4k*,2k=,800 ten thousand) ultra high-definition video flowing lower each second 60
Data flow ability more than frame.
Although the present invention is disclosed as above with preferred embodiment, right many embodiments are illustrated only for the purposes of explanation
, the present invention is not limited to, those skilled in the art can make without departing from the spirit and scope of the present invention
Some changes and retouching, the protection domain that the present invention is advocated should be to be defined described in claims.
Claims (5)
- A kind of 1. global pixel cmos image sensor, it is characterised in that including：The pel array being made up of multiple global pixels；First tail current module, including multiple first tail current sources of each row configuration of the pel array are corresponded to respectively；First decoding module, it controls each global pixel to be exposed simultaneously, signal sampling, chooses the pixel battle array successively Each row of row, and the signal of each global pixel of selected line is read simultaneously；Second decoding module, the signal of each global pixel of the first decoding module institute selected line is sequentially output by it；Output driving module, the signal Serial output that second decoding module is sequentially output；Global pixel described in each of which includes light sensitive diode, transfer tube, suspension node, reset transistor, the first source follower, pre- Charging valve, first sampling holding capacitor, second sampling holding capacitor, first switch pipe, second switch pipe, the second source follower and Row gate tube；The source electrode of the transfer tube connects the light sensitive diode, drain electrode connect first source follower grid and The source electrode of the reset transistor is in the suspension node；The drain electrode of the preliminary filling fulgurite is connected with the source electrode of first source follower In the source electrode of the first switch pipe, source ground；The drain electrode of the reset transistor connects supply voltage, first source follower Drain electrode connects supply voltage；The drain electrode of the first switch pipe and the source electrode of the second switch pipe are connected to first sampling and protected Hold one end of electric capacity, the other end ground connection of the first sampling holding capacitor；The drain electrode of the second switch pipe and described second The grid of source follower is connected to one end of the second sampling holding capacitor, another termination of the second sampling holding capacitor Ground；Drain electrode connection supply voltage, the source electrode of second source follower connect the source electrode of the row gate tube；The row gate tube Output end of the drain electrode as the pixel；The drain electrode of the row gate tube of same row overall situation pixel connects jointly in the pel array First tail current source corresponding to connecing；Transfer tube, reset transistor, preliminary filling fulgurite, first switch pipe, second switch pipe and the row gate tube of each global pixel Signal sent by first decoding module so that each global pixel of selected line second sampling keep Electric capacity successively exports the reset signal of the global pixel and mixing for the light sensitive diode signal of the reset signal and the global pixel Signal is closed, wherein the difference of the reset signal and the mixed signal characterizes the signal of the global pixel；Wherein described first decoding module send second switch signal into the pel array each global pixel second Switching tube, the second switch signal have flag bit, when first decoding module sends the second switch signal to control It is 1 or 0 that the flag bit is set when making all second switch pipes, when first decoding module sends the second switch The flag bit is correspondingly arranged as 0 when signal is to control in the pel array the only second switch pipe of the global pixel of selected line Or 1.
- 2. global pixel cmos image sensor according to claim 1, it is characterised in that also including the second tail current mould Block, including the second tail current source of multiple ground connection of each row configuration of the pel array is corresponded to respectively；Each overall situation The drain electrode of the row gate tube of pixel connects second tail current source corresponding to it by a controlling switch.
- 3. global pixel cmos image sensor according to claim 2, it is characterised in that the opening and closing of the controlling switch The opening and closing signal that state is sent by first decoding module controls so that before each second switch pipe output signal its The corresponding controlling switch is closed after opening.
- A kind of 4. method for transmitting signals of global pixel cmos image sensor as claimed in claim 1, it is characterised in that bag Include：Step S1：Make each global pixel while exposure and signal sampling in the pel array；Step S2：Certain a line of the pel array is chosen, the signal of each global pixel of the row is read simultaneously；Step S3：The signal that each global pixel of the row is read is sequentially output；Repeat step S2 and step S3 up to the signal output of whole global pixels in the pel array；Wherein, step S1 includes：Step S11：Open the reset transistor and transfer tube of all global pixels, the suspension node is carried out electric charge empty and Reset；Step S12：Each transfer tube is turned off, makes each global pixel start to expose；Step S13：Preliminary filling fulgurite, first switch pipe and the second switch pipe of all global pixels are opened, makes each described the One sampling holding capacitor and the second sampling holding capacitor sample the reset signal that each preliminary filling fulgurite is exported；Step S14：Turning off each second switch pipe makes each second sampling holding capacitor keep each reset signal；Step S15：Each transfer tube is opened, each global pixel exposure is finished, and each first sampling holding capacitor is adopted The light sensitive diode signal that each preliminary filling fulgurite of sample is exported；Step S16：Turning off each first switch pipe makes each first sampling holding capacitor keep each light sensitive diode Signal；Step S2 includes：Step S21：Certain a line of the pel array is chosen, read the row each described second samples what holding capacitor was kept Each reset signal；Step S22：Each second switch pipe of the row is opened, makes each described the first of the row to sample what holding capacitor was kept Light sensitive diode signal mixes with each reset signal that each second sampling holding capacitor is kept and makes each of the row The second sampling holding capacitor keeps the blended mixed signal formed；Step S23：Read each mixed signal that each second sampling holding capacitor of the selected line is kept；Step S13, what the opening and closing of second switch pipe described in step S14 and S22 was sent by first decoding module second opens OFF signal controls, and the second switch signal has flag bit, when first decoding module sends the second switch signal The flag bit is set as 1 or 0 during controlling all second switch pipes, when first decoding module sends described second Switching signal is correspondingly arranged the mark to control in the pel array during the only second switch pipe of the global pixel of selected line Position is 0 or 1.
- 5. method for transmitting signals according to claim 4, it is characterised in that the global pixel cmos image sensor is also Including the second tail current module, including the second tail current of multiple ground connection of each row configuration of the pel array is corresponded to respectively Source；The drain electrode of the row gate tube of each global pixel connects second tail current corresponding to it by a controlling switch Source；Before step S21 and step S23 is performed every time, each controlling switch of the selected line is set to be closed after opening.
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| CN105554421B (en) * | 2015-12-10 | 2019-12-13 | 上海集成电路研发中心有限公司 | global pixel nonlinear compensation structure |
| CN106375688B (en) * | 2016-09-06 | 2019-11-22 | 上海集成电路研发中心有限公司 | A kind of cmos image sensor and its method for transmitting signals |
| CN106791514B (en) * | 2016-12-29 | 2020-01-10 | 上海集成电路研发中心有限公司 | Full-frame image sensor |
| WO2020107316A1 (en) * | 2018-11-29 | 2020-06-04 | 深圳市大疆创新科技有限公司 | Image sensor, method for preparing image sensor, and pixel circuit |
| CN110062181B (en) * | 2019-05-13 | 2021-04-02 | 西北核技术研究院 | Ultra-high-speed double-frame image acquisition method based on global shutter type CMOS image sensor |
| CN112399113B (en) * | 2019-08-12 | 2022-07-05 | 天津大学青岛海洋技术研究院 | High-speed global exposure pixel structure for realizing intra-pixel correlated double sampling |
| CN112399104B (en) * | 2019-08-14 | 2023-06-16 | 天津大学青岛海洋技术研究院 | Global exposure low-noise high-speed three-dimensional sensor phase-locked pixel and reading mode |
| CN111491119A (en) * | 2020-04-22 | 2020-08-04 | 上海微阱电子科技有限公司 | Pixel structure supporting global exposure and roller shutter exposure |
| CN115550579B (en) * | 2022-10-09 | 2023-09-26 | 成都微光集电科技有限公司 | Image sensor reading method and image sensor |
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| CN102447848B (en) * | 2012-01-17 | 2013-09-04 | 中国科学院半导体研究所 | Global shutter pixel unit of complementary metal oxide semiconductor (CMOS) image sensor |
| CN102752560B (en) * | 2012-06-21 | 2014-11-12 | 吉林大学 | Ultra-wide dynamic range image sensor based on pixel charge compensation technology |
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