CN104333382A - Current-steering DAC (digital-to-analog converter) calibration method - Google Patents

Abstract

The invention provides a current-steering DAC (digital-to-analog converter) calibration method, and belongs to the field of integrated circuits. A current-steering DAC is a 12-bit current-steering DAC and implemented in a binary coding mode. The current-steering DAC firstly acquires an offset current value I0 by testing, secondly acquires 12 data currents by testing, thirdly subtracts the offset current value I0 from the 12 data currents to obtain a data action current, fourthly sets a target value of the data action current and finally calculates the difference between an actual value and the target value of the data action current to respectively adjust current sources corresponding to data. The current-steering DAC calibration method effectively solves the problem of poor static performances such as DAC INL (integral non-linearity) and DNL (differential non-linearity) caused by process mismatch and the like, and the performance of the DAC is greatly improved. Moreover, the calibration method is simple to operate and low in implementation cost and can be effectively applied to calibrating the current-steering DAC.

Description

A kind of calibration steps of current steering DAC

Technical field

The invention belongs to integrated circuit fields, particularly a kind of calibration steps of current steering DAC.

Background technology

DAC is the abbreviation of digital to analog converter, and as the bridge between connecting analog signal and digital signal, digital to analog converter uses more and more extensive in information industry, and in a lot of occasion, the required precision of logarithmic mode transducer is also more and more higher.

Traditional current steering DAC adopts multiple independently current source to form, the input data one_to_one corresponding of these independently current source and DAC, according to the difference of data encoding, the size of the output current that these current sources cause is generally certain proportionate relationship, and the size of the output current that the current source of binary coded data causes becomes binary scale relation.

Traditional current steering DAC is very high to the coherence request of current source, and the mismatch of the current source brought due to process deviation and deviation inevitable, this non-ideal factor has very large impact to static propertiess such as the integral nonlinearity INL of current steering DAC and differential nonlinearity DNL.

Summary of the invention

In view of this, the invention provides a kind of calibration steps of current steering DAC, to improve the static properties such as integral nonlinearity INL and differential nonlinearity DNL of current steering DAC.

A kind of calibration steps of current steering DAC comprises the steps:

Step S1, the output current of current steering DAC during test input data full 0, is expressed as offset current I ₀;

Step S2, inputs 16 binary data 001,002,004,008,010,020,040,080,100,200,400,800 respectively, reads the output current of current steering DAC respectively, and be expressed as electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀;

Step S3, by all electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀all deduct offset current I ₀;

Step S4, by I ₈₀₀-I ₀value be set to dreamboat value ITAR, can show that the target current value that other each data input is as follows, i.e. I _{800_1}=ITAR; I _{400_1}=ITAR/2; I _{200_1}=ITAR/2 ²; I _{100_1}=ITAR/2 ³; I _{080_1}=ITAR/2 ⁴; I _{040_1}=ITAR/2 ⁵; I _{020_1}=ITAR/2 ⁶; I _{010_1}=ITAR/2 ⁷; I _{008_1}=ITAR/2 ⁸; I _{004_1}=ITAR/2 ⁹; I _{002_1}=ITAR/2 ¹⁰; I _{001_1}=ITAR/2 ¹¹;

Step S5, calculates desired value I respectively _{800_1}, I _{400_1}, I _{200_1}, I _{100_1}, I _{080_1}, I _{040_1}, I _{020_1}, I _{010_1}, I _{008_1}, I _{004_1}, I _{002_1}, I _{001_1}with measured value I ₈₀₀-I ₀, I ₄₀₀-I ₀, I ₂₀₀-I ₀, I ₁₀₀-I ₀, I ₀₈₀-I ₀, I ₀₄₀-I ₀, I ₀₂₀-I ₀, I ₀₁₀-I ₀, I ₀₀₈-I ₀, I ₀₀₄-I ₀, I ₀₀₂-I ₀, I ₀₀₁-I ₀between gap, by adjusting the size of the current source of each correspondence, every road electric current being exported and equal corresponding desired value, completing the calibration of current source.

Further, the adjustment to current source size in described step S5, adopts fuse or band EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM to realize.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the flow chart of current steering DAC calibration steps provided by the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

A calibration steps for current steering DAC, as shown in Figure 1, comprises the steps:

Step S1, the output current of current steering DAC during test input data full 0, is expressed as offset current;

Step S2, inputs 16 binary data 001,002,004,008,010,020,040,080,100,200,400,800 respectively, reads the output current of current steering DAC respectively, and be expressed as electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀;

Step S3, by all electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀all deduct offset current;

Step S4, by-value be set to dreamboat value ITAR, can show that the target current value that other each data input is as follows, i.e. I _{800_1}=ITAR; I _{400_1}=ITAR/2; I _{200_1}=ITAR/2 ²; I _{100_1}=ITAR/2 ³; I _{080_1}=ITAR/2 ⁴; I _{040_1}=ITAR/2 ⁵; I _{020_1}=ITAR/2 ⁶; I _{010_1}=ITAR/2 ⁷; I _{008_1}=ITAR/2 ⁸; I _{004_1}=ITAR/2 ⁹; I _{002_1}=ITAR/2 ¹⁰; I _{001_1}=ITAR/2 ¹¹;

Step S5, calculates desired value I respectively _{800_1}, I _{400_1}, I _{200_1}, I _{100_1}, I _{080_1}, I _{040_1}, I _{020_1}, I _{010_1}, I _{008_1}, I _{004_1}, I _{002_1}, I _{001_1}with measured value I ₈₀₀-I ₀, I ₄₀₀-I ₀, I ₂₀₀-I ₀, I ₁₀₀-I ₀, I ₀₈₀-I ₀, I ₀₄₀-I ₀, I ₀₂₀-I ₀, I ₀₁₀-I ₀, I ₀₀₈-I ₀, I ₀₀₄-I ₀, I ₀₀₂-I ₀, I ₀₀₁-I ₀between gap, by adjusting the size of the current source of each correspondence, every road electric current being exported and equal corresponding desired value, completing the calibration of current source.

As embodiments of the invention, the adjustment to current source size in described step S5, adopts fuse or band EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM to realize.

Current steering DAC in the present invention is the current steering DAC of 12, and it adopts binary coding mode to realize.12 16 binary data 001,002,004,008,010,020,040,080,100,200,400,800 corresponding current source circuit respectively, the size of each current source circuit electric current is added by multichannel electron current source to form, and every way current source circuit all controls it by fuse or band EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM and whether accesses.Like this, just achieve with fuse or be with EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM to the adjustment of current source circuit size of current.

The calibration steps of current steering DAC of the present invention, effectively can calibrate the static properties of current steering DAC, avoids the problem of the DAC static properties difference caused due to process mismatch greatly.And this calibration steps is simple to operate, and implementation cost is low, the calibration of current steering DAC extraordinaryly can be applied to.

In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (2)

1. a calibration steps for current steering DAC, is characterized in that, comprises the steps:

Step S1, the output current of current steering DAC during test input data full 0, is expressed as offset current I ₀;

Step S2, inputs 16 binary data 001,002,004,008,010,020,040,080,100,200,400,800 respectively, reads the output current of current steering DAC respectively, and be expressed as electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀;

Step S3, by all electric current I ₀₀₁, I ₀₀₂, I ₀₀₄, I ₀₀₈, I ₀₁₀, I ₀₂₀, I ₀₄₀, I ₀₈₀, I ₁₀₀, I ₂₀₀, I ₄₀₀, I ₈₀₀all deduct offset current I ₀;

Step S4, by I ₈₀₀-I ₀value be set to dreamboat value ITAR, can show that the target current value that other each data input is as follows, i.e. I _{800_1}=ITAR; I _{400_1}=ITAR/2; I _{200_1}=ITAR/2 ²; I _{100_1}=ITAR/2 ³; I _{080_1}=ITAR/2 ⁴; I _{040_1}=ITAR/2 ⁵; I _{020_1}=ITAR/2 ⁶; I _{010_1}=ITAR/2 ⁷; I _{008_1}=ITAR/2 ⁸; I _{004_1}=ITAR/2 ⁹; I _{002_1}=ITAR/2 ¹⁰; I _{001_1}=ITAR/2 ¹¹;

Step S5, calculates desired value I respectively _{800_1}, I _{400_1}, I _{200_1}, I _{100_1}, I _{080_1}, I _{040_1}, I _{020_1}, I _{010_1}, I _{008_1}, I _{004_1}, I _{002_1}, I _{001_1}with measured value I ₈₀₀-I ₀, I ₄₀₀-I ₀, I ₂₀₀-I ₀, I ₁₀₀-I ₀, I ₀₈₀-I ₀, I ₀₄₀-I ₀, I ₀₂₀-I ₀, I ₀₁₀-I ₀, I ₀₀₈-I ₀, I ₀₀₄-I ₀, I ₀₀₂-I ₀, I ₀₀₁-I ₀between gap, by adjusting the size of the current source of each correspondence, every road electric current being exported and equal corresponding desired value, completing the calibration of current source.

2. the calibration steps of current steering DAC as claimed in claim 1, is characterized in that, the adjustment to current source size in described step S5, adopts fuse or band EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM to realize.