CN104332463B - 多芯片器件 - Google Patents
多芯片器件 Download PDFInfo
- Publication number
- CN104332463B CN104332463B CN201410408963.5A CN201410408963A CN104332463B CN 104332463 B CN104332463 B CN 104332463B CN 201410408963 A CN201410408963 A CN 201410408963A CN 104332463 B CN104332463 B CN 104332463B
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- Prior art keywords
- semiconductor chip
- multichip device
- conducting element
- multichip
- contact area
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Abstract
一种多芯片器件,包括布置在第一载体上的第一半导体芯片和布置在第二载体上的第二半导体芯片。所述多芯片器件进一步包括将所述第一半导体芯片与所述第二半导体芯片电耦合的导电元件。所述导电元件包括第一暴露接触区域。
Description
技术领域
本公开涉及多芯片器件以及用于制造多芯片器件的方法。
背景技术
电子器件可以包括相互电连接的多个半导体芯片。必须不断改进这样的多芯片器件以及用于制造多芯片器件的方法。可能期望改进多芯片器件的性能和质量。特别是,可能期望提高集成密度并改进多芯片器件的热管理。
发明内容
根据多芯片器件的一个实施例,多芯片器件包括布置在第一载体上的第一半导体芯片,布置在第二载体上的第二半导体芯片,以及将第一半导体芯片与第二半导体芯片电耦合的导电元件。所述导电元件包括第一暴露接触区域。
根据多芯片器件的另一个实施例,多芯片器件包括第一半导体芯片,第二半导体芯片,和包括第一端部区段、第二端部区段和第三端部区段的T形导电元件。第一端部区段与第一半导体芯片电耦合。第二端部区段与第二半导体芯片电耦合。第三端部区段包括暴露接触区域。
根据多芯片器件的又一个实施例,多芯片器件包括第一半导体芯片,第二半导体芯片,以及包括第一部分和与所述第一部分基本上垂直的第二部分的L形导电元件。所述第一部分将第一半导体芯片与第二半导体芯片电耦合。所述第二部分包括暴露接触区域。
本领域技术人员在阅读下文的详细描述时和查看附图时,将认识到附加特征和优点。
附图说明
包括附图以提供对各方面的进一步理解,以及将附图并入本说明书中并构成本说明书的一部分。附图图示了各方面,并与描述一起用于解释各方面的原理。其他方面和各方面的许多预期优点在通过参考下文的详细描述使它们变得更好理解时,将被容易地理解。附图的元素相对于彼此不一定是按比例。相同的附图标记可以指定对应的相似部分。
图1示意性图示出根据一个实施例的多芯片器件的截面视图。
图2示意性图示出根据另一个实施例的多芯片器件的截面视图。
图3示意性图示出根据又一个实施例的多芯片器件的截面视图。
图4A和4B示意性图示出根据一个实施例的用于制造多芯片器件的方法的相应截面视图。
图5A到5D示意性图示出根据另一个实施例的用于制造多芯片器件的方法的相应截面视图。
图6示意性图示出根据一个实施例的多芯片器件的截面视图。
图7示意性图示出根据另一个实施例的多芯片器件的截面视图。
图8图示出半桥电路的示意图。
具体实施方式
在下文的详细描述中,对形成其一部分的附图进行参考,并且在附图中通过图示方式示出其中可以实践本公开的具体方面。在这方面,方向性术语,例如“顶部”、“底部”、“前面”、“后面”等等,可以参照被描述的附图的取向来使用。因为所描述的器件的部件可以被放置在多个不同的方向上,方向性术语可以被用于说明的目的而决不是限制性的。要以理解的是,在不背离本公开的范围的情况下可以利用其他方面并且可以进行结构上或逻辑上的改变。因此,下文的详细描述不以限制意义来进行,并且本公开的范围由所附权利要求所限定。
如本说明书中所采用的,术语“耦合的”和/或“电耦合的”,不意指元件必须被直接耦合在一起。介入元件可以被提供在“耦合的”或“电耦合的”元件之间。
本文描述了器件和用于制造此类器件的方法。要理解的是,连同所描述器件做出的注解也可以适用于对应的方法,反之亦然。例如,如果描述了器件的具体部件,则用于制造器件的对应方法可以包括以合适方式提供该部件的动作,即使附图中没有明确地描述或图示出这种动作。此外,要理解的是,本文描述的各种示例性方面的特征可以相互组合,除非另外具体指出。
本文所描述的器件可以包括一个或多个半导体芯片。半导体芯片可以是不同类型的,并且可以由不同技术来制造。例如,半导体芯片可以包括集成的电学、光电或机电电路,或无源元件。集成电路可以被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储器电路、集成无源元件,或者微机电***,该微机电***可以包括微机电结构,例如桥接器(bridge)、薄膜或舌结构。半导体芯片不需要由特定的半导体材料来制造,例如,Si、SiC、SiGe、GaAs,并且此外可以包含并非半导体的无机和/或有机材料,例如绝缘体、塑料或金属。此外,半导体芯片可以是封装或非封装的。
特别地,半导体芯片可以包括一个或多个功率半导体。半导体芯片(或功率半导体芯片)可以具有垂直结构,即,半导体芯片可以被制作为使得电流可以在垂直于半导体芯片的主面的方向上流动。具有垂直结构的半导体芯片可以在其两个主面上具有电极,即,在其顶侧和底侧上。特别地,功率半导体芯片可以具有垂直结构,并且在两个主面上都可以具有负载电极。例如,垂直功率半导体芯片可以被配置为功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、JFET(结型栅场效应晶体管)、超结器件、功率双极型晶体管,等等。功率MOSFET的源极电极和栅极电极可以位于一个面上,而功率MOSFET的漏极电极可以被布置在另一个面上。此外,本文所描述的器件可以包括集成电路,以控制功率半导体芯片的集成电路。
半导体芯片可以具有接触垫(或接触元件或接触端子或接触电极),其可以允许与包括在半导体芯片中的集成电路一起构成电接触。对于功率半导体芯片的情况,接触垫可以对应于栅极电极、源极电极、或漏极电极。接触垫可以包括可以被施加到半导体材料的一个或多个金属层。金属层可以用任何期望的几何形状和任何期望的材料成份来制造。任何期望的金属或金属合金,例如铝、钛、金、银、铜、钯、铂、镍、铬、和镍钒中至少一种,可以被用作所述材料。金属层不需要是均一的或仅由一种材料制造,即,在金属层中包含各种成份和浓度的材料是可能的。
本文所描述的器件可以包括其上方(或者其上)布置了半导体芯片的载体。该器件不被限制于仅包括一个单个载体,而是可以包括多个载体。此外,该器件的半导体芯片可以不是排他地仅被布置在一个载体上方(或之上),而是还可以被布置在多个载体上方(或之上)。载体可以由金属、合金、电介质、塑料、陶瓷或其组合来制造。载体可具有均一的结构,但也可以提供如具有电学再分布功能的导通路径的内部结构。此外,载体的覆盖区(footprint)可以取决于布置在载体上的半导体芯片的数量和覆盖区。也就是说,载体可以尤其包括配置成承载半导体芯片的安装区域。用于载体的示例是管芯垫(die pad)、包括管芯垫的引线框架,或者包括一个或多个再分布层的陶瓷基板。
在一个示例中,载体可以包括可以具有任何形状、尺寸和材料的引线框架。引线框架可以被构造为使得管芯垫(或芯片岛区(chip island))和引线被形成。在制作器件期间,管芯垫和引线可以被相互连接。管芯垫和引线还可以由一块构成。管芯垫和引线可以在制作过程中以将一些管芯垫与引线分离的目的通过连接手段而在相互之间连接。这里,将管芯垫与引线分离可以通过机械锯切、激光束、切割、冲压、碾磨、蚀刻、和任何其他合适的技术中的至少一种来执行。引线框架可以是导电的。例如,其可以完全由金属和/或金属合金来制作,尤其是由铜、铜合金、镍、铁镍、铝、铝合金、钢、不锈钢、和其他合适的材料中的至少一种来制作。引线框架可镀有导电材料,例如铜、银、钯、金、镍、铁镍、和镍磷中的至少一种。引线框架则还可以被称为“预镀引线框架”。要注意的是,尽管引线框架可以是导电的,但管芯垫的任意选择可以是相互电绝缘的。
本文所描述的器件可以包括导电元件。例如,导电元件可以被配置成将第一半导体芯片与第二半导体芯片电连接,或者被配置成在半导体芯片和布置在器件外部的部件之间提供电连接。在一个示例中,导电元件可以包括引线框架的一部分。因此,结合上文所描述的引线框架所做出的所有以上注解也可以适用于导电元件。在另一示例中,导电元件可以包括一个或多个接触夹片(clip)。结合上文所描述的引线框架所做出的所有以上注解也可以适用于接触夹片。接触夹片的形状不一定被限制为特定的尺寸或特定的几何形状。接触夹片可以通过冲压、冲孔、压制、切割、锯切、碾磨和任何其他合适的技术中的至少一种来制作。导电元件和半导体芯片的接触垫之间的接触可以通过任何合适的技术来建立。在一个示例中,导电元件可以被焊接到其他部件,例如通过采用扩散焊接过程。
本文所描述的器件可以包括封装材料,其可以至少部分地覆盖器件的一个或多个部件。封装材料可以是电绝缘的,并且可以形成封装体。封装材料可以包括任何合适的硬质塑料(duroplastic)、热塑性或热固性材料、模塑化合物、或叠层(半固化片(prepreg))。可使用各种技术来用封装材料封装部件,例如压膜成型、注塑成型、粉料成型、液体成型和层叠中的至少一种。
本文描述的器件可以包括一个或多个无源电子部件。例如,无源电子部件可以被集成在半导体材料中。替换地,无源电子部件可以被布置在一个或多个层中,尤其是金属层。无源电子部件可以是或者可以包括任何种类的电阻器、电容器、如电感器或线圈的电感部件、天线,等等。任何合适的技术可以被用于制造无源电子部件。
图1至3图示出根据各种实施例的多芯片器件100至300。下文描述了与多芯片器件100至300类似的更详细的多芯片器件以及用于制造多芯片器件的方法。要理解的是,所描述的多芯片器件和方法的特征可以相互组合,除非另外具体指出。
图1示意性图示出根据一个实施例的多芯片器件100的截面视图。多芯片器件100可以包括可以被布置在第一载体3上的第一半导体芯片1。多芯片器件100可以进一步包括可以被布置在第二载体4上的第二半导体芯片2。多芯片器件100可以进一步包括导电元件5,该导电元件5可以将第一半导体芯片1与第二半导体芯片2电耦合。导电元件5可以包括第一暴露接触区域6。
图2示意性图示出根据另一个实施例的多芯片器件200的截面视图。多芯片器件200可以包括第一半导体芯片1和第二半导体芯片2。多芯片器件200可以进一步包括T形导电元件5,该T形导电元件5可以包括第一端部区段7、第二端部区段8和第三端部区段9。第一端部区段7可以与第一半导体芯片1电耦合,而第二端部区段8可以与第二半导体芯片2电耦合。第三端部区段9可以包括暴露接触区域6。
图3示意性图示出根据又一个实施例的多芯片器件300的截面视图。多芯片器件300可以包括第一半导体芯片1和第二半导体芯片2。多芯片器件300可以进一步包括L形导电元件5。L形导电元件5可以包括第一部分和与第一部分基本上垂直的第二部分。出于说明性的目的,示例性的虚线10将第一部分与第二部分分离。在示例性的图3中,第一部分被图示为水平部分,而第二部分被示为垂直部分。第一部分可以将第一半导体芯片1与第二半导体芯片2电耦合。第二部分可以包括暴露接触区域6。
图4A和4B示意性图示出根据一个实施例的用于制造多芯片器件的方法。由该方法得到的多芯片器件400的截面在图4B中被图示出。例如,多芯片器件400可以与图1的多芯片器件100类似。在图4A中,第一半导体芯片1可以被布置在第一载体3上,以及第二半导体芯片2可以被布置在第二载体4上。在图4B中,可以提供导电元件5,使得导电元件5将第一半导体芯片1与第二半导体芯片2电耦合。导电元件5可以包括第一暴露接触区域6。
图5A到5D示意性图示出根据另一个实施例的用于制造多芯片器件的方法。由该方法得到的示例性的所制造的多芯片器件500的截面在图5D中被示出。根据所描述的方法所制造的多芯片器件的细节同样可以被应用于根据本公开的任何其他多芯片器件。此外,图5A到5D中所示出的方法可以被看作图4A和4B中所图示的方法的实施方式。因此下文所描述的制造方法的细节同样可以被应用于图4A和4B的方法。
在图5A中,第一半导体芯片1可以被布置在第一载体3的上方(或之上)。半导体芯片1可以是功率半导体芯片,其具有面对第一载体3的第一主表面11,以及背对载体3的相对的第二主表面12。第一电接触13可以被布置在第一主表面11上方(或之上)。特别地,第一导电接触13可以包括第一半导体芯片1的漏极电极。第一主表面11的覆盖区可以是任意的。例如,该覆盖区可以具有矩形、圆形或方形形状。类似地,漏极电极13可以具有任意的尺寸或形状。特别地,漏极电极13可以覆盖第一主表面11的主要部分,并且更特别地,漏极电极13可以完全覆盖第一主表面11。
漏极电极13可以与第一载体3电耦合,该第一载体3可以由导电材料构成。在一个示例中,漏极电极13可以与第一载体3直接物理接触。在另一个示例中,另外的导电材料可以被布置在漏极电极13和第一载体3之间。这种附加的材料可以例如被形成为一个或多个材料层。在一个示例中,第一半导体芯片1可以借助于导电粘合剂来被附着到第一载体3。在另一个示例中,漏极电极13和第一载体3之间的连接可以通过使用烧结过程或扩散焊接过程来建立。此处,可以在漏极电极13和第一载体3之间出现中间金属相(inter-metallicphase)。结合漏极电极13和第一载体3之间的电连接所做出的描述还可以适用于本文所描述的任何其他电连接。
第二电接触14和第三电接触15可以被布置在第一半导体芯片1的第二主表面12上方(或之上)。特别地,第二电接触14可以包括第一半导体芯片1的栅极电极,以及第三电接触15可以包括第一半导体芯片1的源极电极。第二主表面12的覆盖区可以是任意的,并且可以与第一主表面11的覆盖区相一致。栅极电极14和源极电极15中的每个可以具有任意的尺寸或形状。特别地,栅极电极的尺寸可以小于源极电极的尺寸。例如,栅极电极14可以基本上被布置在(例如矩形的)第二主表面12的一角,而源极电极15可以基本上覆盖第二主表面12的其余部分。特别地,栅极电极14和源极电极15可以相互电绝缘。
第一载体3可以由任意的材料构成,并且可以具有任意的尺寸或形状。特别地,第一载体3可以包括结构化载体的一部分,例如,引线框架。第一载体的厚度t1可以尤其是小于大约1.5mm,更尤其是,小于大约1mm。第一载体3的覆盖区可以大于第一半导体芯片1的覆盖区,并因而大于漏极电极13的覆盖区。也就是说,漏极电极13的接触区域可以完全由第一载体3所覆盖。
在图5A中,第二半导体芯片2可以被布置在第二载体4上方(或之上)。第二半导体芯片2可以与第一半导体芯片1类似,使得结合第一半导体芯片1所做出的描述也可以适用于第二半导体芯片2。第二载体4可以包括可以相互电绝缘的第一子载体4A和第二子载体4B。例如,第二载体4可以是结构化载体的一部分,例如引线框架,其还包括第一载体3。第一子载体4A和第二子载体4B中的每个可以与第一载体3电绝缘。第一子载体4A和第二子载体4B的的厚度t2和t3可以分别与第一载体3的厚度t1类似。
第二半导体芯片2可以包括第一电接触16,例如源极电极,其被布置在第二半导体芯片2的面向第一子载体4A的主表面上方(或之上)。源极电极16可以与第一子载体4A电连接,其中,第一子载体4A的覆盖区可以尤其被选为大于源极电极16的覆盖区。第二半导体芯片2可以进一步包括第二电接触17,例如栅极电极,其被布置在第二半导体芯片2的面向第二子载体4B的主表面上方(或之上)。栅极电极17可以与第二子载体4B电连接,其中,第二子载体4B的覆盖区可以尤其被选为大于栅极电极17的覆盖区。第二半导体芯片2可以进一步包括第三电接触18,例如漏极电极,其被布置在第二半导体芯片2的背对第二载体4的主表面上方(或之上)。
在图5B中,可以提供第一导电元件19和第二导电元件20。在一个示例中,导电元件19、20中的至少一个可以包括结构化载体的一部分,例如引线框架的一部分。在另一个示例中,导电元件19、20中的至少一个可以包括夹片。导电元件19、20的厚度t4、t5、t6和t7可以处于从大约100微米至大约500微米的范围,更尤其是从大约150微米至大约250微米的范围。厚度t4、t5、t6和t7可以相互类似或可以相互不同。
第一导电元件19可以是T形。第一导电元件19可以包括水平部分和与水平部分基本上垂直布置的垂直部分。水平部分的端部区段可以与第一半导体芯片1的栅极电极14电连接。特别地,第一导电元件19的端部区段的(水平)覆盖区可以大于栅极电极14的覆盖区。也就是说,第一导电元件19可以完全覆盖栅极电极14的接触区域。第一导电元件19的水平部分的另外的端部区段可以包括暴露接触区域21。第一导电元件19的垂直部分的端部区段可以包括另外的暴露接触区域22。经由暴露接触区域21、22中的任一或两者,可以电接触第一半导体芯片1的栅极电极14。
第二导电元件20可以是T形。第二导电元件20可以包括水平部分和与水平部分基本上垂直布置的垂直部分。水平部分的端部区段可以与第一半导体芯片1的源极电极15电连接。此处,该端部区段的(水平)覆盖区可以大于源极电极15的覆盖区(或接触区域)。水平部分可以进一步与第二半导体芯片2的漏极电极18电连接。水平部分可以完全覆盖漏极电极18的接触区域。第二导电元件20因而可以提供第一半导体芯片1的源极电极15和第二半导体芯片2的漏极电极18之间的电连接。第二导电元件20的水平部分的端部区段可以包括暴露接触区域23。此外,第二导电元件20的垂直部分的端部区段可以包括另一个暴露接触区域24。经由暴露接触区域23、24中的任一或两者,可以电接触第一半导体芯片1的源极电极15和第二半导体芯片2的漏极电极18。
导电元件19、20和载体3、4被布置为使得所图示的多芯片器件的各种表面可以是共面的。例如,第一导电元件19的上表面和第二导电元件20的上表面可以是共面的。这可以支持向导电元件19、20的上表面上安装另外的部件和/或在导电元件19、20的上表面上沉积另外的材料层。此外,暴露接触区域22、24和载体3、4A和4B的下表面中的至少两个可以是共面的。这可以提供将多芯片器件安装在另外的部件上,例如印刷电路板(PCB)上的机会。PCB(未图示出)可以包括接触垫,暴露接触区域22、24和载体3、4A和4B的下表面中的至少一个可以与该接触垫连接。
在图5C中,多芯片器件的部件可以至少部分地由可选的封装材料25所封装。在一个示例中,封装材料25可以被施加为使得接触区域21、22、23、24和载体3、4A和4B的下表面中的一个或多个保持暴露,而多芯片器件的其余部件可以被封装。在其他示例中,多芯片器件的另外的部分可以保持暴露,即保持未被封装材料25所覆盖。在图5C中,封装材料25至少部分地覆盖导电元件19、20的上表面。在另一个示例中,导电元件19、20的上表面可以保持未被封装材料25所覆盖。封装材料25可以尤其被形成为使得封装材料25的下表面26可以与暴露接触区域22、24和载体3、4A和4B的下表面中的至少一个共面。这可以支持在另外的部件(例如PCB)上安装封装的多芯片器件。
暴露接触区域21、22、23、24中的至少一个可以被配置成在相应的导电元件19、20和布置在多芯片器件外部的部件之间提供电耦合。导电元件19、20因而可以经由暴露接触区域21、22、23、24在半导体芯片1、2和外部部件之间提供直接电连接,而不接触载体3、4中的任意。例如,部件在其未被封装材料25所封装(或覆盖)时可以被定义为“外部的”。替换地,当经由布置在多芯片器件的***上的接触区域,例如,经由暴露接触区域21、22、23、24,来在部件和半导体芯片1、2之间建立电连接时,部件可以被定义为“外部的”。类似的,当接触区域未被材料所覆盖,使得外部部件可以(直接)与该接触区域电连接时,该接触区域可以例如被定义为“暴露的”。
在图5D中,至少部分地移除封装材料25,使得导电元件19、20的上表面27A、27B中的至少一个变为暴露。可以已经执行如图5C中所示和上文所描述的封装的动作,使得将封装材料25从导电元件19、20的上表面27A、27B移除。任何合适的技术可以被用于移除封装材料25。特别地,可以移除封装材料25,使得导电元件19、20的上表面27A、27B和封装材料25是共面的。暴露导电元件19、20可以提供将另外的部件连接到导电元件19、20的可能性。另外,暴露导电元件19、20可以支持在远离多芯片器件500的方向上的散热。
在图5D中,第二导电元件20是T形,并且被布置为使得暴露接触区域24基本上被布置在第一载体3和第二载体4之间。图5D的布置是示例性的,并且不同设计的类似布置也是可能的。例如,第二导电元件20可以是L形,例如,如图3中所图示的,使得暴露接触区域24可以基本上被布置为紧邻载体3、4之后,而不是在载体3、4之间。在另一个示例中,第二导电元件20可以包括一个或多个附加垂直部分。例如,附加垂直部分可以被布置在子载体4B的右侧,其中,垂直部分的端部部分可以提供附加暴露接触区域。暴露接触区域可以与暴露接触区域22、24、封装材料25的下表面和载体3、4A、4B的下表面中至少一个共面。在附加垂直部分的情况下,第二导电元件20的至少一部分可以是U形。
上文描述的方法可以包括本文中未明确图示出的另外的动作。例如,另外的部件可以被布置在多芯片器件500的上表面27A、27B中的至少一个上方(或之上)。在一个示例中,热沉(heat sink)可以被安装在多芯片器件500的上表面27上。在另一个示例中,无源电子部件可以被布置在导电元件19、20之一的上方(或之上)。无源电子部件可以与相应的导电元件19、20电连接。例如,电容器或电感器可以被布置在第一半导体芯片1的源极电极15和第二半导体芯片2的漏极电极18之间。
多芯片器件500可以被配置成操作为半桥电路。结合图8描述了半桥电路800的示例性示意图。特别地,这样的半桥电路可以包括高侧(high side)开关(S1)和低侧(lowside)开关(S2)。当使用图5D的多芯片器件500作为半桥电路时,第一半导体芯片1可以包括高侧开关,以及第二半导体芯片2可以包括低侧开关。
图5A到5D的方法和多芯片器件500可以具有如下效果。也可以结合根据本公开的任何其他多芯片器件或方法来观察此类效果。所列的效果不是排他的,也不是限制性的。
多芯片器件500可以被直接安装在另外的部件上,例如,PCB。在多芯片器件500和该多芯片器件500可以被安装于其上的另外的部件之间,不需要另外的辅助载体。
与其他多芯片器件相比,为了提供类似数量的电连接和电接触区域,根据本公开的多芯片器件可以要求降低数量的导电元件。
与其他多芯片器件相比,根据本公开的多芯片器件可以具有增加的集成密度。
与其他多芯片器件相比,根据本公开的多芯片器件可以提供由导电元件连接的部件之间的导电性。
与用于制造多芯片器件的其他方法相比,根据本公开的方法可以包括降低数量的制造动作。
与其他多芯片器件相比,根据本公开的多芯片器件可以提供简化的设计和结构。
根据本公开的方法可以提供用于有效制造模块电路的机会。
与其他多芯片器件相比,根据本公开的多芯片器件可以支持远离多芯片器件方向上的散热。特别地,也许可能提供在暴露接触表面处的直接热降低。
根据本公开的多芯片器件的设计和结构可以支持在多芯片器件上安装另外的部件。
结合图5A到5D所描述的方法已经基于两个半导体芯片1、2和两个载体3、4而被描述。然而,可以基于任意数量的半导体芯片和载体来执行类似的方法。也就是说,取决于多芯片器件的期望功能,所制造的多芯片器件还可以包括附加半导体芯片和/或附加载体。此外,可以应用图5A到5D的方法,使得可以制造多个多芯片器件。例如,结构化载体或包括多个区段的引线框架可以被使用,其中,每个区段包括如图5A中所示的第一载体和第二载体。这些区段中的每个可以根据上文描述的方法来被处理。在另外的动作中,得到的结构可以然后被分离成多个多芯片器件,其中每个多芯片器件可以类似于例如多芯片器件500。例如,在图5C或图5D的动作之一之后,可以执行分离成多个多芯片器件。任何合适的技术可以被用于分离该结构,例如锯切、蚀刻、切割、切片等等中的至少一个。
图6示意性图示出根据一个实施例的多芯片器件600的截面视图。多芯片器件600可以类似于图5D的多芯片器件500。结合图5A到5D的描述因而还可以适用于图6的多芯片器件600。在图6中,第一导电元件19和第二导电元件20中的每个可以包括夹片。夹片可以被配置成提供重新布线(或再分布)以及暴露接触区域,该暴露接触区域可以被用于将外部部件连接到多芯片器件600。多芯片器件600不一定包括布置在图5D的多芯片器件500的侧表面上的暴露接触区域21、23。代替的,封装材料25可以被布置为使得可以通过封装材料25形成多芯片器件600的侧表面28、29。
图7示意性图示出根据另一个实施例的多芯片器件700的截面视图。多芯片器件700可以类似于上文描述的一个或多个多芯片器件。结合前述附图所做出的描述因而还可以适用于多芯片器件700。特别地,多芯片器件700可以类似于图5B的多芯片器件。与图5B相比,导电元件19、20的垂直部分的至少一个端部区段可以被加宽。在示例性图7中,只有第一导电元件19的垂直部分的端部区段被加宽,这可以导致例如暴露接触区域22的增加的接触表面。取决于多芯片器件700的期望功能,可以灵活选择例如暴露接触区域22的覆盖区。通过应用另外的动作,可以处理图7的多芯片器件700。例如,可以应用图5C和/或5D的动作。
图8图示出半桥电路800的示意图。根据本公开的多芯片器件可以被配置成操作为这样的半桥电路。半桥电路800可以被布置在节点N1和N2之间。半桥电路可以包括串联连接的开关S1和S2。功率半导体芯片1和2,如例如5D中所示的多芯片器件500,可以被实现为开关S1和S2。恒定电势可以被施加到节点N1和N2。例如,高电势,诸如10、50、100、200、500或1000V或任何其他电势,可以被施加到节点N1,以及低电势,例如0V,可以被施加到节点N2。因此,第一半导体芯片1可以被配置成充当高侧开关(S1),而第二半导体芯片2可以被配置成充当低侧开关(S2)。开关S1和S2可以在从1kHz到100MHz的范围内的频率下被切换,但是切换频率也可以在此范围之外。这意味着,在半桥电路的操作期间,可以将变化的电势施加到布置在开关S1和S2之间的节点N3。节点N3的电势可以在低电势和高电势之间的范围内变化。
半桥电路可以例如在用于转换DC电压的电子电路(所谓的DC-DC转换器)中被实现。DC-DC转换器可以被用于将由电池或可再充电电池所提供的DC输入电压转换成与下游所连接的电子电路的需求相匹配的DC输出电压。DC-DC转换器可以被体现为降压(stepdown)转换器,其中输出电压小于输入电压,或者升压(step up)转换器,其中输出电压高于输入电压。若干MHz或更高的频率可以被施加到DC-DC转换器。此外,高达50A或甚至更高的电流可以流过DC-DC转换器。
虽然可以相对于仅若干个实施方式中的一个已经公开了本公开的特定特征或方面,但这种特征或方面可以在对于任何给定的或特定的应用而言是期望的或有利的时与其他实施方式的一个或多个其他特征或方面进行组合。此外,就在详细描述或权利要求中使用术语“包括”、“具有”、“有”或其其他变型而言,这种术语意在与类似于术语“包含”类似的方式而是包含性的。而且,术语“示例性的”仅意指作为示例,而不是最好或最优。还要理解的是,出于简化和易于理解的目的,本文所描绘的特征和/或元件以相对彼此的特定尺寸来图示出,并且实际尺寸可以基本上不同于本文所图示出的尺寸。
尽管本文已经图示出和描述了具体的实施例,但本领域技术人员将理解的是,在不背离本公开范围的情况下,可以用各种替代和/或等价的实施方式来代替所示出或描述的具体方面。本申请意在覆盖本文中所讨论的具体方面的任何改编或变化。因此,所意在的是,本公开仅由权利要求及其等价方式所限定。
Claims (20)
1.一种多芯片器件,包括:
第一半导体芯片,其被布置在第一载体上;
第二半导体芯片,其被布置在第二载体上;以及
导电元件,其将所述第一半导体芯片与所述第二半导体芯片电耦合,其中所述导电元件包括第一暴露接触区域。
2.权利要求1的多芯片器件,其中所述导电元件包括接触夹片和第一引线框架的一部分中的至少一个。
3.权利要求1的多芯片器件,其中,所述第一暴露接触区域被配置成在所述导电元件和所述多芯片器件外部的部件之间提供电耦合。
4.权利要求1的多芯片器件,其中,所述导电元件包括第一部分和与所述第一部分基本上垂直的第二部分,其中,所述第一部分将所述第一半导体芯片与所述第二半导体芯片电耦合,并且其中,所述第二部分的端部区段包括第一暴露接触区域。
5.权利要求1的多芯片器件,其中,所述导电元件是U型、T形或L形。
6.权利要求1的多芯片器件,其中所述第一载体与所述第二载体电绝缘。
7.权利要求1的多芯片器件,进一步包括:
引线框架,其包括所述第一载体和所述第二载体。
8.权利要求1的多芯片器件,其中,所述第一暴露接触区域基本上被布置在所述第一载体和所述第二载体之间。
9.权利要求1的多芯片器件,其中,所述第一暴露接触区域与所述第一载体的表面和所述第二载体的表面中的至少一个共面。
10.权利要求1的多芯片器件,进一步包括:
至少部分地封装所述导电元件的封装材料。
11.权利要求10的多芯片器件,其中,所述第一暴露接触区域与所述封装材料的表面共面。
12.权利要求1的多芯片器件,其中所述第一半导体芯片和所述第二半导体芯片中的至少一个包括功率半导体器件。
13.权利要求1的多芯片器件,其中,所述第一半导体芯片包括源极接触,所述第二半导体芯片包括漏极接触,并且所述导电元件将所述源极接触与所述漏极接触电耦合。
14.权利要求1的多芯片器件,进一步包括:
半桥电路,其包括高侧开关和低侧开关,其中,所述第一半导体芯片包括所述高侧开关,以及所述第二半导体芯片包括所述低侧开关。
15.权利要求1的多芯片器件,其中,所述导电元件包括第二暴露接触区域。
16.权利要求15的多芯片器件,进一步包括:
与所述第二暴露接触区域电耦合的无源电子部件。
17.一种多芯片器件,包括:
第一半导体芯片;
第二半导体芯片;以及
T形导电元件,其包括第一端部区段、第二端部区段和第三端部区段,其中,所述第一端部区段与所述第一半导体芯片电耦合,所述第二端部区段与所述第二半导体芯片电耦合,以及所述第三端部区段包括暴露接触区域。
18.权利要求17的多芯片器件,其中,所述导电元件包括接触夹片和第一引线框架的一部分中的至少一个,以及其中,所述第一半导体芯片和所述第二半导体芯片中的至少一个包括功率半导体器件。
19.一种多芯片器件,包括:
第一半导体芯片;
第二半导体芯片;以及
L形导电元件,其包括第一部分和与所述第一部分基本上垂直的第二部分,其中,所述第一部分将所述第一半导体芯片与所述第二半导体芯片电耦合,并且所述第二部分包括暴露接触区域。
20.权利要求19的多芯片器件,其中,所述导电元件包括接触夹片和第一引线框架的一部分中的至少一个,以及其中,所述第一半导体芯片和所述第二半导体芯片中的至少一个包括功率半导体器件。
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US13/940,577 US8884420B1 (en) | 2013-07-12 | 2013-07-12 | Multichip device |
US13/940577 | 2013-07-12 |
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US9570379B2 (en) * | 2013-12-09 | 2017-02-14 | Infineon Technologies Americas Corp. | Power semiconductor package with integrated heat spreader and partially etched conductive carrier |
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JP6318064B2 (ja) * | 2014-09-25 | 2018-04-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
DE102015102453A1 (de) | 2015-02-20 | 2016-08-25 | Heraeus Deutschland GmbH & Co. KG | Bandförmiges Substrat zur Herstellung von Chipkartenmodulen, Chipkartenmodul, elektronische Einrichtung mit einem derartigen Chipkartenmodul und Verfahren zur Herstellung eines Substrates |
US10892210B2 (en) * | 2016-10-03 | 2021-01-12 | Delta Electronics, Inc. | Package structures |
DE102017207564A1 (de) * | 2017-05-05 | 2018-11-08 | Robert Bosch Gmbh | Halbleitermodul |
KR102048478B1 (ko) * | 2018-03-20 | 2019-11-25 | 엘지전자 주식회사 | 양면냉각형 파워 모듈 및 그의 제조 방법 |
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