CN104332422A - Defect detection method of integrated circuit layouts in different directions - Google Patents
Defect detection method of integrated circuit layouts in different directions Download PDFInfo
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- CN104332422A CN104332422A CN201410441475.4A CN201410441475A CN104332422A CN 104332422 A CN104332422 A CN 104332422A CN 201410441475 A CN201410441475 A CN 201410441475A CN 104332422 A CN104332422 A CN 104332422A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- Microelectronics & Electronic Packaging (AREA)
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
The invention relates to the technical field of integrated circuits and particularly relates to a defect detection method of integrated circuit layouts in different directions. Through calling of an optical defect detection device, data of patterns in two different directions of design circuits of a static memory in a wafer is obtained and according to a preset direction conversion relation in the optical defect detection device, direction conversion from one direction pattern to another direction pattern is carried out and defect detection is carried out. The technical scheme is capable of realizing one-time scanning detection of static-memory design circuits, which are different in direction but repeated in structure, according to a preset detection direction so that the defect detection precision is improved significantly and the defect detection cost is reduced at the same time.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of defect inspection method of different directions integrated circuit diagram.
Background technology
In existing technical field, the manufacture craft of a chips often comprises the operation of hundreds of step, and main technical module can be divided into several major parts such as photoetching, etching, ion implantation, film growth and cleaning.Along with the development of integrated circuit technology and constantly reducing of characteristic size, the distribution of on-chip circuitry also becomes increasingly complex, and the slight errors of any link all will cause the inefficacy of whole product, so just more and more stricter to the requirement of technology controlling and process.In order to the defect of product can be found timely, generally the detection of a considerable amount of defect detection equipment to On-line Product is all configured with in the production process of reality, the principle of defects detection is the signal being obtained several chip by equipment, and then carry out the comparison of data, as Fig. 1 a ~ 1c is expressed as 3 adjacent chips, by gathering the graph data of 3 chips simultaneously, then drawn the position of signal difference by the comparison of B chip and A chip; The position of signal difference is drawn again by the comparison of B chip and C chip; So in these two comparing results, the same position of difference letter is exactly the position of the defect that B chip detects.And structure that is the highest for on-chip circuitry density and that repeat, as shown in Figure 2, detect to realize defective, what take is that comparing between repetitive structure is to determine the position of defect.But, due to the consideration of chip design itself, often there is the static memory circuit structure of different directions on a single die, Scanning Detction repeatedly can only be taked just to complete the defects detection of different directions static memory according to current method, this efficiency that will affect detection greatly makes production cost significantly increase.
Chinese patent (CN103065993A) discloses a kind of wafer defect detection system, comprise Fourier filters, it comprises the multiple blocking units being positioned at light intensity signal collection scope, and described blocking unit is the first blocking unit of first direction arrangement and/or the second blocking unit of second direction arrangement; Handover module is connected with described fourier filter, according to detection side to described blocking unit being switched to described first blocking unit or described second blocking unit; And detector, detect the light of Fourier filters transmission.The present invention is also corresponding provides a kind of wafer defect detection method.
A kind of wafer defect detection system and detection method disclosed in above-mentioned patent, the wafer defect that just can complete in a transport process on different directions figure detects, improve the efficiency of defects detection, but the design of this wafer defect detection system is comparatively complicated, cost is higher, cannot carrying out on first direction with the contrast of structured data in second direction and then carry out defects detection, make it when defects detection, defects detection precision is restricted.
Summary of the invention
In view of the above problems, the invention provides a kind of defect inspection method of different directions integrated circuit diagram, can be solved by the method and cannot to carry out on first direction with the contrast of the repetitive structure data in second direction and then carry out defects detection, make it when defects detection, the defect that defects detection precision is restricted.
The present invention solves the problems of the technologies described above adopted technical scheme:
A defect inspection method for different directions integrated circuit diagram, wherein, described method comprises:
Step S1, the wafer providing to have an integrated circuit diagram, described integrated circuit diagram comprises some the first circuit regions along first direction distribution and the second circuit district along second direction distribution, and described first circuit region is identical with the structure in second circuit district;
Step S2, call a checkout equipment and detect described integrated circuit diagram, obtain described first circuit region and the described second circuit district graph data on respective direction;
Step S3, preset the direction transformational relation of described checkout equipment to described figure, by described first circuit region and described second circuit district, the Graphic Exchanging on respective direction is same direction, and detects.
Step S4, obtain described first circuit region graph data in a second direction, and compare with described second circuit district graph data in a second direction; Or
Obtain described second circuit district graph data in a first direction, and compare with described first circuit region graph data in a first direction, and then complete the defects detection to described wafer.
Preferably, the defect inspection method of above-mentioned different directions integrated circuit diagram, wherein, described first circuit region and described second circuit district are static memory design circuit.
Preferably, the defect inspection method of above-mentioned different directions integrated circuit diagram, wherein, the direction in the vertical described second circuit district, direction of described first circuit region.
Preferably, the defect inspection method of above-mentioned different directions integrated circuit diagram, wherein, described checkout equipment is an optical defect checkout equipment.
Technique scheme tool has the following advantages or beneficial effect:
The defect inspection method of a kind of different directions integrated circuit diagram disclosed by the invention, the neither equidirectional graph data of the static memory design circuit in wafer is obtained by calling an optical defect checkout equipment, and according to the direction transformational relation preset in optical defect checkout equipment to wherein a kind of direction figure to the conversion of another kind of direction figure travel direction, and carry out defects detection; Therefore technical solution of the present invention can detect to realizing realizing one-off scanning to the static memory design circuit of different directions repetitive structure according to the detection side preset, and reduces the cost of defects detection while greatly improving defects detection precision.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part deliberately proportionally not draw accompanying drawing, focuses on indicating purport of the present invention.
Fig. 1 a ~ 1c is that the data of 3 chipsets adjacent in prior art compare schematic diagram;
Fig. 2 is different directions repetitive structure static memory design circuit schematic diagram in prior art chips;
Fig. 3 a and Fig. 3 b is the static memory design circuit schematic diagram of different directions in the inventive method;
Fig. 4 is the schematic diagram that in the inventive method, wafer detects downwards;
Fig. 5 a and Fig. 5 b is the pictorial diagram of the static memory design circuit of different directions repetitive structure in the inventive method;
Fig. 6 is the schematic diagram that in the inventive method, wafer detects to the right;
Fig. 7 is the figure direction transition diagram of the static memory design circuit of different directions repetitive structure in the inventive method.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
For realizing detecting the defect one-off scanning of different directions integrated circuit diagram, the cost of defects detection is reduced while improving defects detection precision, the invention provides a kind of defect inspection method of different directions integrated circuit diagram, concrete as shown in Fig. 3 a ~ 7:
Step S1, provide a wafer, in this wafer, preparation has integrated circuit diagram, in an embodiment of the present invention, integrated circuit diagram comprises some the first circuit regions along first direction distribution and the second circuit district along second direction distribution, and the first circuit region is identical with the structure in second circuit district, preferably, the structure of this first circuit region and the detection side of follow-up optical defect checkout equipment are to having repeatability.
In an embodiment of the present invention, the first circuit region and second circuit district are all preferably static memory design circuit.
As shown in Figure 3 a, this static memory design circuit is the most responsive surveyed area of defect, and very high and its distribution of the density of texture of as can be seen from the figure static memory design circuit is in the arrangement periodically repeated (namely first circuit region A, B and C is the static memory design circuit of same structure and A, B and C all periodicity repeated arrangement), wherein Fig. 3 b structure is identical with Fig. 3 a, does not repeat them here.
Optional but in nonrestrictive embodiment in one, as shown in Figure 3 a, by in static memory design circuit A, B and C of some same structures with the direction of grid structure for reference, Fig. 3 a is set to first circuit region (i.e. static memory design circuit) of first direction (in figure X-direction) repetitive structure, equally, Fig. 3 b is set to the second circuit district of second direction (in figure Y direction) repetitive structure; This first direction is corresponding with second direction, those skilled in the art should be understood to the direction of grid structure in Fig. 3 a as reference, also the first circuit region of second direction (being set to Y direction) repetitive structure can be set to, as long as reach object of the present invention.
Step S2, pre-set detection side that the moving direction of this wafer and checkout equipment detect wafer to, as shown in Figure 4, after presetting the constitutional repeating unit (a defects detection module of this checkout equipment to enter for least unit with this constitutional repeating unit this first circuit region and second circuit district are detected) in the first circuit region and second circuit district simultaneously, call above-mentioned checkout equipment to be detected the first circuit region of first direction and the second circuit district of second direction by this constitutional repeating unit, obtain the graph data of second direction in the graph data of first direction in the first circuit region and second circuit district simultaneously, as shown in figure 5 a and 5b.
Fig. 4 is expressed as the movement of wafer along above-mentioned first direction, and checkout equipment detects downwards wafer, wherein those skilled in the art according to different process requirements, can preset the orientation that different checkout equipments detects wafer, detect the orientation of wafer for right as Fig. 6 is expressed as checkout equipment.
Preferably, this checkout equipment is an optical defect checkout equipment.
Step S3, in advance prior to setting the direction transformational relation of the figure of second direction in the figure of first direction in the first circuit region and second circuit district in above-mentioned optical defect checkout equipment, the first circuit region is changed consistent with the direction of second circuit district figure.
In an embodiment of the present invention, as shown in Figure 7, because pre-setting optical defect checkout equipment to the downward orientation detection of wafer, therefore carrying out in the follow-up process that graphical information is detected, this defect detection equipment only carries out the identifying processing of defect information to the first direction figure of the first circuit region, therefore the direction of the figure in second circuit district is converted to the direction of the figure of the first circuit region by optical defect checkout equipment automatically according to the above-mentioned direction transformational relation set, the direction of two figures is changed consistent (if pre-set optical defect checkout equipment to wafer orientation detection to the right, then the direction of the figure of the first circuit region is converted to the direction of the figure in second circuit district by optical defect checkout equipment according to the above-mentioned direction transformational relation set).
Step S4, when optical defect checkout equipment is according to above-mentioned transformational relation automatic acquisition second circuit district, the direction graph data in a first direction set, and compare with the first circuit region graph data in a first direction and (if pre-set optical defect checkout equipment to wafer orientation detection to the right, obtain the first circuit region graph data in a second direction, and compare with second circuit district graph data in a second direction) and then the defects detection that completes wafer, thus realize detecting the disposable Defect Scanning of the static memory design circuit of different directions repetitive structure.
Therefore, in technical solution of the present invention, because the structure of this first circuit region and the detection side of optical defect checkout equipment are to having repeatability, when defect detection equipment carries out data scanning to the first circuit region, the contrast carrying out data that can be synchronous and then complete the defects detection of the first circuit region on first direction; On the other hand, the second circuit plot structure of second direction and the detection side of optical defect checkout equipment are to not having repeatability, when defect detection equipment carries out data scanning to second circuit district, also need the conversion of travel direction relation just can carry out the contrast of data, also can carry out Data Comparison with the first circuit region, and then the disposable Defect Scanning of the static memory completing different directions structure detects simultaneously.
In addition, because the probability of the constitutional repeating unit simultaneously existing defects in same direction circuit district is larger, therefore when the graph data contrast carrying out same direction circuit district, may cannot carry out the detection identification of defect because constitutional repeating unit itself all has defect, the contrast that therefore the present invention carries out graph data by the circuit region carrying out first direction and second direction simultaneously can reduce the probability that cannot identify defect because constitutional repeating unit itself all has defect greatly.
Wherein those skilled in the art should be understood to the defects detection that the inventive method is applicable to the static memory design circuit of multiple direction repetitive structure, are not limited in the defects detection of the static memory design circuit of two kinds of direction repetitive structures in the present invention.Therefore the precision that the inventive method improves defects detection greatly in certain degree reduces the cost of defects detection simultaneously.
In sum, the defect inspection method of a kind of different directions integrated circuit diagram disclosed by the invention, the neither equidirectional graph data of the static memory design circuit in wafer is obtained by calling an optical defect checkout equipment, and according to the direction transformational relation preset in optical defect checkout equipment to wherein a kind of direction figure to the conversion of another kind of direction figure travel direction, and carry out defects detection; Therefore technical solution of the present invention can detect to realizing realizing one-off scanning to the static memory design circuit of different directions repetitive structure according to the detection side preset, and reduces the cost of defects detection while greatly improving defects detection precision.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1. a defect inspection method for different directions integrated circuit diagram, is characterized in that, described method comprises:
Step S1, the wafer providing to have an integrated circuit diagram, described integrated circuit diagram comprises some the first circuit regions along first direction distribution and the second circuit district along second direction distribution, and described first circuit region is identical with the structure in second circuit district;
Step S2, call a checkout equipment and detect described integrated circuit diagram, obtain described first circuit region and the described second circuit district graph data on respective direction;
Step S3, preset the direction transformational relation of described checkout equipment to described figure, by described first circuit region and described second circuit district, the Graphic Exchanging on respective direction is same direction, and detects.
Step S4, obtain described first circuit region graph data in a second direction, and compare with described second circuit district graph data in a second direction; Or
Obtain described second circuit district graph data in a first direction, and compare with described first circuit region graph data in a first direction, and then complete the defects detection to described wafer.
2. the defect inspection method of different directions integrated circuit diagram as claimed in claim 1, it is characterized in that, described first circuit region and described second circuit district are static memory design circuit.
3. the defect inspection method of different directions integrated circuit diagram as claimed in claim 1, is characterized in that, the direction in the vertical described second circuit district, direction of described first circuit region.
4. the defect inspection method of different directions integrated circuit diagram as claimed in claim 1, it is characterized in that, described checkout equipment is an optical defect checkout equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410441475.4A CN104332422A (en) | 2014-09-01 | 2014-09-01 | Defect detection method of integrated circuit layouts in different directions |
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| CN201410441475.4A CN104332422A (en) | 2014-09-01 | 2014-09-01 | Defect detection method of integrated circuit layouts in different directions |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545700A (en) * | 2018-11-30 | 2019-03-29 | 上海华力微电子有限公司 | Wafer defect scan method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266281A (en) * | 1999-02-24 | 2000-09-13 | 因芬尼昂技术北美公司 | Improved system and method for automatic photomask fault detection |
| CN101872715A (en) * | 2009-04-21 | 2010-10-27 | 南茂科技股份有限公司 | Wafer defect marking system |
| US7869966B2 (en) * | 2001-09-13 | 2011-01-11 | Hitachi, Ltd. | Inspection method and its apparatus, inspection system |
| CN102931116A (en) * | 2012-11-12 | 2013-02-13 | 上海华力微电子有限公司 | Synchronous defect detecting method for memorizer |
-
2014
- 2014-09-01 CN CN201410441475.4A patent/CN104332422A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266281A (en) * | 1999-02-24 | 2000-09-13 | 因芬尼昂技术北美公司 | Improved system and method for automatic photomask fault detection |
| US7869966B2 (en) * | 2001-09-13 | 2011-01-11 | Hitachi, Ltd. | Inspection method and its apparatus, inspection system |
| CN101872715A (en) * | 2009-04-21 | 2010-10-27 | 南茂科技股份有限公司 | Wafer defect marking system |
| CN102931116A (en) * | 2012-11-12 | 2013-02-13 | 上海华力微电子有限公司 | Synchronous defect detecting method for memorizer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545700A (en) * | 2018-11-30 | 2019-03-29 | 上海华力微电子有限公司 | Wafer defect scan method |
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Application publication date: 20150204 |