CN1043275C - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

Description

Semiconductor storage

The present invention relates to semiconductor storage, more specifically, for example relate to the technology of the batch EEPROM (erasable removing and programmable read only memory) that is used for high speed effectively and reads.

EEPROM is a Nonvolatile memory device in batches, and its function is to operate, and the method for electricity consumption is wiped all storage unit that form on the chip in batches, or wipes wherein several groups of storage unit.

Such batch EEPROM once mentioned in following data: IEEE ISSCC collection of thesis 152-153 page or leaf in 1980; IEEE ISSCC collection of thesis 76-77 page or leaf in 1987; With 1988 the 23rd volume IEEE solid-state circuit magazine 1157-1163 pages or leaves.

Figure 27 is the sectional structure chart that a batch EEPROM unit of being reported is propped up in international electronic installation meeting in 1987.Structurally this storage unit is all very similar with any common storage unit; In other words, it comprises an insulated door field effect transistor (be called MOSFET later on or abbreviate transistor as) in the two storied gate structure.In Figure 27, represent a P type silicon chip with reference to digital 8, the p type diffused layer that 11 representatives form on silicon chip 8,10 represent the low-density n type diffused layer that forms on silicon chip 8, and 9 represent the n type diffused layer that forms respectively on P type and n type diffused layer 11,10.Also have, with reference to the floating gate that digital 4 representatives form on thin oxide film 7 by P type silicon chip 8, the control gate that 6 representatives form on floating gate 4 by oxide film 7,3 represent drain electrode, and 5 represent the source electrode.In other words, the storage unit of Figure 27 generates with MOSFET in N raceway groove two storied gate structure, and deposit data is in transistor, and in fact data are that parameter as starting voltage leaves in the transistor.

Unless dated especially, below be used for store data in the described example transistor (being referred to as transistor later on) all be the N channel-type.The class of operation that data are write the operation of the storage unit among Figure 27 and EPROM by program seemingly.In other words, the operation that writes of program is following finishing: will attach near the thermal barrier that produced the drain region 9 of drain electrode 3 and inject floating gates 4.Since the program write operation, from the angle of control gate 6, the height when starting voltage of memory transistor ratio does not carry out the program write operation.

On the other hand, in erase operation, owing on source electrode 5, added high voltage, at control gate 4 be connected between the source region 9 of source electrode 5 and produced high electric field.Utilize tunnel(l)ing promptly to be drawn into source electrode 5 at the electronics of floating gate 4 stored by source region 9 by thin oxide film 7.Therefore, the data of being stored promptly are wiped free of.In other words, from the angle of control gate 6, erase operation has reduced the starting voltage of memory transistor.

In read operation, the voltage that is added on drain electrode 3 and the control gate 6 relatively is limited to little numerical value, to prevent having faint program to write to storage unit, just, stops undesirable carrier to inject floating gate 4.For example, low as voltage 1 volt is added on the drain electrode 3 and voltage low as 5 volts adds on the master control gate 6.These voltages apply up, and being used to detect the size of the channel current that flows to memory transistor and being used for decision institute's deposit data in storage unit is " 0 " or " 1 ".

The memory cycle that the read operation of memory transistor recited above is finished is slow in about 1 μ s.The present inventor pays special attention to the following fact: when data were exported, next address may be imported data, and they and consideration data can be with the high-speed and continuous series read-outs.

An object of the present invention is to provide a kind of semiconductor storage, it can be used for the high speed serialization reading of data and can reduce peak point current.

Another object of the present invention provides a kind of semiconductor storage, and it can be used to reduce the coupling effect of adjacent data line to data line.

With reference to the following description and drawings, can more clearly understand these and other purposes of the present invention and new feature.

Purpose of the present invention can be finished by following apparatus: a semiconductor storage, the data line of wherein numerous storage arrays that comprises storing semiconductor is arranged in matrix form, and these data lines that have high or low starting voltage according to institute's deposit data are divided into numerous simultaneously; And the detecting amplifier that is used for amplifying signal, they finish amplifieroperation in time dispersedly.In addition, first group and second group of detecting amplifier have been arranged corresponding to the odd and even number line of adjacent data line, they do following arrangement: when one group of detecting amplifier is sent output signal, word line promptly switches, this moment, another group detecting amplifier was arranged to finish the operation of amplifying signal, and institute's amplifying signal is to read in the storage unit corresponding to the word line that is switched.

Utilize above-mentioned semiconductor storage, because detecting amplifier scatter operation in time, therefore peak point current can reduce, again owing to alternately the odd and even number data line is finished read operation, so adjacent data line to the coupling noise of data line can reduce, and can finish the sequential serial high speed operation effectively.

Fig. 1 is a block diagram of implementing batch EEPROM of the present invention.

Fig. 2 is the base plate of above-mentioned storer and the schematic circuit of its peripheral hardware.

Fig. 3 is used to explain according to the data line of semiconductor storage of the present invention and the wiring diagram of the relation between the detecting amplifier.

Fig. 4 is used to explain according to the data line of semiconductor storage of the present invention and another wiring diagram of the relation between the detecting amplifier.

Fig. 5 is used to explain according to the data line of semiconductor storage of the present invention and another wiring diagram of the relation between the detecting amplifier.

The data line that Fig. 6 is before the present invention to be recognized and the wiring diagram of detecting amplifier example.

Fig. 7 is a basic waveform figure, is used to explain the read operation according to semiconductor storage internal circuit of the present invention.

Fig. 8 is the oscillogram that is used for explaining corresponding to the read operation example of Fig. 3 embodiment.

Fig. 9 is the sequential chart according to the continuous read operation of semiconductor storage of the present invention.

Figure 10 is the sequential chart according to another continuous read operation of semiconductor storage of the present invention.

Figure 11 is the sequential chart according to another continuous read operation of semiconductor storage of the present invention.

Figure 12 is the process flow diagram that is used to explain corresponding to the operation of the internal wiring of Fig. 9 operator scheme.

Figure 13 shows the process flow diagram be used to explain corresponding to the operation of the internal wiring of Figure 10 operator scheme.

Figure 14 shows the remainder be used to explain corresponding to the process flow diagram of the operation of the internal wiring of Figure 10 operator scheme.

Figure 15 shows the part be used to explain corresponding to the process flow diagram of the operation of the internal wiring of Figure 11 operator scheme.

Figure 16 shows the another part be used to explain corresponding to the process flow diagram of the operation of the internal wiring of Figure 11 operator scheme.

Figure 17 shows the remainder be used to explain corresponding to the process flow diagram of the operation of the internal wiring of Figure 11 operator scheme.

Figure 18 is a block diagram of implementing the major part of another semiconductor storage of the present invention.

Figure 19 is used to explain according to the data line of semiconductor storage of the present invention and the wiring diagram of the relation between the differential detection amplifier.

Figure 20 is used to explain according to the data line of semiconductor storage of the present invention and another wiring diagram of the relation between the differential detection amplifier.

Figure 21 is the oscillogram that is used to explain Figure 20 line loop operation example.

Figure 22 is used to explain according to the data line of semiconductor storage of the present invention and another wiring diagram of the relation between the differential detection amplifier.

Figure 23 is the oscillogram that is used to explain Figure 22 line loop operation example.

Figure 24 is used to explain according to another of semiconductor storage of the present invention read the block diagram of circuit.

Figure 25 is used to explain according to the data line of semiconductor storage of the present invention and another wiring diagram of the relation between detecting amplifier.

Figure 26 is the block diagram that for example uses according to the such data handling system of the microcomputer of semiconductor storage of the present invention.

Figure 27 is the principle sectional view of the example of conventional storage unit.

Figure 28 is the principle sectional view of another example of storage unit.

Fig. 1 is a block diagram of implementing batch EEPROM of the present invention.Any known semiconductor integrated circuit technique is used in and forms each piece circuit piece as shown in Figure 1 on the block semiconductor substrate, though unnecessary qualification, substrate material can be a monocrystalline silicon.

According to present embodiment, though needn't limit, memory array can comprise 4 block storage base plate MAT.Every block storage base plate has secondary code translator SUB-DCR, is used to produce word line WL and selects signal.In order to realize integrated level, the spacing of word line and word line is done very narrowly, and the secondary code translator between storer base plate MAT is the storer base plate MAT generation word line selection signal of both sides simultaneously.Shown in key drawing, the word line of storer base plate MAT alternately is connected to two secondary code translator SUB-DCR, and the latter is clipped in the middle storer base plate MAT.

Below apparent, the circuit of main code translator MAN-DCR is used to form signal, the latter is used to select one to select MOSFET, thereby selects numerous storage units that has, this circuit also is used to be provided with selection and the non-selection rank of secondary code translator SUB-DCR.Door code translator GDCR produces the storage unit that signal is used for selecting a storage block being selected by main code translator MAN-DCR.

Though needn't limit, the memory transistor that forms in storage base plate MAT can be finished simultaneously and wipe and the program write operation, and this makes its rely on tunnel current to launch electric charge therefrom to finish by electric charge being injected Fu Dong Men And.In addition, memory transistor can utilize tunnel current as shown in figure 27 to finish erase operation.

Though needn't limit, detecting amplifier SA can be divided into two groups as seeing clearly Chu later on, and the amplifieroperation of each detecting amplifier SA is then controlled by detecting amplifier control circuit SAC.Though needn't limit, but done following arrangement: two groups of detecting amplifiers are all encouraged in the initial read cycle and when being accompanied by reading continuously that word line switches subsequently, word line switches and carries out in the following moment: after the amplifieroperation that reads signal ended and one group of detecting amplifier of one group of detecting amplifier began, another group detecting amplifier SA provided the moment of a serial signal.

Detecting amplifier SA has latch function, when it when data line receives the essential read signal of amplifieroperation, it and data line are thrown off, and keep institute's amplifying signal so that amplify the Xin And that receives.Therefore, promptly exported by Y gate transmission line YG is signals selected by data output buffering OB.In the time of with this class signal output function, can carry out like that as mentioned previously corresponding to the word line switching of next address.

Status register SREG utilizes TS signal accepting state data, and where necessary from the outside by data output buffering OB display operation state.According to the present invention, the program write/erase operation of finishing the connected reference operation and mentioning in the past.Provide status register SREG, because need understand internal state from the outside in each operating period.

Voltage generation circuit VG is as the DC-DC converter, it responds to control signal TV when the current/voltage VCC of for example 5V that receives circuit and earthing potential VSS, different voltage Vpw, Vpv, Vew, Ved, Vev and Vr are provided, these voltages respectively to program write, read with erase operation all be important.

Address buffer ADB obtains address signal Ai ， And from exterior terminal makes address latch ALH keep address signal.Signal TA is a control signal, be used for address signal is latched, and the TSC signal is inner serial clock signal.

Circuit ADG takes place inner serial clock signal TSC is responded in the address, finishes the address stepwise operation, and this clock signal TSC synchronously produces with the clock signal SC that is provided by the outside.Circuit ADG takes place and produces address signal Ayo in the address, to be used to encourage the detecting amplifier SA corresponding to the odd data line, produces address signal Aye, to be used to encourage detecting amplifier SA and the generation word line switching signal AC corresponding to the even data line.In other words, the address signal that is used for follow-up connected reference produces in inside according to clock signal SC, and according to this enforcement side, only the beginning of appointment is played the address is input to semiconductor storage, can obtain clock signal SC from exterior terminal.Above-mentioned signal Ayo and Aye, AC and/AC offers amplifier operation circuit SAC.This is a band thick stick signal for the symbol/expression of signal A C band, and its low level is the level of drive; This criterion also is applicable to other signals.

Y door YG responds to the address signal Ay in the Y string, produces signal so that select a data line ， And and selection to be used to amplify the signal of related detection amplifier when read operation, and sends amplifying signal to data output buffering OB.Y door YG also produces signal, is used for selecting a data line in the program write operation, and this Y door is carried a signal to data line, and this signal writes data corresponding to the program that is provided by data input buffer IB.

The order ， And that command decoder CDCR decipher is provided by data input buffer IB and as the back is explained transmits order data Di to operation circuit CONT.Signal TC is a command decoder control signal, is used to obtain order and control code translator.

Receiving chip enable signal/CE, output enabling signal/OE writes enabling signal/WE, and behind clock signal SC and the reset signal RS, operation circuit CONT produces the required different timing signal of internal wiring operation.Signal XM is main encoded control signal, and it is used for just switching/negative logic in programming check constantly; Signal TXG is an encoded control signal; Signal TV is the current circuit control signal; Signal TA is the address buffer control signal that is used for the control address latch operation; With signal TI is to be used to control the data input buffer control signal of obtaining data and order.

Signal TO is the data output buffer control signal that is used to control output data; Signal TC is the command decoder control signal that is used to obtain order and control code translator; Signal TS is the status register control signal that mode bit is set and resets that is used for state of a control register SREG; Signal TSA is used for control excitation timing detection amplifier control signal; Signal TSC is inner serial clock signal; And signal AC is the word line switching signal.

In addition, deliver to the address signal in the signal AXOX series of main code translator MAN-DCR by address latch ALH, be used to specify selected storage block; The signal Axi that delivers to a code translator GDCR by address latch ALH is the address signal in the X series, is used for specifying in a storage block word line; And the signal Ay that delivers to Y door YG is the address signal in the Y series.

Voltage Vpw is that program writes word line voltage constantly; Vpv is a check word line voltage constantly; Vew wipes word line voltage constantly; Ved wipes data line voltage constantly; And Vr is the data line pre-charge voltage.

Signal Oi is the output data of coming from data output buffering OB; Signal Do is a status data; And signal Di is an order data.In addition, signal RDY/BUSY is the signal that is used for the pio chip state.

Figure 28 is the principle sectional view of another storage unit of batch EEPROM.

Among Figure 28, P-Sub represents P type silicon chip; SSL representative n ⁺The secondary source line that the type diffusion layer forms; SR is the source region of storage unit; DR is the drain region of storage unit; And DSL is the secondary data line that forms with n type diffusion layer.Source region SR uses P ⁺And n ^-The type diffusion layer forms and drain region DR uses the n type diffusion layer as secondary data line DSL to form.Drain region DR says it is asymmetric with respect to the source region.In addition, FG represents the floating gate that forms by oxide film 12 on P type silicon chip; The control gate that the CG representative forms on floating gate by oxide film 13.Utilization is by being positioned at the tunnel(l)ing of the oxide film 12 between floating gate FG and source region DR, can finish to the operation that writes from the program of storage unit as shown in figure 28 with obliterated data.In erase operation, electric charge is injected into floating gate FG from drain region DR, and in the program write operation, so injects the electric charge of floating gate FG and discharge from drain region DR.With respect to Men Eryan, write with erase operation in the source and the drain voltage that are applied can be referring to the table 1 that will introduce.

In this example, gate voltage is added on the control gate CG; Source voltage is added on the SR of source region; And drain voltage is added on the DR of drain region.

Fig. 2 is the schematic circuit of former described storage base plate and peripheral hardware thereof.Storage unit is a MOSFET in the stacked door of Figure 28, otherwise be with similar stacked door shown in Figure 27 in a MOSFET.According to present embodiment, utilize tunnel current by thin oxide film, the program of can finishing writes and wipes two operations.

Numerous store M OSFET are combined into one in leakage and source with them when transforming public purpose into.The public leakage of store M OSFET is connected to data line DL by selecting MOSFET.The common source of store M OSFET obtains the earthing potential of circuit by " selecting MOSFET ".The control gate of store M OSFET is connected to word line WL." select MOSFET " is selected by the parallel selection wire that extends to word line WL.In other words, " select MOSFET " and can regard selected main word line as by main code translator MAN-DCR.

According to above-mentioned arrangement storage unit is divided into piece, the earthing potential of each piece circuit is delivered to secondary data line DSL and is carved source line SSL by " non-selection MOSFET ", and this can reduce the stress that puts on the nonselected memory cell.In other words, be made as non-selective at the selecteed data in storage unit line of word line, or be made as nonselective data in storage unit line at word line and be made as selectivity, so program write or erase operation in mustn't write or erasing voltage is added to and should keeps the storage unit of data to get on.Consequently stress only puts on the interior minority storage unit of piece.

According to present embodiment, adjacent data line DL is divided into the odd and even number line, and short MOSFET correspondingly is provided simultaneously.Short MOSFET is arranged to and alternately selects odd and even number data line ， And by non-selective data line DL being arranged at the fixed level of line-to-ground current potential, is used to reduce the noise that intercouples between the adjacent data line DL.In order to handle the data line of arrangement like this, Y door YG also is divided into the odd and even number group to be used for selection, and this does with respect to the detecting amplifier that reads signal that is used on the amplification data line DL.The back will know and see that Y door YG forms with migration MOSFET.

Further selected by secondary code translator SUB-DCR by a storage unit in the piece of main code translator MAN-DCR selection, the latter selects a word line in piece.A such a word line selection signal is formed by door code translator GDCR.In other words, after receiving selection/non-selection level, secondary code translator SUB-DCR forms word line selection/non-selection drive signal, and this selection/non-selection level is determined according to the operator scheme that is formed by main code translator MAN-DCR.

Table 1

Fetch program writes wipes

Vg Vcc-10V 12V selects Vd 1V 4V-4V

Vs 0V open circuit-4V

The non-selection of Vg 0V/ open circuit Vcc/0V 0V/0V Vd 1V/ open circuit 0V/ open circuit-4V/ open circuit

Vs 0V/ open circuit open circuit/open circuit-4V/ open circuit

Above table 1 shown gate voltage (word line WL) Vg, drain voltage Vd and the source voltage Vs of the store M OSFET of each pattern in reading, write (program) and erasing mode.Consider the relative voltage relation of door, drain voltage Vg, Vd and voltage Vs, the gate insulation film thin by one deck produces tunnel current, so that electric charge is injected floating gate or make floating gate discharge electric charge, thereby finishes and writes and erase operation by changing starting voltage.In the table 1, two voltage that use/separates or two class states are corresponding to the non-selection/non-selection piece constantly of selecting.

Fig. 3 is used to explain the wiring diagram that concerns according between data line of the present invention and the detecting amplifier.Among Fig. 3,4 data line DL0-DL3 and corresponding 4 detecting amplifier SA have been shown by example.Data line DL0-DL3 is divided into even data line DL0, DL2 and odd data line DL1, DL3.For even data line DL0, DL2 provide the MOSFET that is used to receive pre-charge voltage Vro, for providing, odd data line DL1, DL3 be used to receive pre-charge voltage Vr simultaneously ₁MOSFET.So, every even number and odd data line can carry out precharge for independent read operation.

Even data line DL0, DL2 are by being connected to detecting amplifier SA respectively by the migration MOSFET (TRMOS) that selects signal FO switching controls.Odd data line DL1, DL3 are by being connected to detecting amplifier SA respectively by the migration MOSFET (TRMOS) that selects signal F1 switching controls.The output signal of detecting amplifier SA is by being provided respectively by the Y door YG that selects signal Y0-Y3 switching controls.So, the data line of storage base plate or storage array is divided into two groups: the odd and even number group, they respond to selecting signal F0 and F1, can distinguish the read operation of deadline distributed store unit.Detecting amplifier SA and data line DL in same storage base plate MAT are the reasons are as follows of not encouraging simultaneously:

Because odd and even number detecting amplifier SA alternately encourages, alternately read in Xin And and amplify from storage unit.Shown in Fig. 3 bend, for example, word line WL switches to another by one in corresponding to the detecting amplifier SA of the odd data line DL1 of complete operation and DL3, from storage unit, take out simultaneously and read signal so that further operation, the signal that reads that has amplified is provided by the detecting amplifier corresponding to even data line DL0 and DL2 this moment.

When detecting amplifier was divided into two groups of And and arranges as mentioned above to finish amplifieroperation dispersedly in time, the peak point current that is accompanied by the amplifieroperation of detecting amplifier separated in time, had therefore in fact reduced half.

The number of the winning the confidence And that reads that comes from the storage unit of storage base plate one side does not appear on the adjacent data line simultaneously.In other words, in fact coupling noise can rely on shielding effect to be eliminated, and this shielding effect can be arranged at fixed level and obtain by the data line with non-excitation, as utilizing the short-and-medium MOSFET of Fig. 2 to obtain the example of earthing potential of circuit.The such a coupling noise that reduces might not consider the stray capacitance between the data line DL, so data line to the spacing of data line can be done narrowly as much as possible.The result is just to obtain the bigger integrated level of storage array.

Can unlike the line-to-ground current potential example that utilizes short MOSFET, be set to fixed level by non-excited data line, instead, it can be placed quick condition.Because the data line that is in quick condition DL is provided, the stray capacitance between the data line DL of adjacent excitation can reduce significantly in this example.In addition, the function class that is in the stray capacitance that exists between the earthing potential of the data line of quick condition and circuit is similar to and allows noise component to draw away to the earthing potential ， And of circuit can to ignore the noise that is produced actually between the odd number of adjacent excitation or even data line DL.

Fig. 4 is another wiring diagram that is used to explain according to concerning between data line of the present invention and the detecting amplifier.As shown in Figure 4, be respectively two adjacent groups DL0, DL1 and DL2, DL3 provides MOSFET, the latter is used to receive pre-charge voltage Vr ₀And Vr ₁So, per two adjacent data lines may be useful in the precharge operation of independent read operation.

So two data line DL0, DL1 of grouping are by being connected to relevant detecting amplifier SA by the migration MOSFET (TRMOS) that selects signal F0 institute switching controls, and Sheng Xia two data set DL2, DL3 are by being connected to relevant detecting amplifier SA by the migration MOSFET (TRMOS) that selects signal F1 institute switching controls simultaneously.The output signal of detecting amplifier SA is by being exported by the Y door YG that selects signal Y0-Y3 institute switching controls.

More than arrange basically similar in appearance to content shown in Figure 3, but unlike Fig. 3, data line is divided into the odd and even number line, on the contrary but adjacent two lines are combined.Even under this arrangement, might peak point current be reduced by half by the excitation detecting amplifier, also may reach the high-speed and continuous visit by switching word line.Have, owing to only produce the coupling of data line to data line between two groups of data lines, so the actual effect of noise is littler than the coupling noise that an adjacent left side and right data line are produced again.

Fig. 5 is another wiring diagram that is used to explain according to the relation between data line of the present invention and detecting amplifier.Data line is divided into four DL0-DL3 in the shown example of Fig. 5.Corresponding to the data line that is accompanied by corresponding precharge MOSFET, four kinds of pre-charge voltage Vr are also provided ₀-Vr ₃So, every data line DL0-DL3 might have the precharge operation of independent read operation.

Article four, data line DL0-DL3 is by being connected to detecting amplifier SA respectively by the migration MOSFET (TRMOS) that selects signal F0-F3 institute switching controls.The output signal of detecting amplifier SA is by also being exported by the Y door YG that selects signal Y0-Y3 institute switching controls.

In the present embodiment since data line by the quartern, the selection signal Y0-Y3 of Y door YG and select signal F0-F3 to form by same address decode signal.After the such quartern of data line DL, because detecting amplifier simultaneously also can the quartern, the peak point current that is accompanied by the excitation of detecting amplifier also can further reduce.Even, at this moment need not add short MOSFET and can in fact eliminate coupling noise when non-excited data line does not apply fixed level and when keeping quick condition, has three data lines to be in quick condition simultaneously between the data line of excitation.

By accident, when data line DL when dividing as shown in Figure 6, the precharge operation of data line DL0-DL3 then, the read operation of the storage unit that operation causes in the time of detecting amplifier SA and the stray capacitance between the data line DL0-DL3, these all can make the signal that reads that comes from storage unit produce fluctuation, thereby interact.Under worst case, when data line DL1 should remain on pre-charge level and the memory transistor that is connected to data line DL1 when being in off-state, adjacent data line DL0, DL1 change to low level, this moment data line DL1 current potential be coupled reduce.Say that with respect to reference potential coupling has reduced by a level amplitude,, when making the low level decision, can produce maloperation if worse off.

When detecting amplifier encourages simultaneously, the very big peak electricity inflow line road that fails to be convened for lack of a quorum.The power lead that this peak point current is also flowed through and formed in SIC (semiconductor integrated circuit), and because the distributed resistance and the inductance element of line, this peak point current produces noise in the supply voltage of circuit and earthing potential.In order not make memory transistor lose institute's deposit data, drain voltage remains on the low value of 1V in read operation.Relatively little owing to reading to the signal amplitude of data line from memory transistor, the influence of noise is that the opereating specification of detecting amplifier has been diminished in the power supply.

Did to attempt with the element microminiaturization, to increase memory capacity.Because it is very little to flow into the electric current of memory transistor, a collection of MOSFET and similar components are connected to a data line, thereby produce big stray capacitance.For this reason, the variation of reading the signal level of data line from selected memory transistor is slowly, in the time will finishing the high speed reads extract operation, read to increase to the signal level of data line enough big before, detecting amplifier SA needs excitation.Therefore, the dwindling of opereating specification of the detecting amplifier that is caused by noise be can not ignore.On the other hand, in order to guarantee the opereating specification of detecting amplifier, can use the data line that demarcates of storage base plate and the detecting amplifier that demarcates simultaneously according to present patent application, And encourages these detecting amplifiers in time dispersedly, to reach the purpose that reads at a high speed.By alternately encouraging data line and the detecting amplifier that demarcates, can realization of High Speed be accompanied by the connected reference that word line switches.

Fig. 7 is the basic waveform figure that is used to explain according to the read operation of the internal wiring of semiconductor storage of the present invention.When chip enable signal/CE when high level changes to low level, address buffer promptly is energized, address signal Ai promptly is read into simultaneously.Though do not show that the address signal that reads in leaves in the address latch circuit.

The address signal that reads in makes word line be selected ， And to start precharge operation.In other words, selected word line is made as from zero and selects level Vcc.And say that with respect to the pre-charge level of about 1V of data line DL the starting voltage Vthn of precharge MOSFET improves pre-charge voltage Vr.In other words, precharge MOSFET is made as pre-charge level Vr-Vthn as source follower circuit ， And with data line DL.

When data line DL was arranged on pre-charge level, pre-charge voltage Vr was arranged on low level, and the MOSFET of precharge simultaneously is turned off.When for the selection level of word line WL, when the starting voltage of store M OSFET had high value, the current potential of data line DL remained high level (pre-charge level), and institute's deposit data " 0 " is read out simultaneously.When for the selection level of word line WL, when the starting voltage of store M OSFET had low level, the current potential of data line DL was pulled to low level, and institute's deposit data " 1 " is read out simultaneously.

When the stray capacitance of data line DL is relatively very big, the electric current of store M OSFET that inflow is in " on " state is very little, be switched on through back migration MOSFET (TRMOS) after a while simultaneously, this section period is provided so that the acquisition detecting amplifier operates necessary signal amplitude.As migration MOSFET when being in " on " state, provide to detecting amplifier SA and to read signal, thereby realize amplifieroperation.When data line DL kept high level (pre-charge level), it was amplified to the level of power source voltage Vcc, and when it was in low level, it was amplified to the level of the earthing potential of circuit.

Though needn't limit, the amplification output of detecting amplifier SA can be kept in the latch cicuit of output unit.Y selects signal to be used to select a detecting amplifier, and the while output level is undertaken anti-phase by data output buffering, and promptly institute's deposit data " 1 " is exported as high level, and institute's deposit data " 0 " is exported as low level.

Fig. 8 is the oscillogram that is used to explain corresponding to the read operation example of Fig. 3 embodiment.Fig. 8 shows the example of the continuous read operation that is accompanied by the word line switching.

When selecting word line WL0 in the initial cycle, all data line DL0-DL3 encourage, and then all detecting amplifiers also all encourage.Till this step, the details of former operation waveform is similar with waveform shown in Figure 7.Pre-charge voltage Vr marks with the signal with dashed lines that is used to select to move MOSFET among Fig. 8.Produced then and selected signal Y0 And to export data Dout corresponding to data line DL0, the subsequent generation selects signal Y2 And to export data Dout corresponding to data line DL2.

Then, in the time of with output data Dout, word line is switched, the data of this output are corresponding to odd data DL1, and the latter is corresponding to selecting signal Y1.In other words, word line WL0 becomes non-selective, instead, has selected the word line WL1 corresponding to next address.According to the operation of selecting word line WL1, when read operation finishes, at even data line DL0 and enterprising line precharge operation of DL2 and detection amplifieroperation.Switching responds to word line, just is turned off at the odd data line DL1 of output data and the migration MOSFET of DL3.In other words, corresponding to regard to the data Dout of odd data line DL, the data that kept by detecting amplifier SA are output successively with regard to output.

After the data Dout output corresponding to data line DL1, then to selecting signal Y3 to respond, output is corresponding to the data Dout of data line DL3.Again produce then and select the data Dout of signal Y0 ， And output corresponding to the data line DL0 of word line WL1.This time, as the result who selects word line WL2 operation read amplified by detecting amplifier to the signal of data line DL1 and DL3.After this, as to selecting the response of signal Y2, Y1 and Y3, export data Dout continuously corresponding to data line DL2, DL1 and DL3.Corresponding to the end of output of the data Dout of even data line DL2 the time, switch word line again.

Fig. 9 is the sequential chart according to the continuous read operation of semiconductor storage of the present invention.Though needn't limit, can chip enable signal/CE and write enabling signal/WE both and be set to low level, so that from input data I i, obtain order.When the pattern of one group of initial sum end address of input was specified in this order, general/CE was made as low level separately or it is made as low level together, can obtains start address STA1 and end address FDA1 with/WE.

When signal/CE was made as low level, general/WE was reset to high level, so that obtain clock signal SC.Correspondingly, from data D0 corresponding to start address STA1, until data D7 corresponding to end address EDA1, these sequential serial data can with clock signal SC synchronously in acquisition.

Figure 10 is the sequential chart according to another continuous read operation of semiconductor storage of the present invention.As previously mentioned, chip enable signal/CE and write enabling signal/WE both and be set to low level can obtain order from input data I i similarly.When the pattern of two groups of initial sum end address of input was specified in this order, general/CE was made as low level separately or it is made as low level together, can obtains the first initial sum end address STA1, EDA1 and the second initial sum end address STA2, EDA2 with/WE.

When signal/CE was made as low level ,/WE was reset to high level, so that obtain clock signal SC.Correspondingly, output data Oi at first will be corresponding to the data D0 of the first start address STA1 until the data corresponding to the first end address EDA1, according to clock signal SC synchronously, output in proper order and serially, the data that will correspond respectively to the second start address STA2 are then exported similarly serially until the data corresponding to the second end address EDA2.It among Figure 10 oscillogram example corresponding to the data D0-D4 of the first start address STA1.

Figure 11 is the sequential chart according to another continuous read operation of semiconductor storage of the present invention.As previously mentioned, with chip enable signal/CE with write enabling signal/WE both and be made as low level, can obtain order from input data I i similarly.Under this order, can realize following three kinds of read operations.General/CE be made as separately low level or with it and/WE is made as low level together, can obtains start address START AD.

In first pattern, read the data serial of a word line.In other words, when signal/CE was made as low level ,/WE was reset to high level, so that obtain clock signal SC.Correspondingly, output data Oi will be corresponding to the data D0 of the start address START AD of selected word line until the data corresponding to the end address in the Y series, according to clock signal SC synchronously, output sequentially.

In second pattern, the data of same middle storage unit are series read-outs.In other words, when signal/CE was made as low level ,/WE was reset to high level, so that obtain clock signal SC.Correspondingly, output data Oi will be corresponding to the storage unit institute deposit data of end address in the Y series of data D0 the last item word line in corresponding to piece of start address START AD, according to clock signal SC synchronously, output sequentially.If start address START AD is corresponding to the last item word line, this example in fact equals first pattern.

As long as clock signal SC is provided always, the serial read operation of second pattern is just carried out always.In other words, when/when CE was made as low level ,/WE was reset to high level, so that clock signal SC is provided.Correspondingly, output data Oi can constantly read data, finishes when the clock signal SC that data D0 provided corresponding to start address START AD is stopped.Shown among Figure 11 in each pattern from the example of start address START AD until the order oscillogram of D0-D9.

Figure 12 is the process flow diagram that is used to explain corresponding to the internal wiring operation of the operator scheme of top Fig. 9.When making the decision of more options pattern by order, even number in the Y series and odd address Ye and Yo are resetted, so that whether decision follows 1 group mode.When making the decision of 1 group mode, the X address is made as a start address Xs, begins read operation simultaneously.

Owing to alternately produce output according to present embodiment odd and even number group, carry out following operation abreast in the odd address side: data are read to data line, and detecting amplifier amplifies, and latch operation; This moment, the data output function was transferred to even address; Similarly, carry out following operation concurrently in the even address side: data are read to data line, and detecting amplifier amplifies, and latch operation; This moment, the data output function was transferred to the odd address.

About the decision-making of sector end is that knack fixes on even number in the selected word line or whether whole read operations of odd data line finish entirely.In other words, the storage unit of a word line is divided into the odd and even number group, and their each groups are counted as a sector.Next level side at the Y of Fig. 3 door YG provides the 2nd grade of Y door, and And is by switching the 2nd grade of Y door, will store in the base plate other occasionally the odd data line all read in proper order.

Figure 13 and Figure 14 are the process flow diagrams that is used to explain corresponding to the operation of the internal wiring of the operator scheme of top Figure 10.When by order decision more options mould formula And and when determining 2 group modes among Figure 12 in the above, as shown in figure 13, the X address is made as one first start address Xs1, begins read operation simultaneously.

When the X address becomes greater than the first end address Xe ₁The time, following operation is arranged then: the second start address Xs is set ₂, the relevant corresponding data line of excitation, detecting amplifier amplifies, and latch operation.When the read operation of last odd number of sectors finished, as shown in figure 15, determine the following fact: the X address had been made as the second start address Xs ₂, data are exported by serial, until the second end address Xe ₂

Figure 15, Figure 16 and Figure 17 are the process flow diagrams that is used to explain corresponding to the operation of the internal wiring of the operator scheme of top Figure 11.Figure 15 shows the process flow diagram of the first half of first and second patterns.When the more options pattern was not followed in decision and (first pattern) read in the decision sector in Figure 15, the X address was made as start address Xs1 and begins read operation simultaneously.Whether finish read operation by the terminal decision in sector.In other words, make Y address become end address, can determine end.

When determining among Figure 15 that carrying out piece reads (second pattern), the X address is made as start address Xs ₁And begins read operation.When the odd address of a sector in the read operation ran through, data output promptly was transferred to even address, next carried out word line in the odd address side and switched, odd data line side encourages, detecting amplifier amplifies and carries out data latching, and these operate all parallel carrying out.

Among Figure 16, when the even number side has output function and sector end, unless have a Fang Wen And to piece end address Xe to follow in even address side reading of data, detecting amplifier amplifies and carries out data latching, otherwise data output is transferred to odd side as shown in figure 15.When visit was performed until end address Xe, the piece read operation promptly finished.

When decision does not use piece to read (second pattern) among Figure 17, just use three-mode automatically, starting address Xs is set simultaneously ₁, the beginning read operation.Read operation continues always, and SC stops until clock signal, and also promptly notice finishes serial read operation.

Figure 18 is a block diagram of implementing another semiconductor storage major part of the present invention.According to present embodiment, used differential detection amplifier SA.Though needn't limit, differential detection amplifier SA can comprise a pair of CMOS phase inverter circuit, and its input end and output terminal are cross-couplings and latching as dynamic ram (random access memory) is employed.Such detecting amplifier SA is encouraged by the power switch MOSFET that comprises P-and N-channel mosfet.

According to present embodiment, detecting amplifier SA is arranged between a pair of storer base plate of vertically laying.Detecting amplifier SA is along with even number and odd data line are divided into two groups.Though even number shown in Figure 180 is vertical laying with odd number detecting amplifier SA, in fact they can be laid point-blank.

The paired input end of even number detecting amplifier SA is connected to the even data line of upper and lower storage base plate, and the paired input end of odd number detecting amplifier SA then is connected to the odd data line of upper and lower storage base plate simultaneously.The secondary code translator SUB-DCR that is provided, main code translator MAN-DCR is similar with example among Fig. 1 with the door code translator.

Detecting amplifier operation circuit SAC produces even number detecting amplifier pumping signal/D0, D0 and odd number detecting amplifier pumping signal/D1, D1.Signal/D0 delivers to the P channel mosfet, and being used for provides supply voltage to even number detecting amplifier SA, and synchronous signal D0 delivers to N-channel MOS FET, is used for providing to even number detecting amplifier SA the earthing potential of circuit.In the same manner, signal/D1 delivers to the P channel mosfet, and being used for provides supply voltage to odd number detecting amplifier SA, and synchronous signal D-1 delivers to N-channel MOS FET, is used for providing the line-to-ground current potential to odd number detecting amplifier SA.Because address buffer, the I/O buffering, operation circuit, voltage generation circuit or the like be all with shown in Figure 1 similar, so no longer explain these elements among Figure 18.

Figure 19 is used to explain the wiring diagram that concerns according between data line of the present invention and the differential detection amplifier.Figure 19 shows that by example two centres are connected with 4 a pair of with relevant detecting amplifier SA of 4 data line DL0-DL3 of the storage base plate of detecting amplifier SA.

Its circuit is shown in that part of detecting amplifier of frame of broken lines and comprises a pair of CMOS phase inverter circuit, and its input end and output terminal are cross-linked.Because the circuit that latchs that is formed by CMOS phase inverter circuit is encouraged by switch MOS FET (so-called Dake MOS), thus the operation that it is finished in fact with one by the phase inverter circuit of clock control finish the same.The result is that a pair of CMOS phase inverter circuit is used by the form of the phase inverter circuit of clock control and represented.

Each input end at detecting amplifier has a MOSFET Q1 to be used for the input node is made as 0V, and input signal promptly is made as 0V before amplifieroperation begins.The a pair of input end of detecting amplifier SA is connected to data line D0-D3 by migration MOSFET (TRMOS).Migration MOSFET is divided into two groups, corresponds respectively to even data line DL0, DL2 and odd data line DL1, and DL3 ， And accepts to select signal F0, F1 respectively.Pre-charge voltage Vr0 correspondingly offers the door of precharge MOSFET, and this precharge MOSFET is for even data line DL0, and DL2 uses, simultaneously pre-charge voltage Vr ₁Correspondingly offer the door of precharge MOSFET, this precharge MOSFET is for odd data line DL1, and DL3 uses.

The a pair of input end of detecting amplifier SA has the switch MOS FET that forms a Y door YG, selects signal Y0-Y3 then to deliver to corresponding door simultaneously.This arrangement is similar to shown in Figure 3.The output terminal of Y door YG is connected to the I/O data line for public purpose ， And by the switch MOS FET that forms second level Y door, and the latter is led to data I/O buffering.

With regard to a pair of storage base plate, another does not encourage when excitation in them.Under the situation that the storage base plate does not encourage, although it is in nonexcited state, migration MOSFET still is in " on " state, and its corresponding data line is connected to the input end of detecting amplifier simultaneously.In non-excitation storage base plate side, pre-charge voltage Vr reduces, and the current potential of such data line is made as the high level of the data line that encourages the storage base plate and the intermediate value between low level simultaneously.The data line of the storage base plate of the non-excitation side of result is used for producing the reference voltage (Ref.DL) of detecting amplifier.

According to present embodiment, the arrangement according to the detecting amplifier SA that uses the cmos latch circuit writes data and is latched and maintains during the program write operation.In other words, even number and odd number migration MOSFET connects simultaneously, Y door YG open in proper order write data with setting after, the program write operation is all finished simultaneously.In response to the program write operation, the detecting amplifier operating voltage switches to 4V.On the other hand, the embodiment of image pattern 3 is the same, and except that the initial period, during the read operation with in programming check the time, even number and odd data line alternately encourage.

Figure 20 is used to explain another wiring diagram that concerns according between data line of the present invention and the differential detection amplifier.According to present embodiment, added an auto-programming write-in functions than content shown in Figure 19.

Figure 21 is the oscillogram that is used to explain Figure 20 center line dataway operation example.The oscillogram of Figure 21 (A) is explained and is write (program writes) and write check (program writes check) operation.Automatically write-in functions makes an explanation with reference to oscillogram.During the program write operation, write data T and deliver to detecting amplifier by the Y door.This moment, synchronous signal PW0 was used for MOSFET is connected because switch MOS (Deka MOS) remains on " on " state ， And and the program that maintains writes data, and detecting amplifier encourages.Write data as program and be in low level, then remain on " off " state, so the current potential of data line DL1 will remain on low level owing to be used for the MOSFET that auto-programming that the reception program writes data writes circuit.Yet if program writes data and is in high level shown in Figure 21 (A), MOSFET is switched on, and by the MOSFET raising of being charged, this MOSFET is connected by signal PW0 the current potential of data line DL1 by power source voltage Vcc simultaneously.

Then, signal TS0 is set to be higher than Vcc.Migration MOSFET correspondingly connects, so that the current potential of data line DL1 is raised to about the required 4v of write operation.Though do not demonstrate among Figure 21, the high pressure of guiding drain electrode into is added between floating gate and the drain electrode, and this moment, word line for example was made as-voltage of 10V, and from the tunnel current that floating gate flows to drain electrode write operation is accomplished.

Signal PW0 is made as low level when the program write operation finishes, and short MOSF ET shown in Figure 2 is switched on, and the current potential of data line DL1 is made as low level simultaneously, so that programming check is realized migration.In other words, signal PR0 is made as pre-charge voltage Vr and data line DL1 by precharge.As previously mentioned, because the signal PR1 of non-selection side is made as the current potential corresponding to reference voltage, therefore the current potential of the data line DL1 of non-selective storage base plate side is made as reference voltage Ref.D.L.

Deka MOSFET is turned off, so detecting amplifier is placed in nonexcited state.When the starting voltage that writes the store M OSFET of data when program before reduces, the current potential of data line DL1 reduces to low level (OK Data), be in low level but write in program as starting voltage under the situation of data deficiencies, then the current potential of data line DL1 rests on high level (NGData) always.Migration MOSFET relies on signal TS0, and TS1 is connected, and institute's read data is delivered to the input end of detecting amplifier together with reference voltage Ref.D.L simultaneously.Then Deka MOSFET Jie Tong And excitation.

If Suo Shu And is dissatisfied before the assay Ru, the program write operation repeats, and until obtaining above-mentioned low level signal, the number of times of repetition limits in advance.When the program write operation that repeats by the number of times that limits in advance all is unsatisfied with, promptly judges the storage unit defectiveness, and replaced with extension wire when needed.

Figure 21 (B) is the oscillogram that is used to explain read operation.When a last read operation finished, Deka MOSFET was turned off." MOSFET is set " current potential of data line DL is made as low level.The selection MOSFET of drain side that follows every storage unit is switched on.In addition, according to the selection/non-selection of storage base plate, pre-charge voltage PR0, PR1 are made as pre-charge voltage and reference voltage respectively with pair of data lines.Subsequent, the selection MOSFET of each side of the storage unit in the piece is switched on, if selected store M OSFET rests on " off " state, then selects the data line current potential of storage base plate side to equal pre-charge level; If selected store M OSFET rests on " on " state, then this current potential is pulled to low level by memory current.

Signal TS0, TS1 establish to high level, so that connect migration MOSFET, make pair of data lines be connected to the input end of detecting amplifier.Then, " MOSFET is set " is turned off, and Deka MOSFET connects, and with the excitation detecting amplifier, will read signal then and be amplified.

In the actual example of Figure 20, be used to receive the MOSFET of detecting amplifier input voltage as complete " a 1 " testing circuit; In other words, the MOSFET that provided of this MOSFET and another similar detecting amplifier input end by line do " or " be connected; And when all data lines that read were in low level entirely, all these MOSFET complete shut-downs were disconnected, so that obtain the high level detection signal.When the input end of any one other detecting amplifier during in high level, MOSFET turn-offs, so produce a low level detection signal, all is in " off " state because of all MOSFET simultaneously, therefore can detect " 1 " of all signals.Figure 20 points out that when the result who reads from storage unit was " 1 ", the data line on the detecting amplifier left side was in erase status.

When making arrangement, when producing the output of detecting amplifier by the circuit that is similar to left side circuit, the program on the right data line writes and wipes logic level and is reversed.In other words,, promptly be in low level output,, still constantly determine erase status in complete " 0 " from exterior terminal though the storage unit that provides for differential detection amplifier right data line is in erase status.

Figure 22 is used to explain another wiring diagram that concerns according between data line of the present invention and the differential detection amplifier.According to present embodiment, can ignore precharge MOSFET.In other words, program write signal PW0, PW1 can have the pre-charging functions that is used to read purpose, so that save precharge MOSFET.

Figure 23 is the oscillogram that is used to explain the line loop operation example.Figure 23 (A) description program writes with checked operation and Figure 23 (B) describes read operation.As shown in figure 23, even read in program, when check and read operation, also adopt signal PW ， And to change voltage level according to each operator scheme; In other words, signal PW, the PR of Figure 21 are by a signal PW performance function.

All provide precharge MOSFET corresponding to each bar data line.Have at semiconductor storage under the situation of high capacity to 32, the quantity of abridged precharge MOSFET is also correspondingly very big, because the quantity of data line can reach as 4096 or 8192.

Figure 24 is used to explain according to another of semiconductor storage of the present invention read the block diagram of circuit.According to present embodiment, the next stage of detecting amplifier has a main amplifier (Main Amp).The next stage of main amplifier has data latches, and institute's read data is exported by data latches and data output bufferings (Dout Buffer).

According to present embodiment,, three detecting amplifier SA are provided though needn't limit.Main amplifier responds to the inceptive impulse 1 of clock signal SC, will amplify from the DATA1 of first detecting amplifier.When clock signal SC was in low level 1L, data latches will be latched by the DATA1 that main amplifier amplifies.Main amplifier responds to second pulse 2 of clock signal, will amplify from the Data 2 of second detecting amplifier.When carrying out with these operations, data output buffering will be exported by the Data1 that data latches obtains.When clock signal SC was in low level 2L, data latches will be latched by the Data 2 that main amplifier amplified.

Main amplifier responds to the 3rd pulse 3 of clock signal SC, will amplify from the Data 3 of the 3rd detecting amplifier.When carrying out with these operations, data output buffering will be exported by the Data 2 that data latches obtains.When clock signal SC was in low level 3L, data output buffering managed to utilize the high level of next clock signal (not shown), will be exported by the Data 3 that data latches obtains.Therefore by being similar to the serial operation of streamline, output data at high speed.Also can manage in this example the output of main amplifier is directly delivered to data output buffering and the omitted data latch.

Figure 25 is another wiring diagram that is used to explain according to concerning between data line of the present invention and the detecting amplifier.According to present embodiment, a detecting amplifier is furnished with two data lines; Also promptly, 4 detecting amplifiers are furnished with 8 data lines, and the latter is equipped with in pairs.Select signal F00, F01, F11 can have " column selection " function.Rely on the various combination of signal F00-F11, data line DL0-DL7 can export their signal continuously, and needn't switch word line.Corresponding to migration MOSFET, there are 4 precharge MOSFET to be used for data line DL0-DL7.Pre-charge voltage Vr ₀-Vr ₃Offer precharge MOSFET respectively.

In continuous read operation, when signal F00, F10 were used to read 4 data lines, for example, then F01, F11 were used to read remaining 4 data lines.After stating F00, F10 and F01, F11 in the use and reading 8 data lines, word line is switched.Under arranging like this, the quantity of detecting amplifier can only be half of data line.

Figure 26 is to use the block diagram according to the such data handling system of the microcomputer of semiconductor storage of the present invention.Formed flash memory by the top semiconductor storage that proposes.

System according to present embodiment comprises CPU (central processing unit) (or computer processor) CPU, address decoder, timing controller, data buffering, data register, relay and flash memory above-mentioned.Though only shown a flash memory in the example, they can be installed by Duo Ge And connection, to obtain desirable memory capacity.Sometimes, RAM, ROM storer and the input-output apparatus that will seem important in such as the such system of above-mentioned microcomputer when explaining dispense, because of they have nothing to do with the present invention.

The SC pin of flash memory is as serial clock input contact.When being added to clock signal SC on the input contact, synchronous therewith, data are serial output.Though produce this serial clock signal SC by timing controller, also can directly import the system clock of CPU.

Read signal with reference to the serial that comes from flash memory, when/CE ,/OE rest on the low level and home address and SC synchronously and during increase, data are exported from the I/O pin.This moment, address bus promptly was released.When first flash memory is serial operation and when the second flash memory (not shown) obtains output, only signal/OE need being kept apart, compete mutually to stop on data and the data sum other data.

Characteristics of the present invention are as follows: (1) comprises that numerous data lines of the storage array of memory transistor are divided into numerous pieces, these memory transistors are arranged to matrix Xing Shi And according to institute's deposit data and have high or low starting voltage, simultaneously detecting amplifier is used in time amplifying signal dispersedly, and so the opereating specification of detecting amplifier can increase and peak point current can reduce.(2) the first and second detecting amplifier groups that correspond respectively to the adjacent data line of odd and even number are so arranged, so that when first group of detecting amplifier sent output signal, word line is switched, another group detecting amplifier complete operation simultaneously, the signal of reading in will the storage unit corresponding to the word line that is switched is amplified respectively.So,, can reduce the coupling noise of adjacent data demand pairs, And and also can finish the extract operation of sequential serial high speed reads effectively according to line by alternately finishing read operation to the odd and even number data line.Used address when (3) list is from odd and even number data line reading of data, used address when switching word line in addition, all by the address circuit taking place provides, the latter is synchronous with the clock signal that is provided by external connector, finish step-by-step operation, thus, mass data can read at a high speed.(4) data line selects MOSFET to be connected to the public drain electrode of store M OSFET in the stacked door by first, select MOSFET to be connected to public source with earthing potential by second, this makes at write/erase constantly, say that with respect to non-selection store M OSFET stress can be significantly, reduce effectively.(5) storage array comprises a pair of storage base plate, and the data line of each storage base plate is input to the differential detection amplifier simultaneously.When the data line current potential with non-selection storage base plate is used as reference voltage, select the data line current potential of storage base plate to be exaggerated, to obtain a detecting amplifier sensitivity, at a high speed.(6) MOSFET that detecting amplifier had is used to receive amplifying signal, be wired as simultaneously " or " logical relation, can export a signal effectively like this, be used to detect the erase status of whole piece data line.(7) by detecting amplifier is locked in circuit as CMOS, writing data Bei Shu Ru And maintains, and by finishing the write operation that is used for storage unit simultaneously, might reach write-in operation at high speed, said memory cells on the basis of the data that kept corresponding to data line.

The invention that the present inventor did was narrated particularly, need not illustrate, this Fa Ming And is not limited to the foregoing description, its correct that can in all sorts of ways in the case without departing from the scope of the present invention.For example, the differential detection amplifier can be used as amplifier MOSFET as in the example of static RAM (SRAM).Except that forming above-mentioned flicker EEPROM, this store M OSFET can be used to form EPROM and shielding ROM.

The present invention can be widely used in the semiconductor storage with high or low starting voltage, and wherein starting voltage is decided by received data.This semiconductor storage can be packed into such as in the such digital integrated circuit of one chip microcomputer.

Be the concise and to the point conclusion of characteristics of the present invention below.The data line that comprises the storage array of memory transistor is divided into numerous pieces, these memory transistors are arranged to matrix Xing Shi And according to institute's deposit data and have high or low threshold value, the detecting amplifier that is used to finish amplifieroperation simultaneously is used in time amplifying signal dispersedly, first and second groups of detecting amplifier groups that correspond respectively to the adjacent data line of odd and even number are so arranged, so that when first group of detecting amplifier sent output signal, word line is switched to another group from one group, another group detecting amplifier complete operation simultaneously, the signal of reading in will the storage unit corresponding to the word line that is switched is amplified respectively.So,, can reduce the coupling noise of adjacent data demand pairs, And and also can finish the extract operation of sequential serial high speed reads effectively according to line by alternately finishing read operation to the odd and even number data line.

Claims (37)

1. semiconductor storage comprises:

Many word lines;

Many data lines;

A plurality of storage unit; Wherein

Each storage unit has first semiconductor region and second semiconductor region, floating gate and control gate, and wherein control gate is connected with one of word line, and first semiconductor region is connected with one of data line simultaneously,

It is characterized in that described semiconductor storage comprises:

Detecting amplifier, be used for provide through data line and amplify and output data of being amplified in the data that each storage unit that links to each other with selected word line is stored; And

Select commutation circuit, be used for order and receive the selection signal, the data that this selection signal is used for being stored in selected storage unit offer detecting amplifier in proper order;

Also comprise data selection circuit, be used for, select the output signal of each detecting amplifier in response to address signal;

Wherein select commutation circuit the data order to be offered detecting amplifier according to the selection signal that is received, and the data on the detecting amplifier order amplification data line and output data of being amplified wherein, and

Wherein detecting amplifier is as being provided with many data line relevant detection amplifiers.

2. semiconductor storage comprises:

Many word lines;

Many data lines;

A plurality of storage unit; Wherein

Each storage unit has first semiconductor region and second semiconductor region, floating gate and control gate, and wherein control gate is connected with one of word line, and first semiconductor region is connected with one of data line simultaneously,

It is characterized in that described semiconductor storage comprises:

First group of detecting amplifier, they are corresponding to the odd data line in many data lines, and are used to amplify the data on the odd data line; And

Second group of detecting amplifier, they are corresponding to the even data line in many data lines, and are used to amplify the data on the even data line; Wherein

When one group of detecting amplifier during in output signal serially, simultaneously word line is switched, another group detecting amplifier then will from the corresponding storage unit of the word line that switches like this data of coming amplified.

3. according to the semiconductor storage of claim 2, wherein be made as when non-selective when data line, be used to provide the switch MOS FET of earthing potential to be connected to every data line, these data are divided into the odd and even number group.

4. according to the semiconductor storage of claim 2, wherein be made as when non-selective when data line, be divided into that each bar all is in quick condition in the data line of odd and even number group.

5. according to the semiconductor storage of claim 2, wherein generation circuit in address provides the address that is used to select the odd data line, the address that is used to select the address of even data line and is used to switch word line, circuit and a clock signal synchronous operation that provides from external connector take place in this address, the completing steps operation.

6. semiconductor storage comprises:

A data terminal;

Many word lines;

Many data lines;

A plurality of storage unit, wherein each storage unit has first semiconductor region and second semiconductor region, floating gate and control gate, and wherein said control gate is connected with one of described many word lines, and in wherein said first semiconductor region each is connected with one of described many data lines

It is characterized in that described semiconductor storage comprises:

Detecting amplifier, each detecting amplifier are provided to corresponding with described many data lines respectively;

Select commutation circuit, it is connected to described detecting amplifier according to the selection signal that order provides with described many data lines; And

Data selection circuit, it is connected to described data terminal according to the address signal that order provides with described detecting amplifier;

Wherein said selection commutation circuit according to described selection signal, provides data from each storage unit that is connected with at least one selected word line to described detecting amplifier in proper order,

The described data that wherein said detecting amplifier storage provides in proper order through described selection commutation circuit, and

Wherein said data selection circuit according to described address signal, is connected to described data terminal with described detecting amplifier, exports the described data that are stored in the described detecting amplifier with order.

7. according to the semiconductor storage of claim 6, wherein also comprise a control circuit, it offers described selection commutation circuit with described selection signal.

8. according to the semiconductor storage of claim 6, wherein also comprise an address generator circuit, it synchronously produces described address signal in proper order with the clock signal that provides from described semiconductor storage outside.

9. semiconductor storage comprises:

Many word lines;

Many data lines;

A plurality of storage unit, in wherein said a plurality of storage unit each has first semiconductor region and second semiconductor region, floating gate and control gate, and wherein control gate is connected with one of described many word lines, and wherein first semiconductor region is connected with one of described many data lines

It is characterized in that described semiconductor storage comprises:

Odd data line in first group of detecting amplifier, they and described many data lines is corresponding,

Even data line in second group of detecting amplifier, they and described many data lines is corresponding,

First selects commutation circuit, and it selects signal according to first, and described first group of detecting amplifier is connected to described odd data line; And

Second selects commutation circuit, and it selects signal according to second, and described second group of detecting amplifier is connected to described even data line;

Data selection circuit, it is connected to described data terminal according to the address signal that order provides with described detecting amplifier,

Wherein according to described first select signal, by described first group of detecting amplifier being connected to after described odd data line, described first group of detecting amplifier store data on the described odd data line, according to described second select signal, by described second group of detecting amplifier is connected to described even data line, described second group of detecting amplifier stored the data on the described even data line

Wherein according to address signal, by described detecting amplifier is connected to described data terminal, described first group and described second group of detecting amplifier are exported the data that are stored in wherein in proper order.

10. according to the semiconductor storage of claim 9, wherein also comprise short MOSFET, be provided to described many data lines in described odd data line corresponding with described even data line.

11. according to the semiconductor storage of claim 10, wherein when described odd data line was nonselection mode, described odd data line was set to earth potential by being provided with the corresponding described short MOSFET of described odd data line.

12. according to the semiconductor storage of claim 11, wherein when described even data line was nonselection mode, described even data line was set to earth potential by being provided with the corresponding described short MOSFET of described even data line.

13. semiconductor storage comprises:

A data terminal;

A plurality of data lines;

Many main data line;

Many auxilliary data lines;

Many source lines;

A plurality of storage unit,

Wherein each storage unit has first and second semiconductor regions, floating gate and control gate,

Wherein said control gate is connected with one of described many word lines,

Wherein in described first semiconductor region of each described storage unit of same column and described many auxilliary data lines links to each other, and selects MOSFET to link to each other with a main data line through one respectively at the described auxilliary data line of same column, and

Wherein in described second semiconductor region of each described storage unit of same column and described many source lines links to each other,

It is characterized in that described semiconductor storage comprises:

Odd data line in first group of detecting amplifier, they and described many main data line is corresponding,

Even data line in second group of detecting amplifier, they and described many main data line is corresponding,

First selects commutation circuit, and it selects signal according to first, and described first group of detecting amplifier is connected to described odd data line; And

Second selects commutation circuit, and it selects signal according to second, and described second group of detecting amplifier is connected to described even data line;

Data selection circuit, it is connected to described data terminal according to the address signal that order provides with described detecting amplifier,

Wherein according to described first select signal, by described first group of detecting amplifier being connected to after described odd number main data line, described first group of detecting amplifier receive data on the described odd number main data line, according to described second select signal, by described second group of detecting amplifier is connected to described even number main data line, described second group of detecting amplifier receives the data on the described even number main data line

Wherein according to address signal, by described detecting amplifier is connected to described data terminal, described first group and described second group of detecting amplifier are exported the data that are stored in wherein in proper order.

14. according to the semiconductor storage of claim 13, wherein also comprise short MOSFET, be provided to described many data lines in described odd data line corresponding with described even data line.

15. according to the semiconductor storage of claim 14, wherein when described odd data line was nonselection mode, described odd data line was by being set to earth potential with the corresponding described short MOSFET of described odd data line.

16. according to the semiconductor storage of claim 15, wherein when described even data line was nonselection mode, described even data line was by being set to earth potential with the corresponding described short MOSFET of described even data line.

17. semiconductor storage comprises:

Many word lines;

Many data lines;

A plurality of storage unit,

Wherein each storage unit has first semiconductor region and second semiconductor region, floating gate and control gate, and in wherein said control gate and described many word lines one is connected, and one in each described first semiconductor region and described many data lines is connected,

It is characterized in that described semiconductor storage comprises:

A clock signal terminal is provided with external timing signal to it;

Address generator, it and described external timing signal are synchronously exported the word line switching signal; And

Data terminal, output with storage unit that selected word line links to each other in the data of being stored,

Wherein during providing described external timing signal to described clock signal terminal, according to described word line switching signal, select a word line in described many word lines, from the output of described data terminal with described storage unit that selected word line links to each other the data of being stored.

18. according to the semiconductor storage of claim 17,

Wherein when from predetermined command of described data terminal input, during providing described external timing signal, export each data of described storage unit, being stored from described data terminal to described clock signal terminal.

19. the semiconductor storage according to claim 18 wherein also comprises:

An address latch, it latchs a starting address signal.

20. according to the semiconductor storage of claim 19,

Wherein said address generator and described external timing signal synchronously, the starting address signal that latchs from described address latch begins, the executive address step-by-step operation.

21. semiconductor storage comprises:

A data terminal;

Many word lines;

Many main data line;

Many auxilliary data lines;

Many source lines;

A plurality of storage unit; Wherein each storage unit has first and second semiconductor regions, floating gate and control gate,

One in described control gate and described many word lines links to each other,

Wherein in described first semiconductor region of each described storage unit of same column and described many auxilliary data lines links to each other, and selects MOSFET to link to each other with a main data line through one respectively at the described auxilliary data line of same column, and

Wherein in described second semiconductor region of each described storage unit of same column and described many source lines links to each other,

It is characterized in that described semiconductor storage comprises:

A clock signal terminal is provided with external timing signal to it;

Address generator, it and described external timing signal are synchronously exported the word line switching signal; And

Data terminal, output with storage unit that selected word line links to each other in the data of being stored,

Wherein during providing described external timing signal to described clock signal terminal, according to described word line switching signal, select a word line in described many word lines, from the output of described data terminal with described storage unit that selected word line links to each other the data of being stored.

22. according to the semiconductor storage of claim 21,

Wherein when from predetermined command of described data terminal input, during providing described external timing signal, export each data of described storage unit, being stored from described data terminal to described clock signal terminal.

23. the semiconductor storage according to claim 22 wherein also comprises:

An address latch, it latchs a starting address signal.

24. according to the semiconductor storage of claim 23,

Wherein said address generator and described external timing signal synchronously, the starting address signal that latchs from described address latch begins, the executive address step-by-step operation.

25. semiconductor storage comprises:

Many word lines;

Many data lines;

A data terminal;

A plurality of storage unit, in wherein said a plurality of storage unit each has first semiconductor region and second semiconductor region, floating gate and control gate, wherein control gate is connected with one of described many word lines, and wherein first semiconductor region is connected with one of described many data lines

It is characterized in that described semiconductor storage comprises:

A plurality of detecting amplifiers, each detecting amplifier is connected with a pair of of described many data lines;

Select commutation circuit for one, it selects signal according to one, and the predetermined first right data line of described data line is connected to described a plurality of detecting amplifier; And

A data selection circuit, it is connected to described data terminal according to the address signal that order provides with described detecting amplifier,

Wherein according to described selection signal, by described a plurality of detecting amplifiers being connected to the described first predetermined data line, described a plurality of detecting amplifier amplifies after the data on the right first described predetermined data line of described many data lines, according to described address signal, export the data of amplifying in proper order by described data terminal detecting amplifier being connected to described data terminal by described a plurality of detecting amplifiers, wherein after described a plurality of detecting amplifiers are exported the data of described amplification in proper order, according to described selection signal, by connecting described a plurality of detecting amplifier, described a plurality of detecting amplifier amplifies the data on the right second predetermined data line of described many data lines, afterwards, according to described address signal, by described a plurality of detecting amplifiers being connected to described data terminal, the data that order output is amplified by described a plurality of detecting amplifiers.

26., wherein also comprise the short MOSFET that is connected in described many data lines according to the semiconductor storage of claim 25.

27. semiconductor storage according to claim 26, wherein when right described first data line of described data line was nonselection mode, the first right data line of described data line was set to earth potential by the described short MOSFET that is connected in right described first data line of described data line.

28. according to the semiconductor storage of claim 26, wherein when second data line was nonselection mode, the second right data line of described data line was set to earth potential by the described short MOSFET that is connected in the second right data line of described data line.

29. according to the semiconductor storage of claim 25, each of wherein said a plurality of detecting amplifiers has the latch function of data latching on data line.

30. according to the semiconductor storage of claim 25, wherein said many data lines are many odd data lines and many even data lines, described many data lines described to being all described odd data line and all described even data line.

31., wherein also comprise the pre-charge circuit that is connected in described many data lines according to the semiconductor storage of claim 30.

32. according to the semiconductor storage of claim 31, wherein said pre-charge circuit is to the precharge of one of described odd number and described even data line.

33., wherein also comprise the controller of controlling described pre-charge circuit according to the semiconductor storage of claim 32.

34. according to the semiconductor storage of claim 33, wherein said controller control described pre-charge circuit in case in the different separately time a pair of described many data lines of preliminary filling.

35. according to the semiconductor storage of claim 27, wherein said many data lines are many odd lines and many even data lines, described many data lines described to being all described odd data line and all described even data line.

36. according to the semiconductor storage of claim 28, wherein said many data lines are many odd data lines and many even data lines, described many data lines described to being all described odd data line and all described even data line.

37. according to the semiconductor storage of claim 29, wherein said many data lines are many odd data lines and many even data lines, described many data lines described to being all described odd data line and all described even data line.

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