CN104320122B - Digital output buffer and control method thereof - Google Patents
Digital output buffer and control method thereof Download PDFInfo
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- CN104320122B CN104320122B CN201410314231.XA CN201410314231A CN104320122B CN 104320122 B CN104320122 B CN 104320122B CN 201410314231 A CN201410314231 A CN 201410314231A CN 104320122 B CN104320122 B CN 104320122B
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention discloses a digital output buffer and a control method thereof. The digital output buffer comprises a time sequence generator, an integrator, a residual current detector, an energy accumulator, an inductor L, a load capacitor CL, a first switching tube SW1, a second switching tube SW2 and a third switching tube SW3, wherein the energy accumulator, the inductor L, the load capacitor CL, the first switching tube SW1, the second switching tube SW2 and the third switching tube SW3 construct a main circuit of the digital output buffer; and the integrator and the residual current detector construct a negative feedback circuit of the digital output buffer. Through adoption of the digital output buffer and the control method thereof, the power consumption of the digital output buffer can be effectively lowered.
Description
Technical field
The present invention relates to output buffer technical field, more particularly to a kind of digital output buffer and its control method.
Background technology
With the rising of digital signal frequency, digital output buffer carries out needing to consume a large amount of during output buffering to data
Power.Therefore, it is necessary to design a kind of digital output buffer for reducing power consumption.
China Patent Publication No. CN103269217, publication date August in 2013 28 days, the entitled output buffer of invention,
This application case discloses a kind of output buffer, and it includes first and second transistor and autobias circuit, first crystal pipe
There are coordination electrode, the input electrode of coupling outfan and output electrode, transistor seconds has coordination electrode, coupling first crystal
The output electrode of the input electrode and coupling reference voltage of the output electrode of pipe, autobias circuit coupling outfan and first crystal
The coordination electrode of pipe.Its weak point is that the power consumption of the output buffer is larger.
The content of the invention
The purpose of the present invention is the technical problem for overcoming existing digital output buffer power consumption larger, there is provided one kind can
Reduce the digital output buffer and its control method of power consumption.
In order to solve the above problems, the present invention is employed the following technical solutions and is achieved：
A kind of digital output buffer of the present invention, including clock generator, integrator, aftercurrent detector, energy storage
Device, inductance L, load capacitance CL, first switch pipe SW1, second switch pipe SW2 and the 3rd switching tube SW3, described accumulator one end
Ground connection, the accumulator other end electrically connected with first conduction terminal of the 3rd switching tube SW3, and the of the 3rd switching tube SW3
Two conduction terminals are electrically connected with inductance L one end, the top crown of the inductance L other ends and load capacitance CL, first switch pipe SW1
The first conduction terminal electrical connection of the first conduction terminal and second switch pipe SW2, the bottom crown and second switch pipe SW2 of the electric capacity CL
The second conduction terminal be all grounded, second conduction terminal of the first switch pipe SW1 is electrically connected with power vd D, the first switch
The control end of the control end, the control end of second switch pipe SW2 and the 3rd switching tube SW3 of pipe SW1 is electric with clock generator respectively
Connection, two test sides of the aftercurrent detector are turned on first conduction terminal and second of the 3rd switching tube SW3 respectively
End electrical connection, the outfan of aftercurrent detector are electrically connected with the input of integrator, the outfan of the integrator
Electrically connect with the second input of clock generator, the first input end of the clock generator is the letter of digital output buffer
Number input.
In the technical program, accumulator, inductance L, load capacitance CL, first switch pipe SW1, second switch pipe SW2 and
3rd switching tube SW3 constitutes the main circuit of digital output buffer, its function be by control first switch pipe SW1, second
Switching tube SW2, the 3rd switching tube SW3 come control LC vibration the electric charge on accumulator is nondestructively moved to according to input signal Din
In load capacitance CL, or the electric charge on CL is nondestructively moved on accumulator according to input signal Din, so in delivery outlet
Dout can realize the conversion from low level to high level and from high level to low level conversion.Accumulator can be with electricity consumption perhaps
Person's voltage source is realized.First switch pipe SW1 and second switch pipe SW2 realizes the reinforcement of the level to digital output Dout,
Dout is maintained in the low level of high level and low-resistance of low-resistance.
In input signal Din from low transition to high level, then by high level jump to it is low level during, numeral
Output buffer work is divided into T1, T2, T3 and T4 four-stage, clock generator control first switch pipe SW1, second switch pipe
SW2 and the 3rd switching tube SW3 work.
It is when input signal Din is from low transition to high level, interval into T1, the 3rd switching tube SW3 conductings, first
Switching tube SW1 and second switch pipe SW2 disconnects, and the electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3,
As inductance L constitutes series resonant circuit with load capacitance CL, load capacitance CL is filled with voltage due to resonance, its top crown
Voltage can be with free oscillation to VDD.Interval in T1, the electric current in inductance L starts to the forward to increase from 0, to after peaking, negative
The voltage oscillation of electric capacity CL top crowns is carried to peak, electric current is returned to 0 in inductance L.
Subsequently enter that T2 is interval, the electric current in inductance L returns at 0 point, be the interval end points of T1, while be that T2 is interval opening
Initial point.First switch pipe SW1 is turned on, and second switch pipe SW2 and the 3rd switching tube SW3 disconnects, and power vd D passes through first switch pipe
SW1 is enhanced to the top crown of load capacitance CL, and the voltage of the top crown of load capacitance CL reaches VDD, and delivery outlet Dout outputs are high
Level.
It is when input signal Din jumps to low level from high level, interval into T3, the 3rd switching tube SW3 conductings, first
Switching tube SW1 and second switch pipe SW2 disconnects., via inductance L, the 3rd switching tube SW3 is by energy storage for electric charge in load capacitance CL
Device is reclaimed.This process, from VDD free oscillations to 0, the electric current in inductance L starts reversely to increase the voltage in load capacitance CL from 0
Maximum point is arrived greatly, 0 is then returned to.
Subsequently enter that T4 is interval, the electric current in inductance L returns at 0 point, be the interval end points of T3, while be that T4 is interval opening
Initial point.Second switch pipe SW2 is turned on, and first switch pipe SW1 and the 3rd switching tube SW3 disconnects.Load capacitance CL top crown via
Second switch pipe SW2 is enhanced to GND, delivery outlet Dout output low levels.
Integrator and aftercurrent detector constitute the negative-feedback circuit of digital output buffer.Due to T1 stages and T3
Stage needs the electric current in inductance L to terminate at 0 point just, so as to reduce power consumption, it is to avoid aftercurrent high frequency vibrating in inductance L
Dissipate one's fortune raw circuit noise.Therefore the persistent period in clock generator control T1 stages and T3 stages is critically important.
The T1 stages are identical with the persistent period in T3 stages, are all time T.Clock generator is by recently received integrator
Numerical value of the corresponding time value of Dsgm values of output as time T.Integrator output Dsgm values are comprised the following steps：Integrator is pre-
One initial value is set to Dsgm first, initial value one T time value of correspondence, when clock generator controls the 3rd switching tube SW3
At the end of conducting T time, aftercurrent detector detects the aftercurrent in inductance L, output Dcmp values to integrator, Dcmp
Value reaction aftercurrent direction, or Dcmp values reaction aftercurrent direction and size, integrator to Dsgm initial values with
The Dcmp values for receiving are integrated, and obtain newest Dsgm values, and by the Dsgm values output to clock generator.Sequential is produced
Device determines corresponding time value according to the Dsgm values for receiving, and using the time value as time T value.
Preferably, a kind of digital output buffer also includes detector for error, data processor and frequency divider, institute
The outfan for stating integrator is also electrically connected with the input of detector for error, the outfan of the detector for error and data processing
The input electrical connection of device, the outfan of the data processor are electrically connected with the second input of frequency divider, the frequency divider
First input end electrically connect with the first input end of clock generator, the outfan of the frequency divider and detector for error when
The clock signal input terminal electrical connection of clock signal input part, the clock signal input terminal of integrator and aftercurrent detector.
Detector for error, data processor and frequency divider constitute another negative-feedback circuit of digital output buffer.
The Dsgm values of detector for error reception integrator output, and calculate error value E rr of the Dsgm values for receiving, detector for error
Error value E rr is input to into data processor, data processor calculates the frequency dividing multiple of frequency divider according to error value E rr
Fsel, and frequency dividing multiple Fsel is sent to frequency divider, frequency divider are carried out to input signal Din point according to frequency dividing multiple Fsel
Frequently, the clock signal clk of respective frequencies is exported to detector for error, integrator and aftercurrent detector.Aftercurrent is detected
Device and integrator are all clock signal clk triggerings.If clock signal clk highest frequency work always, then whole circuit
Power consumption is larger, if clock signal clk low-limit frequency work always, then whole circuit anti-interference ability is weak, and corresponding speed is slow.
The negative-feedback circuit of detector for error, data processor and frequency divider composition makes digital output buffer save power consumption to be had again
Stronger capacity of resisting disturbance.
Preferably, the accumulator is electric capacity or voltage source.
A kind of digital output buffer control method of the present invention, comprises the following steps：
S1：Clock generator read input signal Din, when input signal Din by low transition to high level when, then hold
Row step S2, when input signal Din by high level saltus step to low level when, then execution step S4；
S2：Clock generator controls the 3rd switching tube SW3 conducting T times, control first switch pipe SW1 and second switch pipe
SW2 disconnects T time；
S3：At the end of T time, clock generator control first switch pipe SW1 conducting, control second switch pipe SW2 and the
Three switching tube SW3 disconnect；
S4：Clock generator controls the 3rd switching tube SW3 conducting T times, control first switch pipe SW1 and second switch pipe
SW2 disconnects T time；
S5：At the end of T time, time schedule controller control second switch pipe SW2 conducting, control first switch pipe SW1 and the
Three switching tube SW3 disconnect；
Number of the corresponding time value of Dsgm values that recently received integrator is exported by clock generator as time T
Value, integrator output Dsgm values are comprised the following steps：Integrator arranges an initial value to Dsgm in advance, the initial value correspondence one
The initial value of individual time value, the i.e. time value for time T, when clock generator controls the 3rd switching tube SW3 conducting T time knots
When beam, i.e. the 3rd switching tube SW3 disconnect, aftercurrent detector detects the aftercurrent in inductance L, and output Dcmp values are to product
Device, Dcmp values is divided to react the direction of aftercurrent, or direction and the size of Dcmp values reaction aftercurrent, integrator is to Dsgm
Initial value and all Dcmp values for receiving are integrated, and obtain newest Dsgm values, and the Dsgm values are exported.
Preferably, detector for error receives the Dsgm values of integrator output, and calculate the mistake of the Dsgm values for receiving
Error value E rr is input to data processor by difference Err, detector for error, and data processor is calculated point according to error value E rr
The frequency dividing multiple Fsel of frequency device, and frequency dividing multiple Fsel is sent to into frequency divider, frequency divider is according to frequency dividing multiple Fsel to input
Signal Din is divided, and exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.
Preferably, the method that the detector for error calculates error value E rr is comprised the following steps：Detector for error will
The N number of Dsgm values being most recently received are averaged, and obtain meansigma methodss Dref, and then according to formula Err=c* (Dsgm-Dref), c is
Constant, calculates error value E rr.
Preferably, the method that the data processor calculates frequency dividing multiple Fsel is comprised the following steps：Data processing
According to formula F sel=Fsel0+a* | Err |, Fsel0 is positive constant to device, and a is positive coefficient, calculates frequency dividing multiple Fsel
Value.Fsel Serial regulation frequency divider output frequencies.Linear algorithm, less error E rr correspond to less frequency divider output
Frequency, correspond to less circuit power consumption, but its adjustment speed is slower；Bigger error E rr correspond to bigger frequency divider
Output frequency, correspond to bigger circuit power consumption, but its adjustment speed is faster.Its advantage is that control is simple.
Preferably, the method that the data processor calculates frequency dividing multiple Fsel is comprised the following steps：Data processing
According to formula F sel=Fsel0+b*e^ | Err |, Fsel0 is positive constant to device, and b is positive coefficient, calculates frequency dividing multiple
The value of Fsel.The advantage of exponentiation algorithm is that, in error | Err | when interior in a big way, whole circuit is operated in very low frequency and saves work(
Consumption, it is quiet；After error is larger, quickly increase Fsel, circuit work frequency rapid increase, the adjustment speed of circuit quickly increase
Plus, while the power of circuit consumption quickly increases.
Preferably, the method that the data processor calculates frequency dividing multiple Fsel is comprised the following steps：Data processing
Device adopts sigma-delta algorithms, according to single order Z domains expression formula：Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) are amount
Change noise, calculate the value of frequency dividing multiple Fsel.The output of Fsel (Z) can at least be output as two states, so can be with letter
Change the design of frequency divider.Advantage of the algorithm using sigma-delta can be the design of simplified frequency divider, have the disadvantage to introduce quantization
Noise, but of sigma-delta algorithms itself can shift front end onto noise, and so by substrate coupling, power supply is coupled
The noise near signal frequency point in system can be ignored.
The present invention substantial effect be：Effectively reduce the power consumption of digital output buffer, it is ensured that numeral output is delayed
Rushing utensil has stronger capacity of resisting disturbance, while avoiding the aftercurrent higher-order of oscillation in inductance L from producing circuit noise.
Description of the drawings
Fig. 1 is a kind of circuit theory connection block diagram of the present invention；
Fig. 2 is the structural representation of detector for error；
Fig. 3 is a kind of workflow diagram of the present invention；
Fig. 4 is the control signal sequential chart of a working cycle of the present invention.
In figure：1st, clock generator, 2, integrator, 3, aftercurrent detector, 4, accumulator, 5, detector for error, 6,
Data processor, 7, frequency divider, 8, error op device, 9, dynamic reference maker.
Specific embodiment
Below by embodiment, and accompanying drawing is combined, technical scheme is described in further detail.
Embodiment：The present invention a kind of digital output buffer, as shown in figure 1, including clock generator 1, integrator 2,
Aftercurrent detector 3, accumulator 4, detector for error 5, data processor 6, frequency divider 7, inductance L, load capacitance CL, first
Switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3,4 one end of accumulator ground connection, 4 other end of accumulator are opened with the 3rd
The first conduction terminal electrical connection of pipe SW3 is closed, second conduction terminal of the 3rd switching tube SW3 is electrically connected with inductance L one end, and inductance L is another
First conduction terminal of the top crown, first conduction terminal of first switch pipe SW1 and second switch pipe SW2 of one end and load capacitance CL
Electrical connection, the second conduction terminal of the bottom crown and second switch pipe SW2 of electric capacity CL are all grounded, and the second of first switch pipe SW1 leads
Go side is electrically connected with power vd D, the control end of first switch pipe SW1, the control end of second switch pipe SW2 and the 3rd switching tube
The control end of SW3 is electrically connected with clock generator 1 respectively, and two test sides of aftercurrent detector 3 are switched with the 3rd respectively
First conduction terminal of pipe SW3 and the electrical connection of the second conduction terminal, the outfan of aftercurrent detector 3 and the input of integrator 2
Electrical connection, the outfan of integrator 2 are electrically connected with the input of the second input of clock generator 1 and detector for error 5, when
Signal input part of the first input end of sequence generator 1 for digital output buffer, at the outfan and data of detector for error 5
The input electrical connection of reason device 6, the outfan of data processor 6 are electrically connected with the second input of frequency divider 7, frequency divider 7
First input end is electrically connected with the first input end of clock generator 1, the outfan of frequency divider 7 and the clock of detector for error 5
The clock signal input terminal electrical connection of signal input part, the clock signal input terminal of integrator 2 and aftercurrent detector 3.
Accumulator, inductance L, load capacitance CL, first switch pipe SW1, second switch pipe SW2 and the 3rd switching tube SW3 groups
Into the main circuit of digital output buffer, its function is opened by control first switch pipe SW1, second switch pipe SW2, the 3rd
Close pipe SW3 come control LC vibration the electric charge on accumulator is nondestructively moved in load capacitance CL according to input signal Din, or
It is that the electric charge on CL is nondestructively moved on accumulator according to input signal Din, so can realizes from low in delivery outlet Dout
Level is to the conversion of high level and from high level to low level conversion.Accumulator is electric capacity.First switch pipe SW1 and second is opened
The reinforcement that pipe SW2 realizes the level to digital output Dout is closed, Dout is maintained the low electricity of the high level and low-resistance of low-resistance
On flat.
As shown in figure 4, in input signal Din from low transition to high level, then jumped to by high level low level
During, digital output buffer work is divided into T1, T2, T3 and T4 four-stage, clock generator control first switch pipe
SW1, second switch pipe SW2 and the 3rd switching tube SW3 work.
It is when input signal Din is from low transition to high level, interval into T1, the 3rd switching tube SW3 conductings, first
Switching tube SW1 and second switch pipe SW2 disconnects, and the electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3,
As inductance L constitutes series resonant circuit with load capacitance CL, load capacitance CL is filled with voltage due to resonance, its top crown
Voltage can be with free oscillation to VDD.Interval in T1, the electric current in inductance L starts to the forward to increase from 0, to after peaking, negative
The voltage oscillation of electric capacity CL top crowns is carried to peak, electric current is returned to 0 in inductance L.
Subsequently enter that T2 is interval, the electric current in inductance L returns at 0 point, be the interval end points of T1, while be that T2 is interval opening
Initial point.First switch pipe SW1 is turned on, and second switch pipe SW2 and the 3rd switching tube SW3 disconnects, and power vd D passes through first switch pipe
SW1 is enhanced to the top crown of load capacitance CL, and the voltage of the top crown of load capacitance CL reaches VDD, and delivery outlet Dout outputs are high
Level.
It is when input signal Din jumps to low level from high level, interval into T3, the 3rd switching tube SW3 conductings, first
Switching tube SW1 and second switch pipe SW2 disconnects.Electric charge in load capacitance CL is via inductance L, the 3rd switching tube SW3 by energy storage
Device is reclaimed.This process, from VDD free oscillations to 0, the electric current in inductance L starts reversely to increase the voltage in load capacitance CL from 0
Maximum point is arrived greatly, 0 is then returned to.
Subsequently enter that T4 is interval, the electric current in inductance L returns at 0 point, be the interval end points of T3, while be that T4 is interval opening
Initial point.Second switch pipe SW2 is turned on, and first switch pipe SW1 and the 3rd switching tube SW3 disconnects.Load capacitance CL top crown via
Second switch pipe SW2 is enhanced to GND, delivery outlet Dout output low levels.
Integrator and aftercurrent detector constitute the negative-feedback circuit of digital output buffer.Due to T1 stages and T3
Stage needs the electric current in inductance L to terminate at 0 point just, so as to reduce power consumption, it is to avoid aftercurrent high frequency vibrating in inductance L
Dissipate one's fortune raw circuit noise.Therefore the persistent period in clock generator control T1 stages and T3 stages is critically important.
The T1 stages are identical with the persistent period in T3 stages, are all time T.Clock generator is by recently received integrator
Numerical value of the corresponding time value of Dsgm values of output as time T.Integrator output Dsgm values are comprised the following steps：Integrator is pre-
One initial value is set to Dsgm first, initial value one T time value of correspondence, when clock generator controls the 3rd switching tube SW3
At the end of conducting T time, aftercurrent detector detects the aftercurrent in inductance L, output Dcmp values to integrator, Dcmp
Value reaction aftercurrent direction, or Dcmp values reaction aftercurrent direction and size, integrator to Dsgm initial values with
The Dcmp values for receiving are integrated, and obtain newest Dsgm values, and by the Dsgm values output to clock generator.Sequential is produced
Device determines corresponding time value according to the Dsgm values for receiving, and using the time value as time T value.
Detector for error, data processor and frequency divider constitute another negative-feedback circuit of digital output buffer.
The Dsgm values of detector for error reception integrator output, and calculate error value E rr of the Dsgm values for receiving, detector for error
Error value E rr is input to into data processor, data processor calculates the frequency dividing multiple of frequency divider according to error value E rr
Fsel, and frequency dividing multiple Fsel is sent to frequency divider, frequency divider are carried out to input signal Din point according to frequency dividing multiple Fsel
Frequently, the clock signal clk of respective frequencies is exported to detector for error, integrator and aftercurrent detector.Aftercurrent is detected
Device and integrator are all clock signal clk triggerings.If clock signal clk highest frequency work always, then whole circuit
Power consumption is larger, if clock signal clk low-limit frequency work always, then whole circuit anti-interference ability is weak, and corresponding speed is slow.
The negative-feedback circuit of detector for error, data processor and frequency divider composition makes digital output buffer save power consumption to be had again
Stronger capacity of resisting disturbance.
As shown in Fig. 2 detector for error 5 includes error op device 8 and dynamic reference maker 9, dynamic reference maker 9
Input electrically connect with the outfan of integrator 2, the outfan of dynamic reference maker 9 is defeated with the first of error op device 8
Enter end electrical connection, the second input of error op device 8 is electrically connected with the outfan of integrator 2, the outfan of error op device 8
Electrically connect with the input of data processor 6, the clock signal input terminal and dynamic reference maker 9 of error op device 8 when
Clock signal input part is electrically connected with the outfan of frequency divider 7.Characteristic of the dynamic reference maker 9 according to input Dsgm values, extracts
Go out reference signal information Dref, the temporal information of current over-zero on this reference signal Dref reflection inductance L, which is compared with Dsgm values
Produce output error value Err.
A kind of a kind of digital output buffer control method of the present invention, it is adaptable to above-mentioned digital output buffer, bag
Include following steps：
S1：Clock generator read input signal Din, when input signal Din by low transition to high level when, then hold
Row step S2, when input signal Din by high level saltus step to low level when, then execution step S4；
S2：Clock generator controls the 3rd switching tube SW3 conducting T times, control first switch pipe SW1 and second switch pipe
SW2 disconnects T time；
The electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3, due to inductance L and load capacitance CL
Composition series resonant circuit, load capacitance CL are filled with voltage due to resonance, and the voltage of its top crown can be arrived with free oscillation
VDD.This process, the electric current in inductance L start to the forward to increase from 0, to after peaking, in the electricity of load capacitance CL top crown
Pressure oscillates to peak, and in inductance L, electric current is returned to 0.
S3：At the end of T time, clock generator control first switch pipe SW1 conducting, control second switch pipe SW2 and the
Three switching tube SW3 disconnect；
Power vd D is enhanced to the top crown of load capacitance CL by first switch pipe SW1, the top crown of load capacitance CL
Voltage reaches VDD, delivery outlet Dout output high level.
S4：Clock generator controls the 3rd switching tube SW3 conducting T times, control first switch pipe SW1 and second switch pipe
SW2 disconnects T time；
Electric charge in load capacitance CL is reclaimed by accumulator via inductance L, the 3rd switching tube SW3.This process, load electricity
Hold the voltage on CL from VDD free oscillations to 0, the electric current in inductance L starts to inversely increase maximum point from 0, is then returned to
0。
S5：At the end of T time, time schedule controller control second switch pipe SW2 conducting, control first switch pipe SW1 and the
Three switching tube SW3 disconnect；
Load capacitance CL top crown is enhanced to GND, delivery outlet Dout output low levels via second switch pipe SW2.
Number of the corresponding time value of Dsgm values that recently received integrator is exported by clock generator as time T
Value, integrator output Dsgm values are comprised the following steps：Integrator arranges an initial value to Dsgm in advance, the initial value correspondence one
The initial value of individual time value, the i.e. time value for time T, when clock generator controls the 3rd switching tube SW3 conducting T time knots
When beam, i.e. the 3rd switching tube SW3 disconnect, aftercurrent detector detects the aftercurrent in inductance L, and output Dcmp values are to product
Device, Dcmp values is divided to react the direction of aftercurrent, or direction and the size of Dcmp values reaction aftercurrent, integrator is to Dsgm
Initial value and all Dcmp values for receiving are integrated, and obtain newest Dsgm values, and the Dsgm values are exported.
The Dsgm values of detector for error reception integrator output, and error value E rr of the Dsgm values for receiving is calculated, by mistake
Error value E rr is input to data processor by gap detector, and data processor calculates the frequency dividing of frequency divider according to error value E rr
Multiple Fsel, and frequency dividing multiple Fsel is sent to into frequency divider, frequency divider is carried out to input signal Din according to frequency dividing multiple Fsel
Frequency dividing, exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.
The workflow of digital output buffer, as shown in Figure 3.
Detector for error calculates the method for error value E rr and comprises the following steps：Detector for error is by the N being most recently received
Individual Dsgm values are averaged, and obtain meansigma methodss Dref, and then according to formula Err=c* (Dsgm-Dref), c is constant, calculates mistake
Difference Err.
Data processor calculates the method for frequency dividing multiple Fsel and comprises the following steps：Data processor is according to formula F sel
=Fsel0+a* | Err |, Fsel0 are positive constants, and a is positive coefficient, calculate the value of frequency dividing multiple Fsel.Fsel is linearly adjusted
Whole frequency divider output frequency.Linear algorithm, less error E rr correspond to less frequency divider output frequency, correspond to less
Circuit power consumption, but its adjustment speed it is slower；Bigger error E rr correspond to bigger frequency divider output frequency, correspond to
Bigger circuit power consumption, but its adjustment speed is faster.Its advantage is that control is simple.
Data processor is calculated the method for frequency dividing multiple Fsel and also can be realized by following steps：Data processor according to
Formula F sel=Fsel0+b*e^ | Err |, Fsel0 are positive constants, and b is positive coefficient, calculate the value of frequency dividing multiple Fsel.
The advantage of exponentiation algorithm is that, in error | Err | when interior in a big way, whole circuit is operated in very low frequency and saves power consumption, quiet；
After error is larger, quickly increase Fsel, circuit work frequency rapid increase, the adjustment speed of circuit quickly increase, while electric
The power that road consumes quickly increases.
Data processor is calculated the method for frequency dividing multiple Fsel and can also be realized by following steps：Data processor is adopted
Sigma-delta algorithms, according to single order Z domains expression formula：Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) make an uproar for quantization
Sound, calculates the value of frequency dividing multiple Fsel.The output of Fsel (Z) can at least be output as two states, can so simplify point
The design of frequency device.Advantage of the algorithm using sigma-delta can be the design of simplified frequency divider, have the disadvantage that introducing quantization makes an uproar
Sound, but of sigma-delta algorithms itself can shift front end onto noise, and so by substrate coupling, power supply is coupled to
The noise near signal frequency point in system can be ignored.
Claims (9)
1. a kind of digital output buffer, it is characterised in that：Including clock generator (1), integrator (2), aftercurrent detection
Device (3), accumulator (4), inductance L, load capacitance CL, first switch pipe SW1, second switch pipe SW2 and the 3rd switching tube SW3,
Accumulator (4) one end ground connection, accumulator (4) other end are electrically connected with first conduction terminal of the 3rd switching tube SW3, institute
The second conduction terminal for stating the 3rd switching tube SW3 is electrically connected with inductance L one end, and the inductance L other ends are upper with load capacitance CL
The first conduction terminal electrical connection of pole plate, first conduction terminal of first switch pipe SW1 and second switch pipe SW2, the electric capacity CL's
Second conduction terminal of bottom crown and second switch pipe SW2 is all grounded, second conduction terminal and power supply of the first switch pipe SW1
VDD is electrically connected, the control of the control end, the control end of second switch pipe SW2 and the 3rd switching tube SW3 of the first switch pipe SW1
End processed is electrically connected with clock generator (1) respectively, and two test sides of the aftercurrent detector (3) are switched with the 3rd respectively
First conduction terminal of pipe SW3 and the electrical connection of the second conduction terminal, outfan and the integrator (2) of the aftercurrent detector (3)
Input electrical connection, the outfan of the integrator (2) is electrically connected with the second input of clock generator (1), when described
Signal input part of the first input end of sequence generator (1) for digital output buffer.
2. a kind of digital output buffer according to claim 1, it is characterised in that：Also include detector for error (5), number
According to processor (6) and frequency divider (7), the outfan of the integrator (2) is also electrically connected with the input of detector for error (5),
The outfan of the detector for error (5) is electrically connected with the input of data processor (6), the data processor (6) it is defeated
Go out end to electrically connect with the second input of frequency divider (7), first input end and the clock generator (1) of the frequency divider (7)
First input end electrical connection, the outfan of the frequency divider (7) and the clock signal input terminal of detector for error (5), integrator
(2) the clock signal input terminal electrical connection of clock signal input terminal and aftercurrent detector (3).
3. a kind of digital output buffer according to claim 1 and 2, it is characterised in that：The accumulator (4) is electric capacity
Or voltage source.
4. a kind of digital output buffer control method, it is characterised in that comprise the following steps：
S1：Clock generator read input signal Din, when input signal Din by low transition to high level when, then perform step
Rapid S2, when input signal Din by high level saltus step to low level when, then execution step S4；
S2：Clock generator controls the 3rd switching tube SW3 conducting T times, controls first switch pipe SW1 and second switch pipe SW2
Disconnect T time；
S3：At the end of T time, clock generator control first switch pipe SW1 conductings, control second switch pipe SW2 and the 3rd are opened
Close pipe SW3 to disconnect；
S4：Clock generator controls the 3rd switching tube SW3 conducting T times, controls first switch pipe SW1 and second switch pipe SW2
Disconnect T time；
S5：At the end of T time, time schedule controller control second switch pipe SW2 conductings, control first switch pipe SW1 and the 3rd are opened
Close pipe SW3 to disconnect；
Numerical value of the corresponding time value of Dsgm values that recently received integrator is exported by clock generator as time T, product
Device output Dsgm values are divided to comprise the following steps：Integrator arranges an initial value to Dsgm in advance, when the initial value is corresponding one
Between be worth, i.e., the time value for time T initial value, when clock generator control the 3rd switching tube SW3 conducting T time terminate,
That is, when the 3rd switching tube SW3 disconnects, aftercurrent detector detects the aftercurrent in inductance L, and output Dcmp values are to integration
Device, Dcmp values react the direction of aftercurrent, or direction and the size of Dcmp values reaction aftercurrent, and integrator is at the beginning of Dsgm
Initial value and all Dcmp values for receiving are integrated, and obtain newest Dsgm values, and the Dsgm values are exported.
5. a kind of digital output buffer control method according to claim 4, it is characterised in that also including following step
Suddenly：The Dsgm values of detector for error reception integrator output, and error value E rr of the Dsgm values for receiving is calculated, error is visited
Survey device and error value E rr is input to into data processor, data processor calculates the frequency dividing multiple of frequency divider according to error value E rr
Fsel, and frequency dividing multiple Fsel is sent to frequency divider, frequency divider are carried out to input signal Din point according to frequency dividing multiple Fsel
Frequently, the clock signal clk of respective frequencies is exported to detector for error, integrator and aftercurrent detector.
6. a kind of digital output buffer control method according to claim 5, it is characterised in that the detector for error
The method for calculating error value E rr is comprised the following steps：The N number of Dsgm values being most recently received are averaged by detector for error, are obtained
To meansigma methodss Dref, then according to formula Err=c* (Dsgm-Dref), c is constant, calculates error value E rr.
7. a kind of digital output buffer control method according to claim 5 or 6, it is characterised in that at the data
Reason device calculates the method for frequency dividing multiple Fsel and comprises the following steps：Data processor is according to formula F sel=Fsel0+a* | Err
|, Fsel0 is positive constant, and a is positive coefficient, calculates the value of frequency dividing multiple Fsel.
8. a kind of digital output buffer control method according to claim 5 or 6, it is characterised in that at the data
Reason device calculates the method for frequency dividing multiple Fsel and comprises the following steps：Data processor is according to formula F sel=Fsel0+b*e^ |
Err |, Fsel0 is positive constant, and b is positive coefficient, calculates the value of frequency dividing multiple Fsel.
9. a kind of digital output buffer control method according to claim 5 or 6, it is characterised in that at the data
Reason device calculates the method for frequency dividing multiple Fsel and comprises the following steps：Data processor adopts sigma-delta algorithms, according to one
Rank Z domains expression formula：Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) are quantizing noise, and Err (Z) is error value E rr in Z
Expression formula in domain, calculates the value of frequency dividing multiple Fsel.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410314231.XA CN104320122B (en) | 2014-07-03 | 2014-07-03 | Digital output buffer and control method thereof |
| PCT/CN2015/083257 WO2016000654A1 (en) | 2014-07-03 | 2015-07-03 | Digital output buffer and control method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410314231.XA CN104320122B (en) | 2014-07-03 | 2014-07-03 | Digital output buffer and control method thereof |
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| CN104320122B true CN104320122B (en) | 2017-04-26 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101047378A (en) * | 2006-03-29 | 2007-10-03 | 川崎微电子股份有限公司 | Output buffer circuit and system including the output buffer circuit |
| CN101453207A (en) * | 2007-12-06 | 2009-06-10 | 奇景光电股份有限公司 | Operational amplifier |
| CN102811050A (en) * | 2012-08-01 | 2012-12-05 | 华为技术有限公司 | Buffer and digital step attenuator |
| CN103269217A (en) * | 2013-01-21 | 2013-08-28 | 威盛电子股份有限公司 | Output buffer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3792207B2 (en) * | 2003-03-25 | 2006-07-05 | 沖電気工業株式会社 | Current-driven differential driver and data transmission method using current-driven differential driver |
| CN104320122B (en) * | 2014-07-03 | 2017-04-26 | 杭州硅星科技有限公司 | Digital output buffer and control method thereof |
-
2014
- 2014-07-03 CN CN201410314231.XA patent/CN104320122B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101047378A (en) * | 2006-03-29 | 2007-10-03 | 川崎微电子股份有限公司 | Output buffer circuit and system including the output buffer circuit |
| CN101453207A (en) * | 2007-12-06 | 2009-06-10 | 奇景光电股份有限公司 | Operational amplifier |
| CN102811050A (en) * | 2012-08-01 | 2012-12-05 | 华为技术有限公司 | Buffer and digital step attenuator |
| CN103269217A (en) * | 2013-01-21 | 2013-08-28 | 威盛电子股份有限公司 | Output buffer |
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| CN104320122A (en) | 2015-01-28 |
| WO2016000654A1 (en) | 2016-01-07 |
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