CN104320001B - A kind of magnetic isolation feedback circuit - Google Patents

Abstract

The present invention provides a kind of magnetic isolation feedback circuit, including secondary chip, compensates circuit, Magnetic isolation coupling transformer and main limit chip.By voltage magnitude signal is modulated to pulse width information, after being transmitted by Magnetic isolation coupling transformer, then this pulse width information is reduced to voltage magnitude signal.This circuit can feedback error signal exactly, it is achieved the main limit of controller controls, and capacity of resisting disturbance is strong, simplifies the design of Magnetic isolation coupling transformer.

Description

A kind of magnetic isolation feedback circuit

Technical field

The present invention relates to a kind of magnetic isolation feedback circuit, realize closed loop control particularly in a kind of field of switch power The magnetic isolation feedback circuit of system.

Background technology

Off-line SMPS utilizes transformator to realize electrical isolation, and the signal of its outfan is also required to the most anti- It is fed to former limit and constitutes the negative feedback control ring of system.Classical mode be by TL431 and optocoupler formed across Lead amplifier and output voltage is fed back to the former limit of changer.But, TL431 and optocoupler are required for bigger quiet State operating current, and the optocoupler range of linearity is narrower.Especially optocoupler under the severe applied environment such as high temperature, high irradiation Performance more unreliable, be easily damaged.Another isolation feedback system is Magnetic isolation, i.e. by a coupling Close transformator and output signal is fed back to former limit.The advantage of Magnetic isolation feedback is to have stronger anti-interference, Flouride-resistani acid phesphatase Ability, can keep higher precision and stability under the adverse circumstances such as high temperature, high pressure.

In prior art, the more commonly used Magnetic isolation feedback system is to use the UC1901 chip of TI, this core It, to internal error amplifier, is entered after producing error signal by sheet sampling electric power output voltage by clock signal Row chopper amplification.The pulse formed is sent to main limit by halfwave rectifier, filter circuit also by coupling transformer again Former error signal.This feedback system is disadvantageous in that and error signal is used amplitude modulation, and amplitude is at any time Becoming, adding the design difficulty of transformator.And the power consumption of transformator is relatively big, easily when chopping frequency is relatively low Saturated, when error magnitude is relatively low, capacity of resisting disturbance weakens.Patent US6301135 it is also proposed a kind of Magnetic isolation Feedback circuit, is directly sent to the PWM modulation signal of secondary error signal and triangle wave main limit and controls Master switch.Due to the link not having error signal to reduce, this circuit can only realize secondary univoltage ring and control, and makes Difficulty can be caused to loop compensation when being used in the topologys such as flyback.

Additionally, the magnetic isolation feedback circuit that also discrete device is built, such as patent CN102185485 and patent CN103326579.The circuit that this two patents proposes remains and error signal is carried out amplitude modulation, with The modulation demodulation system of UC1901 is similar, and the circuit reliability that discrete device is built is poor, occupies relatively Big PCB surface is amassed.

Summary of the invention

It is an object of the invention to: provide a kind of magnetic isolation feedback circuit, this circuit can be believed by feedback error exactly Number, it is achieved the main limit of controller controls, and capacity of resisting disturbance is strong, simplifies the design of Magnetic isolation coupling transformer.

It is an object of the invention to be achieved through the following technical solutions: a kind of magnetic isolation feedback circuit, including secondary Chip, compensation circuit, Magnetic isolation coupling transformer and main limit chip.Secondary chip is by FB port sampling electricity The information of source output terminal, and it is translated into error signal, exported by COMP port and compensate circuit One end, the other end compensating circuit is connected to FB port；Meanwhile, by error signals modulate be pulse signal via TRP port and TRN port export Magnetic isolation coupling transformer, are connected to by Magnetic isolation coupling transformer The SP port of main limit chip and SN port；The pulse signal comprising error signal information is reduced by main limit chip For error signal, it is achieved closed loop control.It is characterized in that:

Described secondary chip includes error amplifier, error signals modulate unit and pulse modulation unit；Described Error amplifier forward termination chip internal produce reference voltage V_ref, described error amplifier negative sense End receives sampled value K*V of electric power output voltage_out, described error amplifier output error signal is believed to error Number modulating unit；Described error signals modulate unit by error signals modulate be after square-wave signal output to described Pulse modulation unit；Square-wave frequency modulation is that burst pulse exports Magnetic isolation coupling change by described pulse modulation unit Depressor；

Described main limit chip includes main limit square wave reduction unit, main edge error signal demodulation unit, second compares Device, the first rest-set flip-flop and the second agitator；The input of described main limit square wave reduction unit passes through SN Port and SP port connect the outfan of described Magnetic isolation coupling transformer, described main limit square wave reduction unit Outfan outputs signals to described main edge error signal demodulation unit；The positive input of described second comparator connects Receiving the output signal of autonomous edge error signal demodulation unit, the negative input of described second comparator passes through CS port connects ground connection after inductive current sampling resistor, and the output of described second comparator terminates a described RS The reset terminal R of trigger；The clock that the set end S of described first rest-set flip-flop connects described second agitator is defeated Going out and hold CLK, the outfan Q of described first rest-set flip-flop connects power switch pipe by GATE port.

Preferably, described error signals modulate unit includes the first agitator, the first comparator, first and door And sawtooth waveforms generation unit；The forward end of described first comparator connects the outfan of described error amplifier, The negative end of the first described comparator is connected to described sawtooth waveforms generation unit；The first described comparator is defeated Go out described in termination first with an input of door, described first is with another input termination of door described the The clock signal clk that one agitator produces；Described first with door output termination described in pulse modulation unit； The inversion clock outfan CLK_ of the first described agitator connects described sawtooth waveforms generation unit.

Preferably, described sawtooth waveforms generation unit includes that the first switching tube, the first current source, sawtooth waveforms produce Electric capacity and second switch pipe；The grid of the first described switching tube and the grid of described second switch pipe connect described The inversion clock outfan CLK_ of the first agitator；The source electrode of described first switching tube meets power supply VCC, institute The drain electrode stating the first switching tube connects the positive pole of described first current source；The drain electrode of described second switch pipe connects described saw Tooth ripple produces one end and the negative pole of described first current source, the source electrode of described second switch pipe and the sawtooth waveforms of electric capacity Produce the other end ground connection together of electric capacity.

Preferably, described pulse modulation unit include the 4th phase inverter, the 5th switching tube, the 6th switching tube, 3rd current source, the second electric capacity, the first Schmidt trigger, the 5th phase inverter, the second nor gate, the 4th electricity Stream source, the 7th switching tube, the 8th switching tube, the 3rd electric capacity, the second Schmidt trigger, hex inverter and 3rd nor gate；The input of described 4th phase inverter terminates the outfan of described error signals modulate unit, and It is connected respectively to the grid of described 7th switching tube, the grid of described 8th switching tube and described 3rd nor gate One input；The outfan of described 4th phase inverter connect respectively the grid of described 5th switching tube, the described 6th The grid of switching tube and an input of described second nor gate；The source electrode of described 5th switching tube connects described The negative pole of three current sources, the drain electrode of described 5th switching tube drain electrode and described 6th switching tube connects described second respectively One end of electric capacity and the input of described first Schmidt trigger；The source ground of described 6th switching tube；Institute The output stating the first Schmidt trigger terminates the input of described 5th phase inverter, described 5th phase inverter defeated Go out another input terminating described second nor gate；The output of described second nor gate terminates described Magnetic isolation The positive input of coupling transformer；The source electrode of described 7th switching tube meets the negative pole of described 4th current source, institute The drain electrode of the drain electrode and described 8th switching tube of stating the 7th switching tube meets one end and the institute of described 3rd electric capacity respectively State the input of the second Schmidt trigger, the source ground of described 8th switching tube；Described second Schmidt touches The output sending out device terminates the input of described hex inverter, the output termination the described 3rd of described hex inverter Another input of nor gate；The output of described 3rd nor gate terminates the negative of described Magnetic isolation coupling transformer To input.

Preferably, described main edge error signal demodulation unit include the first phase inverter, delay circuit Delay, Second phase inverter, the 3rd switching tube, the second current source, sawtooth waveforms reduction electric capacity, the 4th switching tube, first or Not gate, the first transmission gate, the 3rd phase inverter, sampling capacitance；The input of described first phase inverter, described in prolong Time the input of circuit Delay and an input of described first nor gate connect described main limit side respectively The outfan of ripple reduction unit；The output of described first phase inverter terminates the grid of described 3rd switching tube, described The source electrode of the 3rd switching tube and drain electrode connect power supply VCC and the positive pole of described second current source respectively；Described sawtooth The two ends of ripple reduction electric capacity connect negative pole and the ground of described second current source respectively；The drain electrode of described 4th switching tube and Source electrode connects negative pole and the ground of described second current source respectively；The output termination described the of described delay circuit Delay The input of two phase inverters, the output of described second phase inverter terminates the grid and described the of described 4th switching tube Another input of one nor gate；The output of described first nor gate terminates a control of described first transmission gate End processed and the input of described 3rd phase inverter, the output of described 3rd phase inverter terminates described first transmission gate Another controls end, and the input of described first transmission gate terminates the negative pole of described second current source, described first transmission The output of door terminates one end and the positive input of described second comparator of described sampling capacitance.

Preferably, described main limit square wave reduction unit includes that the second rest-set flip-flop, described 2nd RS trigger The S end of device and R end receive described Magnetic isolation coupling transformation by main limit chip SP port and SN port respectively Two outfans of device, the square wave after the Q end output reduction of described second rest-set flip-flop.

Preferably, described compensation circuit includes the first electric capacity and the first resistance, described the first electric capacity and first Resistant series.

Below, in conjunction with anti exciting converter, above-mentioned magnetic isolation feedback circuit is described.Anti exciting converter as it is shown in figure 1, Including main power stage circuit and magnetic isolation feedback circuit.

The basic functional principle of the present invention is as follows: the output voltage V of power supply_outAfter sampling network is sampled, Produce and V_outProportional sampled voltage K*V_out, wherein K=R₁₃/(R₁₂+R₁₃), R₁₂、R₁₃For in Fig. 1 Sampling resistor.Sampled voltage is input to the backward end of error amplifier by the FB port of secondary chip, with It is connected on the reference voltage V of forward end_refError signal V is produced after relatively_eaIt is connected to the first comparator COM₂₁ Positive input.First agitator OSC₂₁Produce clock signal clk and inversion signal CLK_ thereof, its In, CLK_ is connected to the first switching tube PM in sawtooth waveforms generation unit 22₂₁Grid and second switch pipe NM₂₂ Grid.Due to PM₂₁For PMOS, NM₂₂For NMOS tube, so two switching tube alternate conduction, Electric capacity C is produced at sawtooth waveforms₂₁Upper generation and synperiodic sawtooth signal V of clock signal_saw, V_sawIt is connected to One comparator COM₂₁Negative input, the first comparator COM₂₁Outfan be given and sawtooth waveforms with week The square-wave signal P of phase₂₁。P₂₁Dutycycle by error signal V_eaDetermine.P₂₁Signal again with clock signal clk With output to pulse modulation unit P_G, with operation limit the maximum duty of square wave of P_G reception Ratio.P_G produces corresponding to square wave P₂₁Rising edge and the burst pulse of trailing edge, when square wave rising edge arrives, In P_G unit, due to the 3rd current source I_s31To the second electric capacity C₃₁The time-lag action of charging, second or non- Door NOR₃₁Two inputs keep the electronegative potential of a very short time, then NOR simultaneously₃₁Outfan give Go out the burst pulse corresponding to square wave rising edge.In like manner, when square wave trailing edge arrives, the 3rd nor gate NOR₃₂ Provide a burst pulse corresponding to trailing edge.Pulse signal is transferred to main limit through Magnetic isolation coupling transformer Square wave reduction unit P_R, rising edge pulse and trailing edge pulse are separately input to the 2nd RS after treatment and touch Send out S end and the R end of device, then the Q end of the second rest-set flip-flop provides the square wave P after reduction₂₂。P₂₂Signal Through the first phase inverter NOT₂₁Produce inversion signal P afterwards₂₃Control the 3rd switching tube PM₂₂Conducting or Turn off.Meanwhile, P₂₂Signal produces a time delay t to its trailing edge after delay circuit Delay_D, obtain Obtain P₂₄Signal.P₂₄Signal obtains P after anti-phase₂₅Signal controls the 4th switching tube NM₂₂Conducting Or turn off.Due to P₂₄Relative to P₂₃The many time delay t of rising edge_D, so sawtooth waveforms reduction electric capacity C₂₂ On sawtooth waveforms V_{saw_res}A period of time t can be kept at peak value_D, this makes the first transmission gate TG₂₁With sampling electricity Hold C₂₃V can be sampled exactly_{saw_res}Current potential during peak value, and the height of spike potential is put with secondary error Error signal V of big device output_eaIt is directly proportional.The sampling pulse of sampling hold circuit is by P₂₂With P₂₅Xiang Huo Non-acquisition, the width of sampling pulse and t_DIdentical.Final at sampling capacitance C₂₃Upper generation secondary error signal V_eaThe recovering signal V of discretization_{ea_res}。

The beneficial effects of the present invention is:

1, provide above-mentioned a kind of magnetic isolation feedback circuit, instead of light-coupled isolation feedback, eliminate the optocoupler longevity Life and the performance degradation impact on product, it is possible to reduce the error signal of secondary exactly, it is achieved the closed loop control of main limit System；

2, above-mentioned modulation and demodulation circuit is introduced, outside therefore eliminating needed for tradition Magnetic isolation feedback chip Enclose rectification discrete device, simplify circuit design；

3, the burst pulse of isolation coupling transformator transmission has fixing amplitude and width, thus improves anti-dry Disturb ability, simplify the design of Magnetic isolation transformator.

Accompanying drawing explanation

Fig. 1 is the typical applied topology of magnetic isolation feedback circuit of the present invention；

Fig. 2 is magnetic isolation feedback circuit figure of the present invention；

Fig. 3 is pulse modulation unit of the present invention and main limit square wave reduction unit circuit diagram；

The oscillogram of error signals modulate in Fig. 4 embodiment one；

The oscillogram of error signal demodulation in Fig. 5 embodiment one；

Analogous diagram before and after the reduction of Fig. 6 error signal.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing 2, right The present invention further describes.Should be appreciated that specific embodiment described herein is only in order to explain this Bright, it is not intended to limit the present invention.

Embodiment one

A kind of magnetic isolation feedback circuit, as in figure 2 it is shown, include: secondary chip Sec_IC, main limit chip Pri_IC, Compensate circuit and Magnetic isolation coupling transformer T2.

Compensate circuit and include the first electric capacity C_cWith the first resistance R_c, C_cAnd R_cSeries connection.

Secondary chip includes error amplifier EA, error signals modulate unit 21 and pulse modulation unit P_G.

Wherein, error signals modulate unit 21 includes the first agitator OSC₂₁, the first comparator COM₂₁、 First with door AND and sawtooth waveforms generation unit 22.Sawtooth waveforms generation unit 22 includes the first switching tube PM₂₁, the first current source I_s21, sawtooth waveforms produce electric capacity C₂₁With second switch pipe NM₂₁.Error amplifier The reference voltage V that the forward termination chip internal of EA produces_ref, sampled value K*V of electric power output voltage_outLogical Crossing FB port and be input to the negative end of error amplifier EA, the outfan of EA connects the first comparator respectively COM₂₁Forward end and the COMP port of secondary chip；Compensate circuit by the first electric capacity Cc and the first resistance Rc is composed in series, and the two ends compensating circuit are connected respectively to negative end and the COMP end of error amplifier EA Mouthful.First comparator COM₂₁Negative end respectively with sawtooth waveforms produce electric capacity C₂₁One end, the first electric current Source I_s21Negative pole and second switch pipe NM₂₁Drain electrode connect；First comparator COM₂₁Output termination first An input with door AND.Another input termination first agitator OSC of AND₂₁Produce time Clock signal CLK；Output termination pulse modulation unit P_G of AND.First agitator OSC₂₁Anti-phase time Clock outfan CLK_ meets the first switching tube PM₂₁Grid and second switch pipe NM₂₁Grid.First switch Pipe PM₂₁Source electrode meet power supply VCC, the first switching tube PM₂₁Drain electrode meet the first current source I_s21Positive pole. Second switch pipe NM₂₁Drain electrode connect sawtooth waveforms produce electric capacity C₂₁One end and the first current source I_s21Negative pole, Second switch pipe NM₂₁Source electrode and sawtooth waveforms produce electric capacity C₂₁Other end ground connection together.Impulse modulation list The outfan of unit P_G connects the positive input of outside isolating transformer T2 by TRP port and TRN port.

Main limit chip includes that main limit square wave reduction unit P_R, main edge error signal demodulation unit 23, second compare Relatively device COM₂₂, the first rest-set flip-flop FF₂₁With the second agitator OSC₂₂。

Wherein, main edge error signal demodulation unit 23 includes the first phase inverter NOT₂₁, delay circuit Delay, Second phase inverter NOT₂₂, the 3rd switching tube PM₂₂, the second current source I_s22, sawtooth waveforms reduction electric capacity C₂₂、 4th switching tube NM₂₂, the first nor gate NOR₂₁, the first transmission gate TG₂₁, the 3rd phase inverter NOT₂₃、 Sampling capacitance C₂₃.Outside the input of main limit square wave reduction unit P_R is connected by SN port and SP port The outfan of the Magnetic isolation coupling transformer in portion, the outfan of P_R meets the first phase inverter NOT respectively₂₁Defeated Enter end, the input of delay circuit Delay and the first nor gate NOR₂₁An input；First is anti-phase Device NOT₂₁Output termination the 3rd switching tube PM₂₂Grid, the 3rd switching tube PM₂₂Source electrode and drain electrode Meet power supply VCC and the second current source I respectively_s22Positive pole；Sawtooth waveforms reduction electric capacity C₂₂Two ends connect respectively Two current source I_s22Negative pole and ground；4th switching tube NM₂₂Drain electrode and source electrode meet the second current source I respectively_s22 Negative pole and ground；The output of delay circuit Delay terminates the second phase inverter NOT₂₂Input, second is anti-phase Device NOT₂₂Outfan be connected on the 4th switching tube NM₂₂Grid and the first nor gate NOR₂₁Another is defeated Enter end；First nor gate NOR₂₁Output termination the first transmission gate control end and the input of the 3rd phase inverter End, the output of the 3rd phase inverter terminates the first transmission gate TG₂₁Another control end, the first transmission gate TG₂₁'s Input termination the second current source I_s22Negative pole, the first transmission gate TG₂₁Output termination sampling capacitance C₂₃One End and the second comparator COM₂₂Positive input, the second comparator COM₂₂Negative input pass through CS port connects ground connection after external inductors current sampling resistor Rs, the second comparator COM₂₂Output termination First rest-set flip-flop FF₂₁Reset terminal R.First rest-set flip-flop FF₂₁Set end S connect the second agitator OSC₂₂Output terminal of clock CLK, the first rest-set flip-flop FF₂₁Outfan Q connect by GATE port Power switch pipe M outside chip_p。

As it is shown on figure 3, pulse modulation unit P_G includes the 4th phase inverter NOT₃₁, the 5th switching tube PM₃₁、 6th switching tube NM₃₁, the 3rd current source I_s31, the second electric capacity C₃₁, the first Schmidt trigger SMT₃₁、 5th phase inverter NOT₃₂, the second nor gate NOR₃₁, the 4th current source I_s32, the 7th switching tube PM₃₂, Eight switching tube NM₃₂, the 3rd electric capacity C₃₂, the second Schmidt trigger SMT₃₂, hex inverter NOT₃₃, 3rd nor gate NOR₃₂.4th phase inverter NOT₃₁Input termination error signals modulate unit 21 output End, and it is connected respectively to the 7th switching tube PM₃₂Grid, the 8th switching tube NM₃₂Grid and the 3rd Nor gate NOR₃₂An input；4th phase inverter NOT₃₁Outfan connect the 5th switching tube respectively PM₃₁Grid, the 6th switching tube NM₃₁Grid and the second nor gate NOR₃₁An input；The Five switching tube PM₃₁Source electrode meet the 3rd current source I_s31Negative pole, the 5th switching tube PM₃₁Drain electrode and the 6th The drain electrode of switching tube connects one end and the input of the first Schmidt trigger of the second electric capacity respectively；6th switching tube NM₃₁Source ground；First Schmidt trigger SMT₃₁Output termination the 5th phase inverter NOT₃₂Defeated Enter end, the 5th phase inverter NOT₃₂Output terminate the second nor gate NOR₃₁Another input；Second Nor gate NOR₃₁Output termination Magnetic isolation coupling transformer T2 positive input.7th switching tube PM₃₂ Source electrode meet the 4th current source I_s32Negative pole, the 7th switching tube PM₃₂Drain electrode and the 8th switching tube NM₃₂ Drain electrode meet the 3rd electric capacity C respectively₃₂One end and the second Schmidt trigger SMT₃₂Input, the 8th opens Close pipe NM₃₂Source ground；Second Schmidt trigger SMT₃₂Output terminate hex inverter NOT₃₃ Input, hex inverter NOT₃₃Output termination the 3rd nor gate NOR₃₂Another input； 3rd nor gate NOR₃₂Output termination Magnetic isolation coupling transformer T2 negative input.Two of T2 Output terminates the input of main limit square wave reduction unit P_R.

Main limit square wave reduction unit P_R includes the second rest-set flip-flop FF₃₁, FF₃₁S end and R end respectively Receive two outfans of Magnetic isolation coupling transformer T2.

Below the operation principle substep that it is concrete is illustrated.

1, secondary error signal V_eaModulation

Agitator OSC₂₁Clock signal clk _ control the PM of output₂₁And NM₂₁Turn-on and turn-off, and then Control current source I_s21To electric capacity C₂₁Discharge and recharge.Due to PM₂₁And NM₂₁It is respectively PMOS and NMOS Pipe, thus two switching tube alternate conduction, when CLK_ is low level, PM₂₁Conducting NM₂₁Turn off, I_s21 With constant electric current I_chargeTo C₂₁Charging.Assume OSC₂₁The dutycycle of the clock CLK produced is D, week Phase is T, then inversion clock CLK_ is low level time t_LFor T*D.OSC is set herein₂₁Account for maximum Empty than 80% output clock CLK, then sawtooth waveforms V_sawAmplitude can be given by:

$V_{saw}=\frac{I_{ch\arg e}*T*D}{C_{saw}}=\frac{I_{ch\arg e}*T*0.8}{C_{saw}}$

In formula, C_sawFor electric capacity C₂₁Capacitance.

When CLK_ is high level, PM₂₁Turn off NM₂₁Conducting is rapidly to C₂₁Electric discharge.Sawtooth waveforms V_saw's Cycle is identical with CLK, by comparator COM₂₁Signal V with error amplifier EA output_eaThan than The rear square-wave signal P producing modulation₂₁, it is assumed that its dutycycle is D_p1, specific D in the most single cycle_p1Value table Levy V in this cycle_eaThe size of amplitude, corresponding relation is:

$V_{ea}=V_{saw}*\frac{D_{p1}}{D}=V_{saw}*\frac{D_{p1}}{0.8}$

The waveform of part signal is shown in Fig. 4.P₂₁Signal and CLK signal the most therewith after adjust through extra pulse modulating unit P_G Make the narrow pulse signal corresponding with its rising edge and trailing edge, it is simple to the transmission of Magnetic isolation coupling transformer.By Level in isolation transformation reception is all the burst pulse of fixed amplitude and width, thus simplifies Magnetic isolation coupling and become The design of depressor, improves capacity of resisting disturbance.

2, the reduction of main edge error signal

The narrow pulse signal that Magnetic isolation coupling transformer passes over reduces after square wave reduction unit P_R For with P₂₁Identical square-wave signal P₂₂, the dutycycle in its single cycle is also D_p1。P₂₂Anti-through first Phase device NOT₂₁Produce inversion signal P afterwards₂₃, in order to control the 3rd switching tube PM₂₂Turn-on and turn-off. Meanwhile, P₂₂After delay unit Delay, trailing edge produces a time delay t_D, it is thus achieved that P₂₄Signal, t_D's Size can be arranged according to demand.P₂₄Through the second phase inverter NOT₂₂Produce P afterwards₂₅Signal in order to Control the 4th switching tube NM₂₂Break-make.By current source I_s22To sawtooth waveforms reduction electric capacity C₂₂Charging.In order to Readily appreciate, it is assumed herein that I_s22With secondary current source I_s21Identical, C₂₂With C₂₁Identical.Because there is time delay t_D, PM₂₂ON time be T*D_p1, and NM₂₂ON time be T* (1-D_p1-t_D), then at PM₂₂ After shutoff, the sawtooth waveforms V of reduction_{saw_res}Peak value can be at C₂₂One time t of upper holding_D, then pass through NM₂₂Charge discharging resisting is fallen.T is set_DPurpose be easy for subsequent sampling holding circuit and have time enough accurate Sample crest voltage.Ideally, V_{saw_res}Peak value should be with the V of each cycle internal modulation_eaPhase With.P₂₂With P₂₅Phase or non-generation the first transmission gate TG afterwards₂₁Control signal Sa, TG₂₁Keep with sampling Electric capacity C₂₃Composition sampling hold circuit, to V_{saw_res}Peak value sample and keep, then at C₂₃On can obtain The V of the discretization after must reducing_{ea_res}Signal.

3, the realization of current-mode

The electric current of power stage static exciter inductance produces pressure drop C on sampling resistor Rs_S.After reduction V_{ea_res}Signal and C_SRelatively produce reset signal Ctrl in each cycle, switch-off power pipe.And the leading of each cycle The logical moment is by OSC₂₂The clock CLK produced determines.Work as FF₂₁Reset terminal when being high level, CLK signal Low level make FF₂₁Q end set be 1, open peripheral power tube, power stage transformator starts excitation. And as current potential C on sampling resistor Rs_SReach V_{ea_res}Value, then produce low level Ctrl reset FF₂₁, Q end Being reset to 0, switch-off power pipe, power stage transformator starts degaussing.So, be achieved that traditional Peak Current Mode controls.

Sum it up, the basic thought of the present invention is: voltage magnitude signal is modulated to pulse width information, logical After crossing the transmission of Magnetic isolation coupling transformer, then this pulse width information is reduced to voltage magnitude signal.So, Embodiments of the present invention are not limited to this, according to foregoing, according to the ordinary technical knowledge of this area and usual Means, without departing under the present invention above-mentioned basic fundamental thought premise, the magnetic isolation feedback circuit of the present invention also has Other embodiment；Therefore the present invention can also make the amendment of other various ways, replace or change, all Fall within the scope of rights protection of the present invention.

Claims (7)

1. a magnetic isolation feedback circuit, including secondary chip, compensate circuit, Magnetic isolation coupling transformer and Main limit chip；Secondary chip is by the information of FB port sampling power output end, and is translated into error letter Number, the one end compensating circuit is exported by COMP port, the other end compensating circuit is connected to FB port； Meanwhile, being pulse signal by error signals modulate exports Magnetic isolation coupling via TRP port and TRN port Transformator, is connected to SP port and the SN port of main limit chip by Magnetic isolation coupling transformer；Main limit core The pulse signal comprising error signal information is reduced to error signal by sheet, it is achieved closed loop control；It is characterized in that:

Described secondary chip includes error amplifier, error signals modulate unit and pulse modulation unit；Described Error amplifier forward termination chip internal produce reference voltage V_ref, described error amplifier negative sense End receives sampled value K*V of electric power output voltage_out, described error amplifier output error signal is believed to error Number modulating unit；Described error signals modulate unit by error signals modulate be after square-wave signal output to described Pulse modulation unit；Square-wave frequency modulation is that burst pulse exports Magnetic isolation coupling change by described pulse modulation unit Depressor；

Described main limit chip includes main limit square wave reduction unit, main edge error signal demodulation unit, second compares Device, the first rest-set flip-flop and the second agitator；The input of described main limit square wave reduction unit passes through SN Port and SP port connect the outfan of described Magnetic isolation coupling transformer, described main limit square wave reduction unit Outfan outputs signals to described main edge error signal demodulation unit；The positive input of described second comparator connects Receiving the output signal of autonomous edge error signal demodulation unit, the negative input of described second comparator passes through CS port connects ground connection after inductive current sampling resistor, and the output of described second comparator terminates a described RS The reset terminal R of trigger；The clock that the set end S of described first rest-set flip-flop connects described second agitator is defeated Going out and hold CLK, the outfan Q of described first rest-set flip-flop connects power switch pipe by GATE port.

Magnetic isolation feedback circuit the most according to claim 1, it is characterised in that: described error signal Modulating unit includes the first agitator, the first comparator, first and door and sawtooth waveforms generation unit；Described The forward end of one comparator connects the outfan of described error amplifier, and the negative end of the first described comparator is even Receive described sawtooth waveforms generation unit；The first described comparator output terminal meets of described first and door Input, described first be the clock signal of described first agitator generation with another input termination of door CLK；Described first with door output termination described in pulse modulation unit；The first described agitator anti-phase Output terminal of clock CLK_ connects described sawtooth waveforms generation unit.

Magnetic isolation feedback circuit the most according to claim 2, it is characterised in that: described sawtooth waveforms produces Raw unit includes that the first switching tube, the first current source, sawtooth waveforms produce electric capacity and second switch pipe；Described The inversion clock that the grid of one switching tube and the grid of described second switch pipe connect the first described agitator is defeated Go out to hold CLK_；The source electrode of described first switching tube meets power supply VCC, and the drain electrode of described first switching tube connects described The positive pole of the first current source；The drain electrode of described second switch pipe connects described sawtooth waveforms and produces one end of electric capacity and described The negative pole of the first current source, the source electrode of described second switch pipe and sawtooth waveforms produce the other end of electric capacity together with connect Ground.

Magnetic isolation feedback circuit the most according to claim 1, it is characterised in that: described impulse modulation Unit include the 4th phase inverter, the 5th switching tube, the 6th switching tube, the 3rd current source, the second electric capacity, first Schmidt trigger, the 5th phase inverter, the second nor gate, the 4th current source, the 7th switching tube, the 8th switch Pipe, the 3rd electric capacity, the second Schmidt trigger, hex inverter and the 3rd nor gate；Described 4th phase inverter Input terminate the outfan of described error signals modulate unit, and be connected respectively to described 7th switching tube Grid, the grid of described 8th switching tube and an input of described 3rd nor gate；Described 4th phase inverter Outfan connect the grid of described 5th switching tube, the grid and described second or non-of described 6th switching tube respectively One input of door；The source electrode of described 5th switching tube connects the negative pole of described 3rd current source, and the described 5th opens The drain electrode of pass pipe drain electrode and described 6th switching tube connects one end and described first of described second electric capacity respectively and executes close The input of special trigger；The source ground of described 6th switching tube；The output of described first Schmidt trigger Terminating the input of described 5th phase inverter, the output of described 5th phase inverter terminates the another of described second nor gate One input；The output of described second nor gate terminates the positive input of described Magnetic isolation coupling transformer； The source electrode of described 7th switching tube connects the negative pole of described 4th current source, the drain electrode of described 7th switching tube and described The drain electrode of the 8th switching tube connects one end and the input of described second Schmidt trigger of described 3rd electric capacity respectively End, the source ground of described 8th switching tube；The output termination of described second Schmidt trigger is described 6th anti- The input of phase device, the output of described hex inverter terminates another input of described 3rd nor gate；Institute The output stating the 3rd nor gate terminates the negative input of described Magnetic isolation coupling transformer.

Magnetic isolation feedback circuit the most according to claim 1, it is characterised in that: described main edge error Signal demodulation unit include the first phase inverter, delay circuit Delay, the second phase inverter, the 3rd switching tube, Two current sources, sawtooth waveforms reduction electric capacity, the 4th switching tube, the first nor gate, the first transmission gate, the 3rd anti-phase Device, sampling capacitance；The input of described first phase inverter, the input of described delay circuit Delay and institute The input stating the first nor gate connects the outfan of described main limit square wave reduction unit respectively；Described first The output of phase inverter terminates the grid of described 3rd switching tube, the source electrode of described 3rd switching tube and drain electrode and connects respectively Power supply VCC and the positive pole of described second current source；The two ends of described sawtooth waveforms reduction electric capacity connect described the respectively The negative pole of two current sources and ground；The drain electrode of described 4th switching tube and source electrode connect the negative of described second current source respectively Pole and ground；The output of described delay circuit Delay terminates the input of described second phase inverter, described second anti- The output of phase device terminates grid and another input of described first nor gate of described 4th switching tube；Described The output of the first nor gate terminates a control end and the input of described 3rd phase inverter of described first transmission gate End, the output of described 3rd phase inverter terminates another control end of described first transmission gate, described first transmission gate Input terminate the negative pole of described second current source, the output of described first transmission gate terminates described sampling capacitance One end and the positive input of described second comparator.

Magnetic isolation feedback circuit the most according to claim 1, it is characterised in that: described main limit square wave Reduction unit includes the second rest-set flip-flop, and the S end of described second rest-set flip-flop and R end are respectively by main limit Chip SP port and SN port receive two outfans of described Magnetic isolation coupling transformer, described 2nd RS Square wave after the Q end output reduction of trigger.

Magnetic isolation feedback circuit the most according to claim 1, it is characterised in that: described compensation circuit Including the first electric capacity and the first resistance, the first described electric capacity and the first resistant series.