CN104319265A - Component embedded packaging structure, semiconductor device and manufacturing method of packaging structure - Google Patents
Component embedded packaging structure, semiconductor device and manufacturing method of packaging structure Download PDFInfo
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- CN104319265A CN104319265A CN201410424515.4A CN201410424515A CN104319265A CN 104319265 A CN104319265 A CN 104319265A CN 201410424515 A CN201410424515 A CN 201410424515A CN 104319265 A CN104319265 A CN 104319265A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
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- H—ELECTRICITY
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a component embedded packaging structure, a semiconductor device and a manufacturing method of the packaging structure. The component embedded packaging structure comprises a bare chip, a first pin, a second pin, a first dielectric layer, a patterned conductive layer, a second dielectric layer and a conductive layer, wherein the bare chip is arranged on a bare chip pedestal; the first pin and the second pin are arranged at the periphery of the bare chip pedestal; the first dielectric layer covers the bare chip, the bare chip pedestal, the first pin and the second pin, and is provided with a first through hole exposed out of at least partial bare chip and a second through hole exposed out of at least partial second pin; one side surface of a first dielectric material is substantially flush with one side surface of the first pin; the patterned conductive layer is arranged on the upper surface of the first dielectric layer, electrically connected with the bare chip by the first through hole, and electrically connected with the second pin by the second through hole; the second dielectric layer is arranged on the first dielectric layer, and covers the patterned conductive layer; and the conductive layer wraps the upper surface and the side surface of the second dielectric layer and the side surface of the first dielectric layer, and is directly contacted with the side surface of the first pin.
Description
Technical field
The present invention relates to a kind of semiconductor packages and manufacture method thereof.
Background technology
Be subject to promoting processing procedure speed and result of scaling demand, semiconductor packages becomes very complicated.When the lifting of processing procedure speed and undersized benefit obviously increase, the characteristic of semiconductor packages also goes wrong.Refer to especially, higher work time pulse (clock speed) causes transition (transition) frequently between signal level (signal level), thus causes in high frequency or the electromagnetic radiation (electromagnetic emission) of higher-strength under shortwave.Electromagnetic radiation can radiation from semiconductor packages and contiguous semiconductor element.If the intensity of the electromagnetic radiation of contiguous semiconductor element is higher, the running that this electromagnetic radiation affects element in semiconductor packages negatively (is electromagnetic interference (electromagnetic interference; EMI)).Especially, when current technology pursue makes part semiconductor element be embedded in substrate, during to vacate space with stacking more multiple semiconductor element, because its semiconductor element density uprises, the distance of itself and other semiconductor element shortens, and this problem seems more important.In addition, still need and consider the design problem electrical ground of this kind of semiconductor packages and/or semiconductor element.Therefore, how can when semiconductor package part size be more and more less, meet it and avoid other semiconductor element electromagnetic interference and meet the important topic that its demand electrical ground just becomes modern devices embedded substrate encapsulation technology.
Summary of the invention
An aspect of of the present present invention relates to a kind of component-embedded encapsulating structure.In one embodiment, described component-embedded encapsulating structure comprises: nude film bearing; Nude film, is placed in described nude film bearing; First pin and the second pin, be placed in around described nude film bearing; First dielectric layer, cover described nude film, described nude film bearing, described first pin and described second pin, and described first dielectric layer has the first through hole, expose at least part of described nude film, and second through hole, expose at least part of described second pin, a side of wherein said first dielectric substance flushes in fact with a side of described first pin; Patterned conductive layer, is placed on the upper surface of described first dielectric layer, and wherein said patterned conductive layer is electrically connected by described first through hole and described nude film, and described patterned conductive layer is electrically connected by described second through hole and described second pin; Second dielectric layer, is placed on described first dielectric layer, and described second dielectric layer covers described patterned conductive layer; And conductive layer, coated described second dielectric layer upper surface and side, and the described side of described first dielectric layer, and directly contact with the described side of described first pin.
Another aspect of the present invention relates to a kind of semiconductor device.In one embodiment, described semiconductor device comprises: nude film bearing; Nude film, is placed in described nude film bearing; First pin and the second pin, be placed in around described nude film bearing; First dielectric layer, cover described nude film, described nude film bearing, described first pin and described second pin, and described first dielectric layer has the first through hole, expose at least part of described nude film, and second through hole, expose at least part of described second pin, a side of wherein said first dielectric substance flushes in fact with a side of described first pin; Patterned conductive layer, is placed on the upper surface of described first dielectric layer, and wherein said patterned conductive layer is electrically connected by described first through hole and described nude film, and described patterned conductive layer is electrically connected by described second through hole and described second pin; Second dielectric layer, is placed on described first dielectric layer, and described second dielectric layer covers described patterned conductive layer, and has third through-hole, the described patterned conductive layer of exposed portion; Element is electrically connected by described third through-hole and described patterned conductive layer; Coated described second dielectric layer of 3rd dielectric layer and described element; And conductive layer, conformal coating (conformally coating) in the surface of described 3rd dielectric layer and side, a side of described second dielectric layer and the described side of described first dielectric layer, and directly contacts with the described side of described first pin.In another embodiment, described semiconductor device comprises: conductive frame (lead frame), and described conductive frame comprises die pad, and the first pin and the second pin are placed in around described die pad; Nude film, is placed in described die pad; First dielectric layer, covers described nude film and described conductive frame, and the side of wherein said first dielectric layer is in the face of a side of described first pin together; First conductive through hole, is placed in described first dielectric layer, is electrically connected with described nude film; Second conductive through hole, is placed in described first dielectric layer, is electrically connected with described second pin; Patterned conductive layer, is placed on the upper surface of described first dielectric layer, is electrically connected described first conductive through hole and described second conductive through hole; Second dielectric layer, covers on described first dielectric layer and described patterned conductive layer; And metal level, conformal coating (conformally coating) upper surface at described second dielectric layer and the side of side and described first dielectric layer, and directly contact with the side of described first pin.
Another aspect of the present invention relates to a kind of manufacture method of component-embedded encapsulating structure.In one embodiment, described method comprises: provide underlying structure, and described underlying structure comprises at least one nude film bearing, at least the first pin and at least one second pin; Arrange that nude film is in described nude film bearing; Arrange that the first dielectric layer is on described substrat structure, described first dielectric layer covers described nude film, described nude film bearing, described first pin and described second pin; Form the first opening at described first dielectric layer, expose the described nude film of part; Form the second opening at described first dielectric layer, expose described second pin of part; With selective electroplating mode formed patterned conductive layer on described first dielectric layer, described first opening and described second opening; Arrange that the second dielectric layer covers described first dielectric layer and described patterned conductive layer; Etching described underlying structure makes described nude film bearing, described first pin and described second pin be separated (isolated); Carry out cutting single stage, described in cut single stage and expose a side of described first dielectric layer and a side of described first pin, the described side of wherein said first dielectric layer flushes with the described side of described first pin; And settle metal level to cover the upper surface of described second dielectric layer and the described side of described first dielectric layer, and the described side of described first pin.
Other side of the present invention and embodiment also contain.Aforesaid summary of the invention and the following description the present invention is limited to any specific embodiment by not intended to be, and only for illustration of some embodiment of the present invention.
Accompanying drawing explanation
Fig. 1 display is according to the profile of an embodiment of the component-embedded substrate package structure of the present invention.
Fig. 2 display is according to the profile of another embodiment of the component-embedded substrate package structure of the present invention.
Fig. 3 display is according to the profile of an embodiment of semiconductor device of the present invention.
Fig. 4 display is according to the profile of another embodiment of semiconductor device of the present invention.
Fig. 5 display is according to the profile of another embodiment of the component-embedded substrate package structure of the present invention.
Fig. 6 A to 6I illustrates an embodiment of the method according to component-embedded substrate package structure of the present invention.
Illustrating the graphic of the embodiment of the present invention and related description thereof, is the principle for explaining some embodiment of the present invention.
Embodiment
Please refer to Fig. 1, it illustrates the profile of the embodiment according to the component-embedded encapsulating structure of the present invention.Described component-embedded encapsulating structure 100 comprises nude film 102, nude film bearing 104, first pin 106, second pin 108, first dielectric layer 110, patterned conductive layer 112, second dielectric layer 114 and conductive layer 116.
Described nude film 102 has active surface 102a and the back side 102b relative to described active surface 102a.Described nude film 102 can have the connection pad 103 be connected with exposed electrical, and the back side 102b of described nude film is attached in described nude film bearing 104 by adhesion coating 118.
Described first pin 106 and described second pin 108 are settled around described nude film bearing 104.Described first pin 106 has first surface 106a, second surface 106b and connects the lateral surface 106c of first surface 106a and second surface 106b.Described second pin 108 has first surface 108a, second surface 108b and connects the lateral surface 108c of first surface 108a and second surface 108b.In one embodiment, described first pin 106 is for ground connection.In one embodiment, described nude film bearing 104, described first pin 106 and described second pin 108 can be a part of conductive frame (lead frame).
Described first dielectric layer 110 has upper surface 110a and lower surface 110b.Described first dielectric layer 110 is placed on described nude film 102, described nude film bearing 104, described first pin 106 and described second pin 108.Described first dielectric layer 110 around described nude film 102, and can infiltrate and the space inserted between described nude film bearing 104 and described first pin 106 and the space between described nude film bearing 104 and described second pin 108.The side 110c of described first dielectric layer 110 flushes in fact with the lateral surface 106c of described first pin 106, and lateral surface 108c interval one distance of the side 110d of described first dielectric layer 110 and described second pin 108.
Described first dielectric layer 110 can have the first through hole, the connection pad 103 of described nude film 102 is extended to from the upper surface 110a of described first dielectric layer 110, expose the connection pad 103 of nude film 102, and second through hole, the upper surface 108a of described second pin 108 is extended to from the upper surface 110a of described first dielectric layer 110.The first electrical interconnections 120 and the second electrical interconnections 122 can be respectively equipped with in described through hole.
Described first dielectric layer 110 can comprise polymerism dielectric substance or non-polymerization dielectric substance.For example, described first dielectric layer 110 can comprise the dielectric substance of more flowability, and it includes but not limited to: liquid crystal polymer, prepreg (prepreg) backing material, ABF class (Ajinomoto build-up film) material, resin material, epoxy compounds or its analog.Described first dielectric layer 110 can have single resin bed or multilayer, the first sublevel be made up of resin as comprised and the second sublevel (as used glass fibre and/or the fibre-reinforced resin of Kevlar) be made up of the resin strengthened.In one embodiment, described first dielectric layer 110 comprises prepreg material.Described prepreg material can be made up of one deck or two-layer above prepreg; Or comprise at least one deck prepreg and at least one deck resin bed.
Described patterned conductive layer 112 is placed on the upper surface 110a of described first dielectric layer 110, and on described upper surface 110a, essence extends laterally.Described patterned conductive layer 112 is electrically connected with the connection pad 103 of described nude film 102 through described first electrical interconnections 120, and is electrically connected with described second pin 108 through described second electrical interconnections 122.Therefore described nude film 102 can pass through described first electrical interconnections 120, described patterned conductive layer 112 and described second electrical interconnections 122 and is electrically connected with described second pin 108.
Described second dielectric layer 114 is placed on described first dielectric layer 110, inserts opening that described patterned conductive layer 112 defines and covers described patterned conductive layer 112.Described second dielectric layer 114 can be welding resisting layer (solder mask or solder resist).For example, described second dielectric layer 114 can be made up of the material of photosensitive dry film or other kind of patternable, such as, can be but be not limited to polyimides.
Described conductive layer 116 is placed on described second dielectric layer 114, the upper surface of coated described second dielectric layer and side, side 110c and 110d of described first dielectric layer 110, and directly contact with the side 106c of described first pin 106, whereby, the semiconductor element that this semiconductor package part can be avoided to be close to and/or the electromagnetic interference of semiconductor packages, to make described semiconductor package part energy smooth operation.In addition, because described conductive layer 116 is in electrical contact with described described first pin 106 for ground connection, described conductive layer 116 can provide the function of ground connection simultaneously.In addition, the side 110d of described first dielectric layer 110 and 108c interval one, the side distance of described second pin 108, whereby, to avoid described second pin 108 to be electrically conducted by described conductive layer 116 with described first pin 106 of ground connection, cause short circuit.
Described conductive layer 116 can comprise the electric conducting material of any tool electromagnetic shielding effect or any metal material utilizing plating or electroless plating to be formed, as metal, metal alloy, metal or metal alloy are scattered in matrix wherein.For example, described conductive layer 116 can comprise copper or conducting resinl.
Although Fig. 1 depicts the first dielectric layer 110 and the second dielectric layer 114, in fact, described first dielectric layer 110 can without obvious boundary with described second dielectric layer 114, and namely it can be same material composition.Although Fig. 1 only depicts one deck first dielectric layer 110 and one deck second dielectric layer 114, in other embodiments, the first dielectric layer 110 and the second dielectric layer 114 can respectively form more than two-layer.
Aforesaid first electrical interconnections 120 and the second electrical interconnections 122 can utilize any available material composition in field of the present invention, such as, comprise metal, metal alloy, have metal or metal alloy and intersperse among material wherein or suitable electric conducting material.For example, the material of described first electrical interconnections 120 and the second electrical interconnections 122 can comprise aluminium, copper, titanium or its combination.In one embodiment, described first electrical interconnections 120 and the second electrical interconnections 122 can comprise copper.Aforesaid patterned conductive layer 112 can utilize any available material composition in field of the present invention, such as, can comprise metal, metal alloy, have metal or metal alloy and intersperse among material wherein or suitable electric conducting material.For example, aforesaid patterned conductive layer 112 can comprise aluminium, copper, titanium or its combination.In one embodiment, aforesaid patterned conductive layer 112 can comprise copper.The material of described first electrical interconnections 120 and the second electrical interconnections 122 and described patterned conductive layer 112 may be the same or different.
Please refer to Fig. 2, it illustrates the profile of another embodiment according to the component-embedded encapsulating structure of the present invention.Described encapsulating structure 200 is similar with that shown in Figure 1 in many aspects, therefore, its main difference part only will be discussed herein.In this embodiment, 3rd dielectric layer 228 is placed on the second surface 208b of the back side 210b of described first dielectric layer 210, the back side 204b of described nude film bearing 204, the second surface 206b of described first pin 206 and described second pin 208, inserts the opening that described nude film bearing 204 defines with described first pin 206 and described second pin 208.Described 3rd dielectric layer 228 can have opening, exposes described nude film bearing 204, described first pin 206 and the part of described second pin 208 for being connected with outside.Described 3rd dielectric layer 228 can be welding resisting layer (solder mask or solder resist).For example, described 3rd dielectric layer 228 can be made up of the material of photosensitive dry film or other kind of patternable, such as, can be but be not limited to polyimides.
Please refer to Fig. 3, it illustrates the profile of the embodiment according to semiconductor device of the present invention.Described semiconductor device 300 is similar with that shown in Figure 1 in many aspects, therefore, its main difference part only will be discussed herein.In this embodiment, described second dielectric layer 314 has opening, exposes the part of described patterned conductive layer 312 as exposed electrical contact, such as, connection pad for being connected with scolding tin or soldered ball.As shown in the figure, scolding tin or soldered ball 330 can be inserted in the opening that described second dielectric layer 314 defines, and be electrically connected, encapsulate to provide systematic with element 332 (can be initiatively or passive device).3rd dielectric layer (can be encapsulating material) 334 is placed on described second dielectric layer 314, coated described element 332.In this embodiment, described conductive layer 316 be conformal coating (conformally coating) in the surface of described 3rd dielectric layer 334 and side, the side of described second dielectric layer 314, the side of described first dielectric layer 310, and directly contact with the side 306c of described first pin 306, whereby, the semiconductor element that this systematic packaging part can be avoided to be close to and/or the electromagnetic interference of semiconductor packages, to make described systematic packaging part energy smooth operation, and provide grounding function by being connected with the first pin 306 of ground connection.
Please refer to Fig. 4, it illustrates the profile of another embodiment according to semiconductor device of the present invention.Described encapsulating structure 400 is similar with that shown in Figure 3 in many aspects, therefore, its main difference part only will be discussed herein.In this embodiment, 4th dielectric layer 428 is placed on the second surface 408b of the back side 410b of described first dielectric layer 410, the back side 404b of described nude film bearing 404, the second surface 406b of described first pin 406 and described second pin 408, inserts the opening that described nude film bearing 404 defines with described first pin 406 and described second pin 408.Described 4th dielectric layer 428 can have opening, exposes described nude film bearing 404, described first pin 406 and the part of described second pin 408 for being connected with outside.Described 4th dielectric layer 428 can be welding resisting layer (solder mask or solder resist).For example, described 4th dielectric layer 428 can be made up of the material of photosensitive dry film or other kind of patternable, such as, can be but be not limited to polyimides.
Please refer to Fig. 5, it illustrates the profile of another embodiment according to the component-embedded encapsulating structure of the present invention.Described encapsulating structure 500 is similar with that shown in Figure 1 in many aspects, therefore, its main difference part only will be discussed herein.In this embodiment, described second pin 508 more comprises the Part I 508e being embedded in described first the dielectric layer 510 and Part II 508f given prominence to outside the first dielectric layer 510.In one embodiment, described second pin 508 more comprises the intersection that summit 508c (apex) is positioned at described Part I 508e and described Part II 508f.The side of described Part II 508f has recess.The surperficial 508d of described recess and 510d interval one, the side distance of described first dielectric layer 510.The lower surface 510b of described first dielectric layer 510 extends to the described recess surface 508d of described second pin 508 from the side of described first dielectric layer 510, whereby, when utilizing plated film mode to form conductive layer 516, described conductive layer 516 just not easily contacts with described second pin 508, causes electrical short.
Although this case is, in above-mentioned embodiment and the graphic mode of providing, the present invention is described, according to the present invention, described embodiment and graphic described in each technical characteristic can combine mutually.
Fig. 6 A to 6I illustrates an embodiment of the method according to component-embedded encapsulating structure of the present invention.The manufacture method below described also is used on substrate and forms multiple encapsulating structure.
With reference to figure 6A, provide underlying structure 600.In one embodiment, described underlying structure 500 comprises at least one nude film bearing part 607, at least one first pin portions 601 and at least one second pin portions 609.Each nude film bearing part 607 is arranged in pairs or groups at least one first pin portions 601 and at least one second pin portions 609, and described nude film bearing part 607, described first pin portions 601 and described second pin portions 609 define opening 605.
With reference to figure 6B, arrange that nude film 602 is on described nude film bearing part 607.Described nude film 602 is attached on described nude film bearing part 607 by viscous layer 618.Described nude film 602 can have connection pad 603.
With reference to figure 6C, the first dielectric layer 610 is arranged on described substrat structure 600, and covers described nude film 602, described first pin portions 601 and described second pin portions 609.Described first dielectric layer 610 is openings 605 that essence is inserted described nude film bearing part 607 and defined with described first pin portions 601 and described second pin portions 609.In one embodiment, described first dielectric layer 610 can utilize laminar manner to be arranged on described substrat structure 600.In another embodiment, described first dielectric layer 610 can utilize any coating technique to be formed, as printing, rotary coating or spraying.In one embodiment, described first dielectric layer 610 is formed from prepreg material.
With reference to figure 6D, described first dielectric layer 610 forms the first through hole 619, exposes the connection pad 603 of the described nude film 602 of part; And form the second through hole 621, expose described second pin 609 of part, as the part be electrically connected.Described through hole 619 and 621 can profit be formed in various manners.For example, described through hole 619 and 621 can utilize photoetching/etching, laser drill, machine drilling mode or other feasible mode to be formed.In an embodiment, described through hole 619 and 621 utilizes laser drill mode to be formed.Described through hole 619 and 621 can be arbitrary shape, such as, include but not limited to column or non-columnar.Column is such as cylindric, oval column, square column or rectangular cylindrical.Non-columnar is such as circular cone, funnel or taper.The side boundaries of described through hole 619 and 621 also can be curve-like or be given shape substantially.
With reference to figure 6E, described through hole 619 and 621 can utilize electric conducting material to insert to form electrical interconnections 620 and 622 respectively.Described electrical interconnections 620 and 622 can utilize any coating technique to be formed, as electroless plating and/or plating.As shown in the figure, conductive layer 613 is formed on the surface of described first dielectric layer 610.Described conductive layer 613 can utilize any coating technique to be formed, as electroless plating and/or plating.In one embodiment, described electrical interconnections 620 and 622 and described conductive layer 613 are formed in same step.
With reference to figure 6F, conductive layer 613 described in patterning, to form described patterned conductive layer 612.Described patterned conductive layer 612 can comprise at least one connection pad and at least one conductive trace, and it can be formed in fact in same step.In one embodiment, described patterning process is reached by photoetching and engraving method.In another embodiment, described patterned conductive layer 612 can selective electroplating mode be formed with described electrical interconnections 620 and 622.In addition, as shown in the figure, patterning is carried out at the back side for described substrat structure 600, is separated (isolated) to make described nude film bearing 604, described first pin 606 and described second pin 608.Described patterning step exposes the surface of at least part of described first pin 606, described nude film bearing 604 and described second pin 608, at described first dielectric layer 610 of exposed portion, correspondence described opening 605 place, and define the opening 636 between described first pin 606, described nude film bearing 604 and described second pin 608.In one embodiment, the step of carrying out patterning for the back side of described substrat structure 600 can form recess on the surface of described second pin 608.Described back etched step is through controlling, to make predetermined formation side 610d (see Fig. 6 I) interval one distance of the surface of described recess and described first dielectric layer 610, the described distance at the surface of described recess and predetermined formation side 610d (see Fig. 6 I) the institute interval of described first dielectric layer 610 need be enough wide, follow-up when utilizing plated film mode to form conductive layer 616 (see Fig. 6 I) to make, described conductive layer 616 (see Fig. 6 I) only can be formed at most on the lower surface 610b of described first dielectric layer 610 of part, and cannot contact with described second pin 608.
With reference to figure 6G, the second dielectric layer 614 is arranged on described first dielectric layer 610, covers described patterned conductive layer 612, and inserts the opening that described patterned conductive layer 612 defines.Described second dielectric layer 614 can utilize the same mode of formation first dielectric layer to be formed.As shown in the figure, described second dielectric layer 614 can have at least one opening 614c, to expose the part of described patterned conductive layer 612 for being electrically connected.The described part appeared can be connection pad.In addition, as shown in the figure, the 3rd dielectric layer 628 is placed on the back side of described substrat structure 600, inserts the opening 636 defined between described first pin 606, described nude film bearing 604 and described second pin 608.Described 3rd dielectric layer 628 can have opening 628c, and the back side of described second pin 608 of described first pin 606 of exposed portion, the described nude film bearing 604 of part and part, to connect as exposed electrical.Described second dielectric layer 614 and described 3rd dielectric layer 628 can be welding resisting layer.Described second dielectric layer 614 and described 3rd dielectric layer 628 can be made up of the material of photosensitive dry film or other kind of patternable, such as, can be but be not limited to polyimides.Described opening 614c and 628c can utilize photoetching/etching, laser drill, machine drilling mode or other feasible mode to be formed.In one embodiment, described opening 614c and 628c is formed in laser drill mode.In another embodiment, described opening 614c and 628c is formed in photoetching (photolithography) mode.
With reference to figure 6H, electric conducting material is inserted the opening exposing patterned conductive layer 612 that described second dielectric layer 614 defines to form electrical interconnections 630.Described electrical interconnections 630 can utilize any technology to be formed, as scolding tin.Described electrical interconnections 630 can be block tin or soldered ball 630, is electrically connected with an element (can be initiatively or passive device) 632.Then, as shown in the figure, the 3rd dielectric layer 634 (can be encapsulating material) is placed on described second dielectric layer 614.Coated described second dielectric layer 614 of described 3rd dielectric layer 634 and described element 632.
With reference to figure 6I, be first first carry out cutting single stage for the encapsulating structure of Fig. 6 H, with by independent individually for the multiple semiconductor package parts in described encapsulating structure.Carry out described cutting step, expose with the lateral surface 606c of the first pin 606 making other semiconductor package part, the lateral surface 610c of wherein said first dielectric layer 610 flushes with the lateral surface 606c of described first pin 606; And lateral surface 608c interval one distance of the lateral surface 610d of wherein said first dielectric layer 610 and described second pin 608.Then, settle metal level 616 in the upper surface 614a of described second dielectric layer 614 and side thereof, the side of described first dielectric layer 610, the side 606c of described first pin 606, and the side 610d that described first dielectric layer 610 does not contact with the side 608c of described second pin 608.Described metal level 616 conformal can be coated with (conformally coating) on described individual semiconductor package part.Described metal level 616 can utilize coating, spraying, plasma sputtering or other feasible mode to be placed on other semiconductor package part.
Above-described embodiment is only effect that principle of the present invention is described, and is not used to limit the present invention.Therefore, those skilled in the art modifies to above-described embodiment and changes still not de-spirit of the present invention.
The specification of this case and graphic only for explaining the present invention, is not intended to limit interest field of the present invention; In addition, graphic middle the illustrated each technical characteristic of this case and element are only for making the technical staff in field of the present invention more understand the present invention, its size illustrated and corresponding closing thereof may not represent its actual relationship, the technical staff in field of the present invention, when the claims that can provide according to this case, invention description and graphic, understand the invention scope that this case claims are contained, interest field of the present invention is when being as the criterion with this case claims, and the technical staff containing field of the present invention is from the specification of this case and graphic the scope that can rationally know by inference.
Claims (14)
1. a component-embedded encapsulating structure, it comprises:
Nude film bearing;
Nude film, is placed in described nude film bearing;
First pin and the second pin, be placed in around described nude film bearing;
First dielectric layer, cover described nude film, described nude film bearing, described first pin and described second pin, and described first dielectric layer has the first through hole, expose at least part of described nude film, and second through hole, expose at least part of described second pin, a side of wherein said first dielectric substance flushes in fact with a side of described first pin;
Patterned conductive layer, is placed on the upper surface of described first dielectric layer, and wherein said patterned conductive layer is electrically connected by described first through hole and described nude film, and described patterned conductive layer is electrically connected by described second through hole and described second pin;
Second dielectric layer, is placed on described first dielectric layer, and described second dielectric layer covers described patterned conductive layer; And
Conductive layer, the upper surface of coated described second dielectric layer and side, and the described side of described first dielectric layer, and directly contact with the described side of described first pin.
2. component-embedded encapsulating structure according to claim 1, wherein said first dielectric layer comprises reinforcing material further.
3. component-embedded encapsulating structure according to claim 2, wherein said reinforcing material is glass fabric.
4. component-embedded encapsulating structure according to claim 1, wherein said first pin is used for ground connection.
5. component-embedded encapsulating structure according to claim 1, wherein said second pin comprises the Part I being embedded in the first dielectric layer and the Part II given prominence to outside the first dielectric layer further.
6. component-embedded encapsulating structure according to claim 5, the side of wherein said Part II has recess.
7. component-embedded encapsulating structure according to claim 5, wherein said second pin comprises the intersection that summit is positioned at described Part I and described Part II further.
8. component-embedded encapsulating structure according to claim 1, it comprises the 3rd dielectric layer further and is placed on the lower surface of described first dielectric layer, has the opening exposing at least part of described nude film bearing, at least partly described first pin and described second pin at least partly.
9. a semiconductor device, it comprises:
Nude film bearing;
Nude film, is placed in described nude film bearing;
First pin and the second pin, be placed in around described nude film bearing;
First dielectric layer, cover described nude film, described nude film bearing, described first pin and described second pin, and described first dielectric layer has the first through hole, expose at least part of described nude film, and second through hole, expose at least part of described second pin, a side of wherein said first dielectric substance flushes in fact with a side of described first pin;
Patterned conductive layer, is placed on the upper surface of described first dielectric layer, and wherein said patterned conductive layer is electrically connected by described first through hole and described nude film, and described patterned conductive layer is electrically connected by described second through hole and described second pin;
Second dielectric layer, is placed on described first dielectric layer, and described second dielectric layer covers described patterned conductive layer, and has third through-hole, the described patterned conductive layer of exposed portion;
Element is electrically connected by described third through-hole and described patterned conductive layer;
Coated described second dielectric layer of 3rd dielectric layer and described element; And
Conductive layer, conformal is coated on surface and side, a side of described second dielectric layer and the described side of described first dielectric layer of described 3rd dielectric layer, and directly contacts with the described side of described first pin.
10. a semiconductor device, it comprises:
Conductive frame, comprises nude film bearing, and the first pin and the second pin are placed in around described nude film bearing;
Nude film, is placed in described nude film bearing;
First dielectric layer, covers described nude film and described conductive frame, and the side of wherein said first dielectric layer is in the face of a side of described first pin together;
First conductive through hole, is placed in described first dielectric layer, is electrically connected with described nude film;
Second conductive through hole, is placed in described first dielectric layer, is electrically connected with described second pin;
Patterned conductive layer, is placed on the upper surface of described first dielectric layer, is electrically connected described first conductive through hole and described second conductive through hole;
Second dielectric layer, covers on described first dielectric layer and described patterned conductive layer; And
Metal level, conformal is coated on the upper surface of described second dielectric layer and the side of side and described first dielectric layer, and directly contacts with the side of described first pin.
The manufacture method of 11. 1 kinds of component-embedded encapsulating structures, comprises:
There is provided underlying structure, described underlying structure comprises at least one nude film bearing, at least one first pin and at least one second pin;
Arrange that nude film is in described nude film bearing;
Arrange that the first dielectric layer is on described substrat structure, described first dielectric layer covers described nude film, described nude film bearing, described first pin and described second pin;
Form the first through hole at described first dielectric layer, expose the described nude film of part;
Form the second through hole at described first dielectric layer, expose described second pin of part;
With selective electroplating mode formed patterned conductive layer on described first dielectric layer, described first opening and described second opening;
Arrange that the second dielectric layer covers described first dielectric layer and described patterned conductive layer;
Etching described underlying structure makes described nude film bearing, described first pin and described second pin be separated;
Carry out cutting single stage, described in cut single stage and expose a side of described first dielectric layer and a side of described first pin, the described side of wherein said first dielectric layer flushes with the described side of described first pin; And
Metal level is settled to cover the upper surface of described second dielectric layer and the described side of described first dielectric layer, and the described side of described first pin.
12. methods according to claim 12, it settles described metal level in plasma sputtering mode.
13. methods according to claim 12, it forms described first opening and described second opening in laser drill mode.
14. methods according to claim 12, it forms described first opening and described second opening with photolithographicallpatterned.
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| CN201711016136.1A CN108022889B (en) | 2014-08-26 | 2014-08-26 | Element embedded packaging structure, semiconductor device and manufacturing method thereof |
| CN201410424515.4A CN104319265B (en) | 2014-08-26 | 2014-08-26 | Component-embedded encapsulating structure, its semiconductor device and its manufacture method |
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| CN201410424515.4A CN104319265B (en) | 2014-08-26 | 2014-08-26 | Component-embedded encapsulating structure, its semiconductor device and its manufacture method |
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| CN105489593A (en) * | 2015-12-24 | 2016-04-13 | 合肥祖安投资合伙企业(有限合伙) | Electromagnetic shield packaging assembly and manufacturing method therefor |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108022889B (en) | 2021-05-07 |
| CN104319265B (en) | 2017-11-14 |
| CN108022889A (en) | 2018-05-11 |
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