CN104301035A - Detection device for testing SFP - Google Patents
Detection device for testing SFP Download PDFInfo
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- CN104301035A CN104301035A CN201410554644.5A CN201410554644A CN104301035A CN 104301035 A CN104301035 A CN 104301035A CN 201410554644 A CN201410554644 A CN 201410554644A CN 104301035 A CN104301035 A CN 104301035A
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Abstract
A detection device for testing SFP is used for detecting the error rate of the SFP through an error code detection module and a code type generating module and through the cooperation of a clock control module and a main control module, and optical power is detected through a photovoltaic conversion module and an analog-digital conversion module and through the cooperation of the main control module. Address data in the SFP are read through the main control module to obtain digital diagnosis data. Thus, the SFP error code detecting, digital diagnosis data obtaining and optical power detecting are achieved. Furthermore, due to the fact that the error code detection module, the code type generating module, the clock control module, the main control module, the photovoltaic conversion module and the analog-digital conversion module are integrated, the detection device for testing the SFP is capable of conducting detection to achieve multiple function tests of the SFP and convenient for a user to carry.
Description
Technical field
The present invention relates to SFP checkout gear, particularly relating to a kind of portable, multi-functional checkout gear for testing SFP.
Background technology
SFP optical module (small form pluggable, small form factor pluggable optical module) need to test the error rate, DDM (digital supervision diagnosis) information and some other important photoelectric parameter, as operating current, luminous power etc. in production test and on-the-spot application.And existing test structure needs the equipment of several difference in functionalitys to build, comprise DC power supply, test board, Error Detector, light power meter, universal instrument, PC etc., these equipment not only cost intensive and take up room large, operation uses also inconvenient.Particularly not easily be carried to engineering site to use.
Summary of the invention
Based on this, be necessary a kind of portable, multi-functional checkout gear for testing SFP.
For testing a checkout gear of SFP, comprise error code detection module, pattern generation module, clock control module, main control module, photoelectric conversion module and analog-to-digital conversion module;
Described photoelectric conversion module connects described analog-to-digital conversion module, described main control module connects described clock control module, described analog-to-digital conversion module and described error code detection module simultaneously, described error code detection module also with described clock detection module and described pattern generation model calling;
The clock signal that described pattern generation module is used for sending according to described clock control module generates pseudo-random binary sequence, and sends to SFP; Described pseudo-random binary sequence sends to described error code detection module via after the attenuation of SFP; Described error code detection module is used for judging that whether the error rate of described SFP is qualified according to via the pseudo-random binary sequence after described SFP decay;
The light signal that described photoelectric conversion module is used for being received converts current signal to, export to described analog-to-digital conversion module, described analog-to-digital conversion module exports to described main control module after the analog signal of reception is converted to digital signal, and described main control module is used for the size calculating luminous power according to the digital signal received;
Described main control module is also for connecting described SFP by I2C bus, and described main control module is for the address date that reads in described SFP and be reduced to digital diagnostic data;
Described error code detection module, described pattern generation module, described clock control module, described main control module, described photoelectric conversion module and described analog-to-digital conversion module integration packaging are integrated.
Wherein in an embodiment, also comprise the first amplifier connecting described photoelectric conversion module and described analog-to-digital conversion module respectively, the current signal that described first amplifier exports for amplifying described photoelectric conversion module, and the current signal after amplifying is exported to described analog-to-digital conversion module.
Wherein in an embodiment, also comprise the second amplifier connecting described SFP and described main control module respectively; Pressure drop after amplifying for the pressure drop that described SFP produces being amplified, and is exported to described main control module by described second amplifier, and described main control module is for calculating the electric current on described SFP according to the pressure drop signal received.
Wherein in an embodiment, described photoelectric conversion module comprises photodiode.
Wherein in an embodiment, described error code detection module and described pattern generation module are chip VSC8228; Described chip VSC8228 is used for pattern and occurs and Error detection.
Wherein in an embodiment, described clock control module comprises clock chip SYS58029U.
Wherein in an embodiment, described main control module comprises chip C8051F380.
Wherein in an embodiment, described analog-to-digital conversion module comprises chip D7091R.
Wherein in an embodiment, also comprise power transfer module; It is described SFP that described power transfer module is used for direct voltage, the operating voltage of described error code detection module, described pattern generation module, described clock control module, described main control module, described photoelectric conversion module and described analog-to-digital conversion module.
The above-mentioned checkout gear for testing SFP coordinates clock control module and main control module to detect the error rate of SFP by error code detection module and pattern generation module; Main control module is coordinated to detect luminous power by photoelectric conversion module and analog-to-digital conversion module.The address date read in SFP by main control module obtains digital diagnostic data.Thus realize the Error detection of SFP, digital diagnostic data obtains and the detection of luminous power.And error code detection module, pattern generation module, clock control module, main control module, photoelectric conversion module and analog-to-digital conversion module become one, therefore, checkout gear for testing SFP can not only detect the multiple functional tests realizing SFP, and facilitates user to carry.
Accompanying drawing explanation
Fig. 1 is the module map of the checkout gear for testing SFP;
Fig. 2 is the schematic diagram of the checkout gear for testing SFP.
Embodiment
As shown in Figure 1, be the module map of the checkout gear for testing SFP.
For testing a checkout gear of SFP, comprise error code detection module 106, pattern generation module 105, clock control module 104, main control module 101, photoelectric conversion module 102 and analog-to-digital conversion module 103.
Described photoelectric conversion module 102 connects described analog-to-digital conversion module 103, described main control module 101 connects described clock control module 104, described analog-to-digital conversion module 103 and described error code detection module 106 simultaneously, and described error code detection module 106 is also connected with described clock detection module 104 and described pattern generation module 105.
Described pattern generation module 105 generates pseudo-random binary sequence for the clock signal sent according to described clock control module 104, and sends to SFP; Described pseudo-random binary sequence is via sending to described error code detection module 106 after the attenuation of SFP; According to via the pseudo-random binary sequence after described SFP decay, described error code detection module 106 is for judging that whether the error rate of described SFP is qualified.
Described photoelectric conversion module 102 converts current signal to for the light signal received, export to described analog-to-digital conversion module 103, described analog-to-digital conversion module 103 exports to described main control module 101 after the analog signal of reception is converted to digital signal, and described main control module 101 is for calculating the size of luminous power according to the digital signal received.
Described main control module 101 is also for connecting described SFP by I2C bus, and described main control module 101 is for the address date that reads in described SFP and be reduced to digital diagnostic data.
Described error code detection module 106, described pattern generation module 105, described clock control module 104, described main control module 101, described photoelectric conversion module 102 and described analog-to-digital conversion module 103 integration packaging are integrated.
Checkout gear for testing SFP also comprises the first amplifier connecting described photoelectric conversion module 102 and described analog-to-digital conversion module 103 respectively, the current signal that described first amplifier exports for amplifying described photoelectric conversion module 102, and the current signal after amplifying is exported to described analog-to-digital conversion module 103.
Checkout gear for testing SFP also comprises the second amplifier connecting described SFP and described main control module 101 respectively; Pressure drop after amplifying for the pressure drop that described SFP produces being amplified, and is exported to described main control module 101 by described second amplifier, and described main control module 101 is for calculating the electric current on described SFP according to the pressure drop signal received.
The light signal switching current signal of photoelectric conversion module 102 for receiving; General employing photodiode PD completes the function of photoelectric conversion module 102 as optical sensor.The current signal that photoelectric conversion module 102 is changed is suitable smaller, is directly transferred to analog-to-digital conversion module 103 and can causes reading, therefore, amplifier generally can be adopted to amplify current signal.
Concrete, adopt the first amplifier simultaneously connecting photoelectric conversion module 102 and analog-to-digital conversion module 103 to amplify.First amplifier is the controllable amplifier on gain three rank.
The current signal amplified via the first amplifier enters after analog-to-digital conversion module 103 is converted to digital signal, finally carries out power calculation by main control module 101, thus draws the luminous power relative loss factor of SFP.
After user selects the speed needing to test, main control module 101 controls clock control module 104 and exports corresponding clock signal to error code generation module 105, error code generation module 105 produces the pseudo-random binary sequence of targeted rate, output to the TX interface of SFP, the light path of SFP is outputted to after being converted to light signal, after the attenuation of SFP, get back to the RX interface of SFP, be again reduced to pseudo-random binary sequence, and output to error code detection module 106; According to the pseudo-random binary sequence received, error code detection module 106 judges that whether the error rate of SFP is qualified.Particularly, the error rate=error code quantity/total code amount.
I2C (Inter-Integrated Circuit) bus is for connecting microcontroller and ancillary equipment thereof.
Main control module 101 can read the address date in SFP, and address date is reduced to digital diagnostic data after directly connecting SFP by I2C bus, thus realizes DDM (digital supervision diagnosis) the information inspection function of SFP.
The ohmically pressure drop of the second amplifier for sampling between SFP and supply current, and export to main control module 101 after the pressure drop sampled being amplified, main control module 101 receives the pressure drop after amplifying and converts corresponding current signal to, thus the operating current of SFP can be calculated, namely detect the operating current of SFP.
Incorporated by reference to Fig. 2.
Photoelectric conversion module 102 comprises photodiode.
Error code detection module 106 and described pattern generation module 105 are chip VSC8228; Described chip VSC8228 is used for pattern and occurs and Error detection.
Clock control module 104 comprises clock chip SYS58029U.
Main control module 101 comprises chip C8051F380.
Analog-to-digital conversion module 103 comprises chip D7091R.
Chip VSC8228, chip VSC8228, clock chip SYS58029U, chip C8051F380, chip D7091R is integrated and coordinate the periphery electronic component of each chip, thus the Error detection of SFP can be completed, luminous power detects, current detecting and DDM information inspection function.Carry out integrated owing to adopting said chip, thus the equipment making the volume relative distribution of the checkout gear for testing SFP realize each Function detection is largely much smaller, therefore, the checkout gear for testing SFP facilitates user to carry, and is applicable to Site Detection SFP.
Checkout gear for testing SFP also comprises power transfer module; It is described SFP that described power transfer module is used for direct voltage, the operating voltage of described error code detection module 106, described pattern generation module 105, described clock control module 104, described main control module 101, described photoelectric conversion module 102 and described analog-to-digital conversion module 103.
Based on above-mentioned all embodiments, the workflow for the checkout gear testing SFP is as follows:
When user needs to carry out error rate detection, select by user the speed needing test, chip C8051F380 controls clock chip SYS58029U and exports corresponding clock signal (Q1, Q2.Q3) to chip VSC8228, the error code generating unit of chip VSC8228 generates the pseudo-random binary sequence of targeted rate, and the TX interface conversion being sent to SFP is the light path that light signal outputs to SFP; After the attenuation of SFP, get back to the RX interface of SFP, be again reduced to pseudo-random binary sequence, and the Error detection unit being sent to chip VSC8228 carries out Error detection.Judge that whether the error rate of SFP is qualified according to the formula error rate=error code quantity/total code amount.Thus the error rate realizing SFP detects.
When needs carry out luminous power detection, after being amplified by amplifier A1 after then the light signal of reception being converted to the signal of telecommunication by photodiode PD, export to chip D7091R and be converted to digital signal, calculated the size of the luminous power of SFP again by chip C8051F380, thus the luminous power completing SFP detects.
When needing the digital diagnostic information of checking SFP, because chip C8051F380 is directly connected with SFP by I2C bus, therefore, chip C8051F380 directly can read the address date of SFP, then address date is reduced into digital diagnostic data, thus realizes DDM (digital supervision diagnosis) information inspection of SFP.
When needing the operating current detecting SFP, then by the ohmically pressure drop between amplifier A2 sampling power transfer module and SFP, after the pressure drop of sampling is amplified by amplifier A2, export to chip C8051F380, pressure drop is converted to corresponding current signal numerical value by chip C8051F380, thus can obtain the operating current size of SFP.
Power transfer module is used for the direct voltage direct voltage of 5V being converted to 3.3V, 1.8V.
The above-mentioned checkout gear for testing SFP coordinates clock control module 104 and main control module 101 to detect the error rate of SFP by error code detection module 106 and pattern generation module 105; Main control module 101 is coordinated to detect luminous power by photoelectric conversion module 102 and analog-to-digital conversion module 103.The address date read in SFP by main control module 101 obtains digital diagnostic data.Thus realize the Error detection of SFP, digital diagnostic data obtains and the detection of luminous power.And error code detection module 106, pattern generation module 105, clock control module 104, main control module 101, photoelectric conversion module 102 and analog-to-digital conversion module 103 become one, therefore, checkout gear for testing SFP can not only detect the multiple functional tests realizing SFP, and facilitates user to carry.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (9)
1. for testing a checkout gear of SFP, it is characterized in that, comprising error code detection module, pattern generation module, clock control module, main control module, photoelectric conversion module and analog-to-digital conversion module;
Described photoelectric conversion module connects described analog-to-digital conversion module, described main control module connects described clock control module, described analog-to-digital conversion module and described error code detection module simultaneously, described error code detection module also with described clock detection module and described pattern generation model calling;
The clock signal that described pattern generation module is used for sending according to described clock control module generates pseudo-random binary sequence, and sends to SFP; Described pseudo-random binary sequence sends to described error code detection module via after the attenuation of SFP; Described error code detection module is used for judging that whether the error rate of described SFP is qualified according to via the pseudo-random binary sequence after described SFP decay;
The light signal that described photoelectric conversion module is used for being received converts current signal to, export to described analog-to-digital conversion module, described analog-to-digital conversion module exports to described main control module after the analog signal of reception is converted to digital signal, and described main control module is used for the size calculating luminous power according to the digital signal received;
Described main control module is also for connecting described SFP by I2C bus, and described main control module is for the address date that reads in described SFP and be reduced to digital diagnostic data;
Described error code detection module, described pattern generation module, described clock control module, described main control module, described photoelectric conversion module and described analog-to-digital conversion module integration packaging are integrated.
2. the checkout gear for testing SFP according to claim 1, it is characterized in that, also comprise the first amplifier connecting described photoelectric conversion module and described analog-to-digital conversion module respectively, the current signal that described first amplifier exports for amplifying described photoelectric conversion module, and the current signal after amplifying is exported to described analog-to-digital conversion module.
3. the checkout gear for testing SFP according to claim 1, is characterized in that, also comprises the second amplifier connecting described SFP and described main control module respectively; Pressure drop after amplifying for the pressure drop that described SFP produces being amplified, and is exported to described main control module by described second amplifier, and described main control module is for calculating the electric current on described SFP according to the pressure drop signal received.
4. the checkout gear for testing SFP according to claim 1, is characterized in that, described photoelectric conversion module comprises photodiode.
5. the checkout gear for testing SFP according to claim 1, is characterized in that, described error code detection module and described pattern generation module are chip VSC8228; Described chip VSC8228 is used for pattern and occurs and Error detection.
6. the checkout gear for testing SFP according to claim 1, is characterized in that, described clock control module comprises clock chip SYS58029U.
7. the checkout gear for testing SFP according to claim 1, is characterized in that, described main control module comprises chip C8051F380.
8. the checkout gear for testing SFP according to claim 1, is characterized in that, described analog-to-digital conversion module comprises chip D7091R.
9. the checkout gear for testing SFP according to claim 1, is characterized in that, also comprise power transfer module; It is described SFP that described power transfer module is used for direct voltage, the operating voltage of described error code detection module, described pattern generation module, described clock control module, described main control module, described photoelectric conversion module and described analog-to-digital conversion module.
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| CN201410554644.5A CN104301035B (en) | 2014-10-17 | 2014-10-17 | For testing the detection means of SFP |
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| CN201410554644.5A CN104301035B (en) | 2014-10-17 | 2014-10-17 | For testing the detection means of SFP |
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| CN104301035B CN104301035B (en) | 2017-03-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016177088A1 (en) * | 2015-07-03 | 2016-11-10 | 中兴通讯股份有限公司 | Method and apparatus for detecting signal |
| CN106411398A (en) * | 2016-05-23 | 2017-02-15 | 深圳市鑫杰讯科技有限公司 | Optical module detector |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2684471Y (en) * | 2004-03-15 | 2005-03-09 | 北京格林威尔科技发展有限公司 | Optical transmitter and receiver with embedded error code testing function |
| CN100409624C (en) * | 2005-04-14 | 2008-08-06 | 武汉电信器件有限公司 | 155 M bit error code analysis tester based on field programmable gate array |
| CN203340079U (en) * | 2013-05-30 | 2013-12-11 | 武汉电信器件有限公司 | Electrical interface code error tester suitable for optical module with transmission rate of 10 G |
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2014
- 2014-10-17 CN CN201410554644.5A patent/CN104301035B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016177088A1 (en) * | 2015-07-03 | 2016-11-10 | 中兴通讯股份有限公司 | Method and apparatus for detecting signal |
| CN106411398A (en) * | 2016-05-23 | 2017-02-15 | 深圳市鑫杰讯科技有限公司 | Optical module detector |
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