CN104300981B - At a high speed, high precision image signal analog to digital conversion circuit - Google Patents
At a high speed, high precision image signal analog to digital conversion circuit Download PDFInfo
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- CN104300981B CN104300981B CN201410518090.3A CN201410518090A CN104300981B CN 104300981 B CN104300981 B CN 104300981B CN 201410518090 A CN201410518090 A CN 201410518090A CN 104300981 B CN104300981 B CN 104300981B
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Abstract
The invention discloses a kind of high speed, high precision image signal analog to digital conversion circuit, it includes multi-stage pipeline circuit, time-delay alignment register array, digital calibration circuit and clock generator, and sampling and keep module, sub- ADC module, sub- DAC module, subtraction circuit and surplus amplification module are further included in each level production line circuit.The present invention can effectively control analog-to-digital conversion error, improve precision and can realize the analog-to-digital conversion of high speed.
Description
Technical field
The present invention relates to a kind of analog to digital conversion circuit, more particularly to a kind of high speed, high precision image signal analog-to-digital conversion electricity
Road.
Background technology
Core devices of the analog-digital converter as digital world user simulated world in contemporary electronic systems, it is defeated in multichannel
Enter, export radio, the cellular communication infrastructure device of 3G and 4G multi-standards, does the precision instrument of resolution ratio and your student as handling capacity
And the field such as some portable high-definition video player, Medical Devices has a wide range of applications.
The requirement of the high-end application field such as wireless communication, digital household appliances is told, high accuracy, Larger Dynamic scope, low-power consumption, to height
The demand of performance A/D converter is growing, and the high speed development of digital technology, then proposes higher to A/D converter performance
Requirement, its integrated level of ADC is with complexity just as system improves the continuous improvement that accuracy and speed requires；Face technique
Size constantly reduces and the form that constantly reduces of supply voltage, how while ADC performances are ensured to reduce its power consumption, reduction
Various factors harmful effect caused by data conversion just becomes one of major subjects that ADC is related to.
Production by assembly line is current high speed, the mainstream structure of high position ADC, just advises power consumption in its system level design stage
Draw and non-ideal effects accounted for the problems such as evading category be whole system design one ring of key, current IC suppliers
The input to pipeline ADC is being continued to increase, is being improved, optimizes from design and processes etc., its performance is also continuously improved,
In terms of high-performance pipeline ADC, the independent data converters IC suppliers as several former in the world（As ADI, TI,
Maxim）, the product of these companies represents the development level of current flowing water ADC products.
At present, communicate etc. in the modernization of national defense and civil electronic and be all badly in need of substantial amounts of High Performance ADC, and China
The research level and technical merit of High Performance ADC are comparatively also relatively backward, some high-end ADC chips are still
So by external import, we should seize the opportunity, and quick raising autonomous Design is horizontal, shortens and external gap.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide one kind effectively to control analog-to-digital conversion to miss
Difference, improves precision and can realize the high speed of the analog-to-digital conversion of high speed, high precision image signal analog to digital conversion circuit.
The purpose of the present invention is what is be achieved through the following technical solutions：
At a high speed, high precision image signal analog to digital conversion circuit, it includes multi-stage pipeline circuit, delay alignment register battle array
Row and digital calibration circuit, each level production line circuit include sampling and keep module, sub- ADC module, sub- DAC module, subtraction
Circuit and surplus amplification module；The first flow line circuit of analog input signal, first adopts signal in sampling and keep module
Sample is kept, and inputs a signal into sub- ADC module afterwards and signal is quantified, and output digit signals are directed at register battle array to delay
Row and sub- DAC module, sub- DAC module are output to subtraction circuit after converting a signal into analog signal, and analog signal is protected with sampling
Signal subtraction after holding, then signal amplification certain multiple is output to next flow line circuit through surplus amplification module；Per level-one
The output of flow line circuit is connected with time-delay alignment register array, time-delay alignment register array output and digital calibration circuit
Connection, output after signal is calibrated.
Present invention additionally comprises a clock generator, the output of clock generator respectively with time-delay alignment register array and
Digital calibration circuit connects..
The beneficial effects of the invention are as follows：Sampling and keep module is all provided with each assembly line in the present invention, can be fine
The each assembly line of control error and ensure sampling rate, while clock signal is input to delay alignment register at the same time
Array and digital calibration circuit, without being disposed in each flow line circuit, can improve the precision of analog-to-digital conversion, realize high
Fast, high-precision analog-to-digital conversion.
Brief description of the drawings
Fig. 1 is the circuit diagram of the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in Figure 1, high speed, high precision image signal analog to digital conversion circuit, it includes multi-stage pipeline circuit, delay pair
Quasi- register array, digital calibration circuit and clock generator, further include sampling and keep module, son in each level production line circuit
ADC module, sub- DAC module, subtraction circuit and surplus amplification module.
Analog input signal is input to each flow line circuit, carries out sampling guarantor to signal in sampling and keep module first
Hold, input a signal into sub- ADC module afterwards and signal is quantified, output digit signals to time-delay alignment register array and
Sub- DAC module, sub- DAC module is output to subtraction circuit after converting a signal into analog signal, after analog signal is kept with sampling
Signal subtraction, then through surplus amplification module by signal amplification certain multiple be output to next pipelining-stage；Clock generator is at the same time
Output clock signal outputs signals to number to time-delay alignment register array and digital calibration circuit, time-delay alignment register array
Word calibrates circuit, output after signal is calibrated.
Claims (1)
1. at a high speed, high precision image signal analog to digital conversion circuit, it is characterised in that：It includes multi-stage pipeline circuit, delay pair
Quasi- register array and digital calibration circuit, each level production line circuit include sampling and keep module, sub- ADC module, sub- DAC
Module, subtraction circuit and surplus amplification module；The first flow line circuit of analog input signal, first in sampling and keep module to letter
Number sampling holding is carried out, input a signal into sub- ADC module afterwards and signal is quantified, output digit signals are aligned to delay
Register array and sub- DAC module, sub- DAC module are output to subtraction circuit, analog signal after converting a signal into analog signal
Signal subtraction after being kept with sampling, then signal amplification certain multiple is output to next assembly line electricity through surplus amplification module
Road；The output of each level production line circuit is connected with time-delay alignment register array, time-delay alignment register array output and number
Word calibration circuit connection, output after signal is calibrated；A clock generator is further included, the output of clock generator is respectively with prolonging
When alignment register array connect with digital calibration circuit, the amplification factor of the surplus amplification module is 2n, n is ADC module
With the digit of DAC module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410518090.3A CN104300981B (en) | 2014-09-30 | 2014-09-30 | At a high speed, high precision image signal analog to digital conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410518090.3A CN104300981B (en) | 2014-09-30 | 2014-09-30 | At a high speed, high precision image signal analog to digital conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104300981A CN104300981A (en) | 2015-01-21 |
| CN104300981B true CN104300981B (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410518090.3A Active CN104300981B (en) | 2014-09-30 | 2014-09-30 | At a high speed, high precision image signal analog to digital conversion circuit |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771460B (en) * | 2017-01-16 | 2023-03-31 | 佛山科学技术学院 | High-resolution measurement conversion circuit |
| CN111740742A (en) * | 2020-05-29 | 2020-10-02 | 红鼎互联(广州)信息科技有限公司 | High-speed and high-precision image signal analog-to-digital conversion circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025373A (en) * | 2009-09-16 | 2011-04-20 | 复旦大学 | Digital background calibration circuit |
| CN201957001U (en) * | 2011-02-16 | 2011-08-31 | 东南大学 | Pipeline analog-to-digital converter capable of carrying out background digital calibration |
| CN102177657A (en) * | 2008-08-12 | 2011-09-07 | 美国亚德诺半导体公司 | Correlation-based background calibration of pipelined converters with reduced power penalty |
| CN103392297A (en) * | 2011-02-22 | 2013-11-13 | 德克萨斯仪器股份有限公司 | Pipelined ADC inter-stage error calibration |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204131502U (en) * | 2014-09-30 | 2015-01-28 | 成都市晶林科技有限公司 | At a high speed, high precision image signal analog to digital conversion circuit |
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- 2014-09-30 CN CN201410518090.3A patent/CN104300981B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102177657A (en) * | 2008-08-12 | 2011-09-07 | 美国亚德诺半导体公司 | Correlation-based background calibration of pipelined converters with reduced power penalty |
| CN102025373A (en) * | 2009-09-16 | 2011-04-20 | 复旦大学 | Digital background calibration circuit |
| CN201957001U (en) * | 2011-02-16 | 2011-08-31 | 东南大学 | Pipeline analog-to-digital converter capable of carrying out background digital calibration |
| CN103392297A (en) * | 2011-02-22 | 2013-11-13 | 德克萨斯仪器股份有限公司 | Pipelined ADC inter-stage error calibration |
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| CN104300981A (en) | 2015-01-21 |
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