CN104300931A - Bandwidth-adjustable passive multiphase filter circuit - Google Patents
Bandwidth-adjustable passive multiphase filter circuit Download PDFInfo
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- CN104300931A CN104300931A CN201310299086.8A CN201310299086A CN104300931A CN 104300931 A CN104300931 A CN 104300931A CN 201310299086 A CN201310299086 A CN 201310299086A CN 104300931 A CN104300931 A CN 104300931A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/18—Networks for phase shifting
- H03H7/20—Two-port phase shifters providing an adjustable phase shift
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
- H03H11/20—Two-port phase shifters providing an adjustable phase shift
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
- H03H11/22—Networks for phase shifting providing two or more phase shifted output signals, e.g. n-phase output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/18—Networks for phase shifting
- H03H7/21—Networks for phase shifting providing two or more phase shifted output signals, e.g. n-phase output
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Abstract
The invention discloses a bandwidth-adjustable passive multiphase filter circuit. The bandwidth-adjustable passive multiphase filter circuit comprises a first-order filter, a second-order filter and a third-order filter which are connected in sequence, wherein the three filters are combined into a three-order passive multiphase filter. According to the bandwidth-adjustable passive multiphase filter circuit, four paths of orthogonal differential signals are received through four ports, namely, an in-phase forward input end, an orthogonal forward input end, an in-phase backward input end and an orthogonal backward input end; output ports comprise an in-phase forward output end, an orthogonal forward output end, an in-phase backward output end and an orthogonal backward output end; and the turn-on resistance of an MOS (Metal Oxide Semiconductor) transistor can be changed by adjusting a first bias voltage, a second bias voltage and a third bias voltage, so that the bandwidth of the passive multiphase filter is changed. Compared with the prior art, the bandwidth-adjustable passive multiphase filter circuit has the advantages and effects that the circuit structure is simplified, and the chip area is reduced.
Description
Technical field
The present invention relates to technical field of radio frequency integrated circuits, relate to the passive polyphase filter circuit that a kind of bandwidth is adjustable.
Background technology
Along with the development of integrated circuit technique, radio frequency receiver proposes more and more higher requirement, need radio frequency front end chip can receive the radiofrequency signal of multiple frequency, often signal bandwidth is not identical yet, so the image-rejection filter needing utilized bandwidth different for the radiofrequency signal of different frequent points.The core of image-rejection filter is passive polyphase filter, for the passive polyphase filter of the signal demand design different bandwidth of different bandwidth.
Traditional radio frequency front end chip, often integrated multiple passive polyphase filter, different according to signal bandwidth for different applied environments, select certain passive polyphase filter switched wherein to use.Because chip internal is integrated with multiple passive polyphase filter, so circuit structure is complicated, chip area is large.
Summary of the invention
The present invention is in order to solve the deficiencies in the prior art, and propose the passive polyphase filter circuit that a kind of bandwidth is adjustable, can realize the adjustment of passive polyphase filter bandwidth, circuit structure is simple, chip area is little.
Technical scheme of the present invention is: the passive polyphase filter circuit that a kind of bandwidth is adjustable, and comprise the firstorder filter, second-order filter and the 3rd rank filter that once connect, three bank of filters form the passive polyphase filter on three rank altogether.
Further improvement of the present invention is: described firstorder filter comprises: the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity; The drain electrode of described first MOS transistor is connected to the homophase forward output of firstorder filter, and the grid of described first MOS transistor is connected to the first bias voltage, and the source class of the first MOS transistor is connected to the homophase positive input of firstorder filter; The drain electrode of described second MOS transistor is connected to the orthogonal forward output of firstorder filter, and the grid of the second MOS transistor is connected to the first bias voltage, and the source class of the second MOS transistor is connected to the orthogonal positive input of firstorder filter; The drain electrode of described 3rd MOS transistor is connected to the homophase inverse output terminal of firstorder filter, and the grid of the 3rd MOS transistor is connected to the first bias voltage, and the source class of the 3rd MOS transistor is connected to the homophase reverse input end of firstorder filter; The drain electrode of described 4th MOS transistor is connected to the orthogonal inverse output terminal of firstorder filter, and the grid of the 4th MOS transistor is connected to the first bias voltage, and the source class of the 4th MOS transistor is connected to the orthogonal reverse input end of firstorder filter; One end of described first electric capacity is connected to the homophase positive input of firstorder filter, and the other end of the first electric capacity is connected to the orthogonal forward output of firstorder filter; One end of described second electric capacity is connected to the orthogonal positive input of firstorder filter, and the other end of the second electric capacity is connected to the homophase inverse output terminal of firstorder filter; One end of described 3rd electric capacity is connected to the homophase reverse input end of firstorder filter, and the other end of the 3rd electric capacity is connected to the orthogonal inverse output terminal of firstorder filter; One end of described 4th electric capacity is connected to the orthogonal reverse input end of firstorder filter, and the other end of the 4th electric capacity is connected to the homophase forward output of firstorder filter.
Described second-order filter comprises: the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th electric capacity; The drain electrode of described 5th MOS transistor is connected to the homophase forward output of second-order filter, and the grid of the 5th MOS transistor is connected to the second bias voltage, and the source class of the 5th MOS transistor is connected to the homophase positive input of second-order filter; The drain electrode of described 6th MOS transistor is connected to the orthogonal forward output of second-order filter, and the grid of the 6th MOS transistor is connected to the second bias voltage, and the source class of the 6th MOS transistor is connected to the orthogonal positive input of second-order filter; The drain electrode of described 7th MOS transistor is connected to the homophase inverse output terminal of second-order filter, and the grid of the 7th MOS transistor is connected to the second bias voltage, and the source class of the 7th MOS transistor is connected to the homophase reverse input end of second-order filter; The drain electrode of described 8th MOS transistor is connected to the orthogonal inverse output terminal of second-order filter, and the grid of the 8th MOS transistor is connected to the second bias voltage, and the source class of the 8th MOS transistor is connected to the orthogonal reverse input end of second-order filter; One end of described 5th electric capacity is connected to the homophase positive input of second-order filter, and the other end of the 5th electric capacity is connected to the orthogonal forward output of second-order filter; One end of described 6th electric capacity is connected to the orthogonal positive input of second-order filter, and the other end of the 6th electric capacity is connected to the homophase inverse output terminal of second-order filter; One end of described 7th electric capacity is connected to the homophase reverse input end of second-order filter, and the other end of the 7th electric capacity is connected to the orthogonal inverse output terminal of second-order filter; One end of described 8th electric capacity is connected to the orthogonal reverse input end of second-order filter, and the other end of the 8th electric capacity is connected to the homophase forward output of second-order filter.
Described 3rd rank filter comprises: the 9th MOS transistor, the tenth MOS transistor, the 11 MOS transistor, the 12 MOS transistor, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity and the 12 electric capacity; The drain electrode of described 9th MOS transistor is connected to the homophase forward output of the 3rd rank filter, and the grid of the 9th MOS transistor is connected to the 3rd bias voltage, and the source class of the 9th MOS transistor is connected to the homophase positive input of the 3rd rank filter; The drain electrode of described tenth MOS transistor is connected to the orthogonal forward output of the 3rd rank filter, and the grid of the tenth MOS transistor is connected to the 3rd bias voltage, and the source class of the tenth MOS transistor is connected to the orthogonal positive input of the 3rd rank filter; The drain electrode of described 11 MOS transistor is connected to the homophase inverse output terminal of the 3rd rank filter, and the grid of the 11 MOS transistor is connected to the 3rd bias voltage, and the source class of the 11 MOS transistor is connected to the homophase reverse input end of the 3rd rank filter; The drain electrode of described 12 MOS transistor is connected to the orthogonal inverse output terminal of the 3rd rank filter, and the grid of the 12 MOS transistor is connected to the 3rd bias voltage, and the source class of the 12 MOS transistor is connected to the orthogonal reverse input end of the 3rd rank filter; One end of described 9th electric capacity is connected to the homophase positive input of the 3rd rank filter, and the other end of the 9th electric capacity is connected to the orthogonal forward output of the 3rd rank filter; One end of described tenth electric capacity is connected to the orthogonal positive input of the 3rd rank filter, and the other end of the 9th electric capacity is connected to the homophase inverse output terminal of the 3rd rank filter; One end of described 11 electric capacity is connected to the homophase reverse input end of the 3rd rank filter, and the other end of the 11 electric capacity is connected to the orthogonal inverse output terminal of the 3rd rank filter; One end of described 12 electric capacity is connected to the orthogonal reverse input end of the 3rd rank filter, and the other end of the 12 electric capacity is connected to the homophase forward output of the 3rd rank filter.
The present invention is by homophase positive input, orthogonal positive input, homophase reverse input end and orthogonal reverse input end four port accepts four road orthogonal differential signal, and output port is homophase forward output, orthogonal forward output, homophase inverse output terminal and orthogonal inverse output terminal; By regulating the first bias voltage, the second bias voltage and the 3rd bias voltage, the conducting resistance of MOS transistor can be changed, thus change the bandwidth of passive polyphase filter.
The present invention is compared with traditional prior art, and the advantage had and effect are: simplify circuit structure, reduce chip area.
Accompanying drawing explanation
Fig. 1 is the adjustable passive polyphase filter circuit theory diagrams of a kind of bandwidth of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is elaborated.
See Fig. 1, the passive polyphase filter circuit that a kind of bandwidth is adjustable comprises the passive polyphase filter that firstorder filter 100, second-order filter 200 and the 3rd rank filter 300, three bank of filters form three rank altogether.
Described firstorder filter 100 comprises: the first MOS transistor M1, the second MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4.
Wherein the drain electrode of the first MOS transistor M1 is connected to the homophase forward output net1 of firstorder filter 100, the grid of the first MOS transistor M1 is connected to the first bias voltage Vb1, and the source class of the first MOS transistor M1 is connected to the homophase positive input IP of firstorder filter 100;
The drain electrode of the second MOS transistor M2 is connected to the orthogonal forward output net2 of firstorder filter 100, the grid of the second MOS transistor M2 is connected to the first bias voltage Vb1, and the source class of the second MOS transistor M2 is connected to the orthogonal positive input QP of firstorder filter 100;
The drain electrode of the 3rd MOS transistor M3 is connected to the homophase inverse output terminal net3 of firstorder filter 100, the grid of the 3rd MOS transistor M3 is connected to the first bias voltage Vb1, and the source class of the 3rd MOS transistor M3 is connected to the homophase reverse input end IN of firstorder filter 100;
The drain electrode of the 4th MOS transistor M4 is connected to the orthogonal inverse output terminal net4 of firstorder filter 100, the grid of the 4th MOS transistor M4 is connected to the first bias voltage Vb1, and the source class of the 4th MOS transistor M4 is connected to the orthogonal reverse input end QN of firstorder filter 100;
One end of first electric capacity C1 is connected to the homophase positive input IP of firstorder filter 100, and the other end of the first electric capacity C1 is connected to the orthogonal forward output net2 of firstorder filter 100;
One end of second electric capacity C2 is connected to the orthogonal positive input QP of firstorder filter 100, and the other end of the second electric capacity C2 is connected to the homophase inverse output terminal net3 of firstorder filter 100;
One end of 3rd electric capacity C3 is connected to the homophase reverse input end IN of firstorder filter 100, and the other end of the 3rd electric capacity C3 is connected to the orthogonal inverse output terminal net4 of firstorder filter 100;
One end of 4th electric capacity C4 is connected to the orthogonal reverse input end QN of firstorder filter 100, and the other end of the 4th electric capacity C4 is connected to the homophase forward output IP of firstorder filter 100;
Described second-order filter 200 comprises: the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 8th MOS transistor M8, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7 and the 8th electric capacity C8.
Wherein the drain electrode of the 5th MOS transistor M5 is connected to the homophase forward output net5 of second-order filter 200, the grid of the 5th MOS transistor M5 is connected to the second bias voltage Vb2, and the source class of the 5th MOS transistor M5 is connected to the homophase positive input net1 of second-order filter 200;
The drain electrode of the 6th MOS transistor M6 is connected to the orthogonal forward output net6 of second-order filter 200, the grid of the 6th MOS transistor M6 is connected to the second bias voltage Vb2, and the source class of the 6th MOS transistor M6 is connected to the orthogonal positive input net2 of second-order filter 200;
The drain electrode of the 7th MOS transistor M7 is connected to the homophase inverse output terminal net7 of second-order filter 200, the grid of the 7th MOS transistor M7 is connected to the second bias voltage Vb2, and the source class of the 7th MOS transistor M7 is connected to the homophase reverse input end net3 of second-order filter 200;
The drain electrode of the 8th MOS transistor M8 is connected to the orthogonal inverse output terminal net8 of second-order filter 200, the grid of the 8th MOS transistor M8 is connected to the second bias voltage Vb2, and the source class of the 8th MOS transistor M8 is connected to the orthogonal reverse input end net4 of second-order filter 200;
One end of 5th electric capacity C5 is connected to the homophase positive input net1 of second-order filter 200, and the other end of the 5th electric capacity C5 is connected to the orthogonal forward output net6 of second-order filter 200;
One end of 6th electric capacity C6 is connected to the orthogonal positive input net2 of second-order filter 200, and the other end of the 6th electric capacity C6 is connected to the homophase inverse output terminal net7 of second-order filter 200;
One end of 7th electric capacity C7 is connected to the homophase reverse input end net3 of second-order filter 200, and the other end of the 7th electric capacity C7 is connected to the orthogonal inverse output terminal net8 of second-order filter 200;
One end of 8th electric capacity C8 is connected to the orthogonal reverse input end net4 of second-order filter 200, and the other end of the 8th electric capacity C8 is connected to the homophase forward output net5 of second-order filter 200;
Described 3rd rank filter 300 comprises: the 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11, the 12 MOS transistor M12, the 9th electric capacity C9, the tenth electric capacity C10, the 11 electric capacity C11 and the 12 electric capacity C12.
Wherein the drain electrode of the 9th MOS transistor M9 is connected to the homophase forward output IPO of the 3rd rank filter 300, the grid of the 9th MOS transistor M9 is connected to the 3rd bias voltage Vb3, and the source class of the 9th MOS transistor M9 is connected to the homophase positive input net5 of the 3rd rank filter 300;
The drain electrode of the tenth MOS transistor M10 is connected to the orthogonal forward output QPO of the 3rd rank filter 300, the grid of the tenth MOS transistor M10 is connected to the 3rd bias voltage Vb3, and the source class of the tenth MOS transistor M10 is connected to the orthogonal positive input net6 of the 3rd rank filter 300;
The drain electrode of the 11 MOS transistor M11 is connected to the homophase inverse output terminal INO of the 3rd rank filter 300, the grid of the 11 MOS transistor M11 is connected to the 3rd bias voltage Vb3, and the source class of the 11 MOS transistor M11 is connected to the homophase reverse input end net7 of the 3rd rank filter 300;
The drain electrode of the 12 MOS transistor M12 is connected to the orthogonal inverse output terminal QNO of the 3rd rank filter 300, the grid of the 12 MOS transistor M12 is connected to the 3rd bias voltage Vb3, and the source class of the 12 MOS transistor M12 is connected to the orthogonal reverse input end net8 of the 3rd rank filter 300;
One end of 9th electric capacity C9 is connected to the homophase positive input net5 of the 3rd rank filter 300, and the other end of the 9th electric capacity C9 is connected to the orthogonal forward output QPO of the 3rd rank filter 300;
One end of tenth electric capacity C10 is connected to the orthogonal positive input net6 of the 3rd rank filter 300, and the other end of the 9th electric capacity C9 is connected to the homophase inverse output terminal INO of the 3rd rank filter 300;
One end of 11 electric capacity C11 is connected to the homophase reverse input end net7 of the 3rd rank filter 300, and the other end of the 11 electric capacity C11 is connected to the orthogonal inverse output terminal QNO of the 3rd rank filter 300;
One end of 12 electric capacity C12 is connected to the orthogonal reverse input end net8 of the 3rd rank filter 300, and the other end of the 12 electric capacity C12 is connected to the homophase forward output IPO of the 3rd rank filter 300;
The present invention is by homophase positive input IP, orthogonal positive input QP, homophase reverse input end IN and orthogonal reverse input end QN tetra-port accepts four road orthogonal differential signal, and output port is homophase forward output IPO, orthogonal forward output QPO, homophase inverse output terminal INO and orthogonal inverse output terminal QPO; By regulating the first bias voltage Vb1, the second bias voltage Vb2 and the 3rd bias voltage Vb3, the conducting resistance of MOS transistor can be changed, thus change the bandwidth of passive polyphase filter.
The present invention and traditional prior art simplified in comparison circuit structure, reduce chip area.
More than show and describe general principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; what describe in above-described embodiment and specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.Application claims protection range is defined by appending claims and equivalent thereof.
Claims (4)
1. the passive polyphase filter circuit that bandwidth is adjustable, is characterized in that, comprise the firstorder filter, second-order filter and the 3rd rank filter that once connect, three bank of filters form the passive polyphase filter on three rank altogether.
2. the passive polyphase filter circuit that a kind of bandwidth according to claim 1 is adjustable, it is characterized in that, described firstorder filter comprises: the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity; The drain electrode of described first MOS transistor is connected to the homophase forward output of firstorder filter,
The grid of described first MOS transistor is connected to the first bias voltage, and the source class of the first MOS transistor is connected to the homophase positive input of firstorder filter;
The drain electrode of described second MOS transistor is connected to the orthogonal forward output of firstorder filter, and the grid of the second MOS transistor is connected to the first bias voltage, and the source class of the second MOS transistor is connected to the orthogonal positive input of firstorder filter;
The drain electrode of described 3rd MOS transistor is connected to the homophase inverse output terminal of firstorder filter, and the grid of the 3rd MOS transistor is connected to the first bias voltage, and the source class of the 3rd MOS transistor is connected to the homophase reverse input end of firstorder filter;
The drain electrode of described 4th MOS transistor is connected to the orthogonal inverse output terminal of firstorder filter, and the grid of the 4th MOS transistor is connected to the first bias voltage, and the source class of the 4th MOS transistor is connected to the orthogonal reverse input end of firstorder filter;
One end of described first electric capacity is connected to the homophase positive input of firstorder filter, and the other end of the first electric capacity is connected to the orthogonal forward output of firstorder filter;
One end of described second electric capacity is connected to the orthogonal positive input of firstorder filter, and the other end of the second electric capacity is connected to the homophase inverse output terminal of firstorder filter;
One end of described 3rd electric capacity is connected to the homophase reverse input end of firstorder filter, and the other end of the 3rd electric capacity is connected to the orthogonal inverse output terminal of firstorder filter;
One end of described 4th electric capacity is connected to the orthogonal reverse input end of firstorder filter, and the other end of the 4th electric capacity is connected to the homophase forward output of firstorder filter.
3. the passive polyphase filter circuit that a kind of bandwidth according to claim 1 is adjustable, it is characterized in that, described second-order filter comprises: the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th electric capacity;
The drain electrode of described 5th MOS transistor is connected to the homophase forward output of second-order filter, and the grid of the 5th MOS transistor is connected to the second bias voltage, and the source class of the 5th MOS transistor is connected to the homophase positive input of second-order filter;
The drain electrode of described 6th MOS transistor is connected to the orthogonal forward output of second-order filter, and the grid of the 6th MOS transistor is connected to the second bias voltage, and the source class of the 6th MOS transistor is connected to the orthogonal positive input of second-order filter;
The drain electrode of described 7th MOS transistor is connected to the homophase inverse output terminal of second-order filter, and the grid of the 7th MOS transistor is connected to the second bias voltage, and the source class of the 7th MOS transistor is connected to the homophase reverse input end of second-order filter;
The drain electrode of described 8th MOS transistor is connected to the orthogonal inverse output terminal of second-order filter, and the grid of the 8th MOS transistor is connected to the second bias voltage, and the source class of the 8th MOS transistor is connected to the orthogonal reverse input end of second-order filter;
One end of described 5th electric capacity is connected to the homophase positive input of second-order filter, and the other end of the 5th electric capacity is connected to the orthogonal forward output of second-order filter;
One end of described 6th electric capacity is connected to the orthogonal positive input of second-order filter, and the other end of the 6th electric capacity is connected to the homophase inverse output terminal of second-order filter;
One end of described 7th electric capacity is connected to the homophase reverse input end of second-order filter, and the other end of the 7th electric capacity is connected to the orthogonal inverse output terminal of second-order filter;
One end of described 8th electric capacity is connected to the orthogonal reverse input end of second-order filter, and the other end of the 8th electric capacity is connected to the homophase forward output of second-order filter.
4. the passive polyphase filter circuit that a kind of bandwidth according to claim 1 is adjustable, it is characterized in that, described 3rd rank filter comprises: the 9th MOS transistor, the tenth MOS transistor, the 11 MOS transistor, the 12 MOS transistor, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity and the 12 electric capacity;
The drain electrode of described 9th MOS transistor is connected to the homophase forward output of the 3rd rank filter, and the grid of the 9th MOS transistor is connected to the 3rd bias voltage, and the source class of the 9th MOS transistor is connected to the homophase positive input of the 3rd rank filter;
The drain electrode of described tenth MOS transistor is connected to the orthogonal forward output of the 3rd rank filter, and the grid of the tenth MOS transistor is connected to the 3rd bias voltage, and the source class of the tenth MOS transistor is connected to the orthogonal positive input of the 3rd rank filter;
The drain electrode of described 11 MOS transistor is connected to the homophase inverse output terminal of the 3rd rank filter, and the grid of the 11 MOS transistor is connected to the 3rd bias voltage, and the source class of the 11 MOS transistor is connected to the homophase reverse input end of the 3rd rank filter;
The drain electrode of described 12 MOS transistor is connected to the orthogonal inverse output terminal of the 3rd rank filter, and the grid of the 12 MOS transistor is connected to the 3rd bias voltage, and the source class of the 12 MOS transistor is connected to the orthogonal reverse input end of the 3rd rank filter;
One end of described 9th electric capacity is connected to the homophase positive input of the 3rd rank filter, and the other end of the 9th electric capacity is connected to the orthogonal forward output of the 3rd rank filter;
One end of described tenth electric capacity is connected to the orthogonal positive input of the 3rd rank filter, and the other end of the 9th electric capacity is connected to the homophase inverse output terminal of the 3rd rank filter;
One end of described 11 electric capacity is connected to the homophase reverse input end of the 3rd rank filter, and the other end of the 11 electric capacity is connected to the orthogonal inverse output terminal of the 3rd rank filter;
One end of described 12 electric capacity is connected to the orthogonal reverse input end of the 3rd rank filter, and the other end of the 12 electric capacity is connected to the homophase forward output of the 3rd rank filter.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310299086.8A CN104300931A (en) | 2013-07-16 | 2013-07-16 | Bandwidth-adjustable passive multiphase filter circuit |
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| CN201310299086.8A CN104300931A (en) | 2013-07-16 | 2013-07-16 | Bandwidth-adjustable passive multiphase filter circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110581700A (en) * | 2019-08-30 | 2019-12-17 | 浙江大学 | Ultra-wideband second-order polyphase filter adopting inductance to compensate high-frequency gain |
| EP4009521A1 (en) * | 2020-12-03 | 2022-06-08 | Mediatek Inc. | Filter circuit using polyphase filter with dynamic range enhancement |
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| US20090295398A1 (en) * | 2007-11-26 | 2009-12-03 | Honda Motor Co. Ltd. | Voltage detecting device for battery modules |
| CN203423661U (en) * | 2013-07-16 | 2014-02-05 | 陕西北斗恒通信息科技有限公司 | Adjustable-bandwidth passive multi-phase filter circuit |
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| CN1340934A (en) * | 2000-09-02 | 2002-03-20 | 华为技术有限公司 | Broadband data access circuit and its self-adaptive regulation method of channel |
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| US20090295398A1 (en) * | 2007-11-26 | 2009-12-03 | Honda Motor Co. Ltd. | Voltage detecting device for battery modules |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110581700A (en) * | 2019-08-30 | 2019-12-17 | 浙江大学 | Ultra-wideband second-order polyphase filter adopting inductance to compensate high-frequency gain |
| CN110581700B (en) * | 2019-08-30 | 2021-01-29 | 浙江大学 | Ultra-wideband second-order polyphase filter adopting inductance to compensate high-frequency gain |
| EP4009521A1 (en) * | 2020-12-03 | 2022-06-08 | Mediatek Inc. | Filter circuit using polyphase filter with dynamic range enhancement |
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