CN104300928B

CN104300928B - It is differential to turn single-ended converter

Info

Publication number: CN104300928B
Application number: CN201310306073.9A
Authority: CN
Inventors: 陈信光
Original assignee: MStar Semiconductor Inc Taiwan
Current assignee: MediaTek Inc
Priority date: 2013-07-19
Filing date: 2013-07-19
Publication date: 2017-03-29
Anticipated expiration: 2033-07-19
Also published as: CN104300928A

Abstract

The present invention provide it is a kind of it is differential turn single-ended converter and related method, by a differential input signals, to be converted into a single-end output signal.This is differential to turn single-ended converter and includes first, second, third and the 4th transistor, and a current source pair.The first transistor and the transistor seconds are driven by the differential input signals.The first transistor and the transistor seconds have 2 first conduction terminals being coupled together, and are not coupled to 2 second conduction terminals together.The third transistor and the 4th transistor are driven by the differential input signals, are cascaded with the first transistor and the transistor seconds respectively.The current source is coupled to second conduction terminals of the first transistor to being in series with the third transistor and the 4th transistor respectively with a common control end.Second conduction terminals of the transistor seconds are to produce the single-end output signal.

Description

It is differential to turn single-ended converter

Technical field

Embodiments of the invention be generally concerned with it is differential turn single-ended converter, espespecially by a differential input signals, be converted into The transducer of one single-end output signal.

Background technology

In order to resist from power line and semiconductor base the noise for transmitting, the internal signal in integrated circuit can be used One differential mode (differential mode) is being processed.For example, ring oscillator (ring oscillator) It is exactly often producing clock signal, common mode (common mode) noise can be avoided to produced by frequency using differential mode Impact.

However, the differential wave that differential mode is adopted needs at least two bars transmission lines, compared with needed for single-ended signal One bars transmission line, it will increase the complexity and IC bond quantity (pin count) of coiling.Therefore, it is integrated In circuit, the signal of most logic circuit all adopts single-ended mode (single-end mode), and needs high antimierophonic Part just adopts differential mode.The differential single-ended converter that turns is responsible for, by a differential input signals, being converted into a single-end output signal, The bridge joint being taken as in the circuit of unlike signal pattern.

Fig. 1 show it is differential known to one turn single-ended converter 10, which includes two nmos pass transistors N1 and N2, and two Individual PMOS transistor P1 and P2.The differential single-ended converter 10 that turns can be considered as differential amplifier (differential known to amplifier).Constitute the non-return signal S-NON and reverse signal S-INV difference input NMOS transistor N1 of a differential wave With the grid end (gate) of N2.PMOS transistor P1 is then combined into a current mirror (current mirror) with P2, and both is common Control end CON-O is connected to a drain terminal (drain) of PMOS transistor P1 together.Nmos pass transistor N1 is gone here and there with PMOS transistor P1 It is connected between power line VDD and VSS.Nmos pass transistor N2 and PMOS transistor P2, through outfan OUT, are serially connected with power line Between VDD and VSS.Outfan OUT produces single-ended signal S-ONE.

One good differential single-ended converter that turns will rapidly change which as the logical value of differential wave switches The logical value of single-ended signal.Additionally, the differential voltage conversioning rate (slew rate) for turning single-ended converter, it is also necessary to fast.Such as This, receives the differential clock signal that provided by ring oscillator to produce during single-ended clock signal, the work of single-ended clock signal Making the cycle (duty cycle) just can closely ideal value 50%.

The content of the invention

Embodiments of the invention propose that one kind is differential and turn single-ended converter, by a differential input signals, to be converted into one Single-end output signal.This is differential to turn single-ended converter and includes first, second, third and the 4th transistor, and a current source It is right.The first transistor and the transistor seconds are driven by the differential input signals.The first transistor and second crystal Pipe is with 2 first conduction terminals being coupled together, and is not coupled to 2 second conduction terminals together.The third transistor Driven by the differential input signals with the 4th transistor, one is connected on the first transistor and the transistor seconds respectively Rise.The current source is coupled to this to being in series with the third transistor and the 4th transistor respectively with a common control end Second conduction terminals of the first transistor.Second conduction terminals of the transistor seconds are to produce the single-end output signal.

Embodiments of the invention separately propose a kind of signal conversion method, by a differential wave, to be converted into a single-ended letter Number.The differential wave includes a non-return signal and a reverse signal.The method includes：One outfan is provided, to Produce the single-ended signal；One current source is provided；The current source is controlled according to the non-return signal；And according to the reverse letter Number, one of a discharge path and a charge path are turned on, and it are wherein another with the charge path to cut off the discharge path, Wherein, when the differential wave is first logical value, the current source passes through the charge path of the conducting to the signal output part Charge, when the differential wave is second logical value, the outfan discharges through the discharge path of the conducting.

Description of the drawings

It is that the above objects, features and advantages of the present invention can be become apparent, below in conjunction with tool of the accompanying drawing to the present invention Body embodiment elaborates, wherein：

Fig. 1 shows and differential known to one turns single-ended converter.

Fig. 2 and Fig. 3 to show and two differential turned single-ended converter according to what the present invention implemented.

Fig. 4 show one using Fig. 2 the differential integrated circuit for turning single-ended converter 20.

Component label instructions in figure：

10th, 20,30 differential turn single-ended converter

52 voltage control oscillators

54 logic circuits

CON, CON-O co- controlling end

N1, N2, N11, N12 nmos pass transistor

OUT outfans

P1, P2, P11, P12, P21, P22 PMOS transistor

S-INV reverse signals

S-ONE single-ended signals

The non-return signals of S-NON

VCC, VDD, VSS power line

Specific embodiment

Fig. 2 to show and turn single-ended converter 20 according to the differential of one embodiment of the invention.As shown in Figure 2, differential turn of list End transducer 20 is with two nmos pass transistor N11 and N12 and four PMOS transistor P11, P12, P21 and P22.One In embodiment, the component size of nmos pass transistor N11 and N12 is about；PMOS transistor P11 is big with the component size of P12 About；The component size of PMOS transistor P21 and P22 is about.

Nmos pass transistor N11 and N12 is differential right as one, and its grid end is respectively by the non-return signal S-NON of differential wave Driven with reverse signal S-INV.Nmos pass transistor N11 is couple to power line VSS together with the source of N12, and NMOS crystal Together with pipe N11 is not coupled to the drain terminal of N12.The mode of operation of nmos pass transistor N11 and N12 can be complementary.In other words, when When nmos pass transistor N11 is turned on, nmos pass transistor N12 is closed, and vice versa.

Used as another differential right, its grid end is respectively by the non-return signal S- of differential wave for PMOS transistor P11 and P12 NON is driven with reverse signal S-INV.As shown in Figure 2, PMOS transistor P11 and P12 respectively with nmos pass transistor N11 It is cascaded with N12.In Fig. 2, PMOS transistor P11 can be complementary with the mode of operation of P12.In other words, work as PMOS transistor When P11 is turned on, PMOS transistor P12 is closed, and vice versa.

PMOS transistor P21 can be considered as a current source pair with P22, and its grid end links together, used as a co- controlling End CON, is connected to the drain terminal of nmos pass transistor N11, and the drain terminal of PMOS transistor P11.PMOS transistor P21 is divided with P22 It is not cascaded with P12 with PMOS transistor P11.PMOS transistor P21 is together couple to power line VDD with the source of P22.

The drain terminal of nmos pass transistor N12, and the drain terminal of PMOS transistor P12, used as a signal output part OUT, which can To produce single-end output signal S-ONE.

Following operation will be with power line VDD as 1.1V, and power line VSS is 0V, rather than reverse signal S-NON and reversely believes The change in voltage of number S-INV does not have track to track (rail-to-rail), changes, be used as example only between 0V to 0.6V, But it is not intended to limit the present invention.When the voltage of non-return signal S-NON and reverse signal S-INV is respectively 0V and 0.6V, The logical value of differential wave is " 0 "；Conversely, when the voltage of non-return signal S-NON and reverse signal S-INV be respectively 0.6V with During 0V, the logical value of differential wave is " 1 ".

When differential wave is " 0 ", nmos pass transistor N11 and PMOS transistor P12 are closed, nmos pass transistor N12 with PMOS transistor P11 is turned on.Therefore, the discharge path provided by nmos pass transistor N12 signal output part OUT switched on is dragged down For 0V, the logical value of single-end output signal S-ONE is " 0 ".Now, CON equivalents in co- controlling end are connected to PMOS transistor P21 Drain terminal, so PMOS transistor P21 and P22 constitute an equivalent current mirror.PMOS transistor P21 is with P22 respectively as two Individual charging current source, two drain terminals of pair pmos transistor P21 and P22 charge, so this two drain terminal and co- controlling end CON Voltage can be about 1V or slightly below 1V.

When differential wave will be converted into " 1 " from " 0 ", non-return signal S-NON is begun to ramp up from 0V, and reverse signal S- INV is begun to decline from 0.6V.Once the voltage of non-return signal S-NON be higher than reverse signal S-INV, nmos pass transistor N11 with The transition of PMOS transistor P12 is conducting, and nmos pass transistor N12 is closing with the transition of PMOS transistor P11.PMOS transistor P21 This charging current source, because the closing of PMOS transistor P11, cannot charge to co- controlling end CON.Therefore, it is common to control The discharge path provided by nmos pass transistor N11 end CON processed switched on, rapidly discharges into 0V.Nmos pass transistor N12's Close, equal to having cut off discharge paths of the signal output part OUT to power line VSS.Now, PMOS transistor P22 is as charging Current source, through the charge path provided by PMOS transistor P12 of conducting, charges to signal output part OUT.Because common control The voltage of end CON processed is 0V, and the gate source voltage (gate-to-source voltage) of PMOS transistor P22 would is that -1V, It is exactly the maximum possible negative value under the system that power line VDD and power line VSS powers, so PMOS transistor P22 will be with maximum Charging current is to signal output part OUT quick charges.The voltage for finally making single-end output signal S-ONE is 1V, and logical value is “1”。

When differential wave will be converted into " 0 " from " 1 ", non-return signal S-NON is begun to decline from 0.6V, and reverse signal S-INV is begun to ramp up from 0V.Once the voltage of non-return signal S-NON be less than reverse signal S-INV, nmos pass transistor N12 with The transition of PMOS transistor P11 is conducting, and nmos pass transistor N11 is closing with the transition of PMOS transistor P12.Now, PMOS crystal The charge path provided by pipe P12 is equal to and is cut off.The nmos pass transistor N12 of conducting then provides a discharge path, defeated to signal Go out and hold OUT to discharge.So the voltage of single-end output signal S-ONE rapidly can drop to 0V from 1V, logical value becomes " 0 ".Close Nmos pass transistor N11 make co- controlling end CON from coupling in power line VSS, that is, disconnect the coupling with power line VSS.PMOS is brilliant Body pipe P21 this charging current source, can pass through PMOS transistor P11 of conducting, be charged to about 1V-Vthp to co- controlling end CON, Critical voltages (threshold voltage) of the Vthp herein for PMOS transistor P21.And PMOS transistor P22 this charging Current source can be charged to the drain terminal of PMOS transistor P22 after about 1V and stop.

In the embodiment of fig. 2, the voltage swing (voltage of non-return signal S-NON and reverse signal S-INV Swing it is) 0.6V, less than the voltage swing (which is 1V) of single-end output signal S-ONE.Non-return signal S-NON, reverse signal The low logic current potential of S-INV and single-end output signal S-ONE is all 0V.The height of non-return signal S-NON and reverse signal S-INV Logic level is 0.6V, and the high logic level of single-end output signal S-ONE is 1V.

As long as appropriate design, single-end output signal S-ONE in Fig. 2 declines switching rate and rises switching rate all Can be suitable it is quick, exceed the decline switching rate of single-end output signal S-ONE in Fig. 1 and rise switching rate.When Differential wave in Fig. 2 will be converted into " 0 " from " 1 ", because even the charging current provided by PMOS transistor P22 is not temporarily 0, reverse signal S-INV can be initially switched off the charge path provided by PMOS transistor P12, make signal output part OUT only by Nmos pass transistor N12 discharges and rapid decrease.When differential wave will be converted into " 1 " from " 0 ", because reverse signal S-INV cut-outs The discharge path provided by nmos pass transistor N12, and the charging circuit provided through PMOS transistor P12 by PMOS transistor P22 Footpath, is maximum to the charging current of signal output part OUT, so the rising switching rate of single-end output signal S-ONE can phase When quick.

When the differential wave in Fig. 2 switches, can be by rapidly to the charge path and discharge path of signal output part OUT Formed or cut off, so response speed of single-end output signal S-ONE on signal output part OUT to differential wave, also can It is considerably fast.

The decline switching rate and rising switching rate of single-end output signal S-ONE in Fig. 1, ties compared in Fig. 2 Really, in theory can be slow.For example, when the differential wave in Fig. 1 will be converted into " 0 " from " 1 ", although nmos pass transistor N2 and N1 is quickly turned on respectively and is closed, but signal output part OUT quickly will not decline at the very start, it is necessary to when altogether It is charged to a certain degree with control end CON-O, until the charging current provided by PMOS transistor P2 is less than nmos pass transistor The discharge current provided by N2, the voltage of signal output part OUT can just start " at leisure " decline.So single-ended defeated in Fig. 1 The response speed and decline switching rate for going out signal S-ONE all can be smaller.

It is similar, and work as the differential wave in Fig. 1 from " 0 " " 1 " will be converted into when, although nmos pass transistor N1 and N2 distinguishes Quickly conducting and closing, but co- controlling end CON-O cannot be low to 0V, because being limited to what PMOS transistor P1 was formed MOS diode and strangulation.So charging current of PMOS transistor P2 to signal output part OUT, it is impossible to reach PMOS transistor The maximum possible electric current of P2.Therefore, in Fig. 1, the rising switching rate of single-end output signal S-ONE also can be considerably limited.

Just because of in Fig. 2 single-end output signal S-ONE to differential wave (by non-return signal S-NON and reverse signal S- INV is constituted) response speed it is very fast, and the rise/fall switching rate of single-end output signal S-ONE is all suitable Height, so when the working cycle of differential wave being 50%, as long as appropriate design, single-end output signal S-ONE can in Fig. 2 To be readily obtained substantially not with 50% working cycle of manufacture of semiconductor parameter drift.

Fig. 3 to show and turn single-ended converter 30 according to the differential of another embodiment of the present invention.Single-ended turn of differential turn in Fig. 3 Differential in parallel operation 30 and Fig. 2 turns single-ended converter 20, is complementary relationship each other.The differential operation for turning single-ended converter 30 and original Reason, can be, with general circuit design skill, to analogize understanding with illustrating according to the teaching of Fig. 2, therefore be not repeated.

Fig. 4 show one using Fig. 2 the differential integrated circuit for turning single-ended converter 20.Voltage control oscillator 52 can To produce a clock signal, its after the reverser that two power line VCC with 0.6V and 0V power line VSS power is processed, Non-return signal S-NON and reverse signal S-INV is produced, feeding is differential to turn single-ended converter 20, as shown in Figure 4.Differential turn Single-ended converter 20 produces single-end output signal S-ONE of 50% working cycle, through two with 1V power lines VDD and 0V power supplys After the reverser that line VSS powers strengthens its driving force, logic circuit 54 is sent into.

Although the present invention is disclosed as above with preferred embodiment, so which is not limited to the present invention, any this area skill Art personnel, without departing from the spirit and scope of the present invention, when a little modification and perfect, therefore the protection model of the present invention can be made Enclose when by being defined that claims are defined.

Claims

1. one kind is differential turns single-ended converter (differential to single-end converter), to differential by one Input signal is converted into a single-end output signal, and the differential single-ended converter that turns includes：

One the first transistor and a transistor seconds, are driven by the differential input signals, the first conduction of the first transistor End couples the first conduction terminals of the transistor seconds, and the second conduction terminals of the first transistor do not couple the transistor seconds The second conduction terminals；

One third transistor and one the 4th transistor, are driven by the differential input signals, respectively with the first transistor and should Transistor seconds is cascaded；

One current source pair, is in series with the third transistor and the 4th transistor respectively, with a common control end, is coupled to Second conduction terminals of the first transistor；

Wherein, second conduction terminals of the transistor seconds are to produce the single-end output signal.

2. it is as claimed in claim 1 differential to turn single-ended converter, it is characterised in that the first transistor and the transistor seconds are the One transistor npn npn, the third transistor and the 4th transistor are the second transistor npn npn, first transistor npn npn be complementary to this Two transistor npn npns.

3. it is as claimed in claim 1 differential to turn single-ended converter, it is characterised in that the current source to include one the 5th transistor and One the 6th transistor, is connected with the third transistor and the 4th transistor respectively, the 5th transistor and the 6th transistor Co- controlling end be connected to second conduction terminals of the first transistor.

4. it is differential as claimed in claim 1 to turn single-ended converter, it is characterised in that the behaviour of the first transistor and the transistor seconds It is complementation to make the mode of operation that state is complementation, the third transistor and the 4th transistor.

5. it is differential as claimed in claim 1 to turn single-ended converter, it is characterised in that the unit of the first transistor and the transistor seconds Part size is identical, and the third transistor is identical with the 4th transistor unit size, and the element size of the current source pair is identical.

6. it is differential as claimed in claim 1 to turn single-ended converter, it is characterised in that the differential single-ended converter that turns includes a high pressure Power line and a low-tension supply line, first conduction terminals of the first transistor and first conduction terminals of the transistor seconds The low-tension supply line is respectively coupled to, the current source is to being coupled to the high-voltage power-line.

7. it is as claimed in claim 1 differential to turn single-ended converter, it is characterised in that the differential input signals by a non-return signal with And one reverse signal constituted, drive the first transistor and the transistor seconds respectively.

8. it is differential as claimed in claim 7 to turn single-ended converter, it is characterised in that the electricity of the non-return signal and the reverse signal The pressure amplitude of oscillation (voltage swing), less than the voltage swing of the single-end output signal.

9. as claimed in claim 8 this differential turns single-ended converter, it is characterised in that the non-return signal, the reverse signal and The single-end output signal enjoys a low logic current potential jointly.

10. a kind of signal conversion method, be applied to one it is differential turn single-ended converter, it is single-ended a differential wave is converted into one Signal, this is differential to turn single-ended converter to include a first transistor, a transistor seconds, a third transistor brilliant with one the 4th Body pipe, one first conduction terminals of the first transistor couple one first conduction terminals of the transistor seconds, the first transistor One second conduction terminals do not couple one second conduction terminals of the transistor seconds, the 3rd and the 4th transistor, respectively with this first It is cascaded with transistor seconds, the differential wave includes a non-return signal and a reverse signal, the method is included Have：

An outfan is provided, to produce the single-ended signal；

One current source is provided；

According to the non-return signal, through this first with third transistor controlling the current source；And

According to the reverse signal, through this second and one of one discharge path of the 4th transistor turns and a charge path, And it is wherein another with the charge path to cut off the discharge path, wherein, when the differential wave is first logical value, the electricity Stream source is charged to the outfan through the charge path of the conducting, when the differential wave is second logical value, the outfan Discharge through the discharge path of the conducting.

11. as claim 10 signal conversion method, it is characterised in that control the current source according to the non-return signal Step is included：The control end that the current source is controlled according to the non-return signal is couple to a low-voltage source line, makes the current source The charging current of offer is maximized.

12. as claim 10 signal conversion method, further include：When the discharge path is turned on according to the reverse signal, according to It is about 0 that the current source is controlled according to the non-return signal.

13. as claim 11 signal conversion method, further include：When the discharge path is turned on according to the reverse signal, according to The control end is controlled according to the non-return signal and disconnects the coupling with the LVPS line.