CN104282738A - Gate pad structure capable of reducing on resistance of power device - Google Patents
Gate pad structure capable of reducing on resistance of power device Download PDFInfo
- Publication number
- CN104282738A CN104282738A CN201410590768.9A CN201410590768A CN104282738A CN 104282738 A CN104282738 A CN 104282738A CN 201410590768 A CN201410590768 A CN 201410590768A CN 104282738 A CN104282738 A CN 104282738A
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- China
- Prior art keywords
- gate liner
- power device
- conducting resistance
- doped region
- drift layer
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- 238000002161 passivation Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a gate pad structure capable of reducing the on resistance of a power device. The gate pad structure comprises a first drifting layer, a plurality of active units, a plurality of gate pad strips and a passivation layer, wherein the active units are formed in the first drifting layer, the gate pad strips are formed on the first drifting layer and the active units, the passivation layer is formed on the active units and the gate pad strips, and the center of each gate pad strip is located above the first drifting layer between two adjacent active units. According to the gate pad structure capable of reducing the on resistance of the power device, the gate pad structure is composed of the gate pad strips, the active units are formed below the gate pad strips, and thus the microcurrent can be increased; meanwhile, the on resistance of the power device using the gate pad structure is effectively lowered, and the on resistance is lowered to be about 90% of the original on resistance.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of gate liner structure reducing power device conducting resistance.
Background technology
The material of conductivity between conductor and insulator is semiconductor, utilize the electronic device of semi-conducting material manufacturing to have special conductive characteristic because of it, thus be widely used in the field such as consumer electronics, computer and peripheral hardware thereof, communication, power supply electrical equipment.Power device is a kind of electronic device by semi-conducting material manufacturing, and it is mainly used in the device as Power Processing in circuit.In the structure of existing power device, gate liner (Gate PAD) 100 just in order to the conducting of grid (Gate) carrying device or cut-off (Turn On/Off) electric signal but, its area (field) is determined with metal thickness by the gold thread bonding (Wire bonding) during encapsulation, as shown in Figure 1, this gate liner 100 is generally square bulk, as sized by be the square of 500um × 5000um.
Summary of the invention
The object of the present invention is to provide a kind of gate liner structure reducing power device conducting resistance, effectively can reduce the conducting resistance of the power device of this gate liner structure of application, conducting resistance about reduces to original 90%.
Technical scheme of the present invention is as follows: the invention provides a kind of gate liner structure reducing power device conducting resistance, comprise: the first drift layer, the several active cells be formed in described first drift layer, the passivation layer being formed at several gate liner bars on described first drift layer and several active cell and being formed on described several active cell and several gate liner bars, above the first drift layer between two adjacent active cells of the centre of gate liner bar described in each.
Described in each, gate liner bar is rectangular-shaped.
Described in each, the width of gate liner bar is 2-10um, and the spacing between adjacent two gate liner bars is 5-15um.
Described in each, the width of gate liner bar is 6um, and the spacing between adjacent two gate liner bars is 9um.
The described gate liner structure reducing power device conducting resistance also comprises several insulating barrier, and the quantity of described insulating barrier equals the quantity of described gate liner bar, and insulating barrier described in each establishes the below being formed at a gate liner bar.
The described gate liner structure reducing power device conducting resistance also comprises the metal level be formed on described passivation layer and the second drift layer be formed at below described first drift layer, and first and second drift layer described is N-type drift layer.
The area of active cell described in each is 15um × 15um, and the quantity of described active cell is 2-3200.
Described in each, active cell comprises: P-doped region and the P+ doped region be formed in described P-doped region and two N+ doped regions, described P+ doped region is arranged in the below of inside, described P-doped region, and described two N+ doped regions are symmetrically set in described P-doped region.
Described in each, the thickness of P-doped region is 3um, and described in each, the thickness of N+ doped region is 0.5um.
Adopt such scheme, the gate liner structure reducing power device conducting resistance of the present invention, wherein gate liner structure is made up of several gate liner bars, and several active cell is formed below this gate liner bar, micro-electric current can be increased, also effectively reduce the conducting resistance of the power device of this gate liner structure of application, conducting resistance about reduces to original 90% simultaneously.
Accompanying drawing explanation
Fig. 1 is the structural representation of gate liner structure in existing power device.
Fig. 2 is the structural representation that the present invention can reduce the gate liner structure of power device conducting resistance.
Fig. 3 is the structural representation that the present invention can reduce active cell in the gate liner structure of power device conducting resistance.
Fig. 4 is that existing power device contrasts schematic diagram with the conducting resistance of the power device of application gate liner structure of the present invention.
Fig. 5 is that existing power device contrasts schematic diagram with the source-drain electrode puncture voltage of the power device of application gate liner structure of the present invention.
Fig. 6 is that existing power device contrasts schematic diagram with the conducting voltage of the power device of application gate liner structure of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Refer to Fig. 2 and Fig. 3, the invention provides a kind of gate liner structure reducing power device conducting resistance, comprising: the first drift layer 2, the several active cells 3 be formed in described first drift layer 2, the passivation layer 5 being formed at several gate liner bars 4 on described first drift layer 2 and several active cell 3 and being formed on described several active cell 3 and several gate liner bars 4.Above the first drift layer 2 between two adjacent active cells 3 of the centre of gate liner bar 4 described in each.Gate liner structure is designed to be made up of several gate liner bars 4 by the present invention, and several active cell 3 is formed below this gate liner bar 4, micro-electric current can be increased, also effectively reduce the conducting resistance Rds(on of the power device of this gate liner structure of application simultaneously), conducting resistance Rds(on) about reduce to original 90%
Concrete, described in each, gate liner bar 4 is in rectangular-shaped.Described in each, the width L of gate liner bar 4 is 2-10um, and the spacing L2 between adjacent two gate liner bars is 5-15um.In the present embodiment, described in each, the width L1 of gate liner bar 4 is preferably 6um, and the spacing L2 between adjacent two gate liner bars 4 is preferably 9um.
The described gate liner structure reducing power device conducting resistance also comprises: several insulating barrier 42, be formed at the metal level 6 on described passivation layer 5 and be formed at the second drift layer 7 below described first drift layer 2.The quantity of described insulating barrier 42 equals the quantity of described gate liner bar 4, and described in each, insulating barrier 42 is formed at the below of a gate liner bar 4.First and second drift layer 2,7 described is N-type drift layer.
Described in each, the area of active cell 3 is 15um × 15um, described several active cell 3 need be formed in the area of 500um × 500um, consider engineering manufacturing limit (Margin) simultaneously, the quantity of described active cell 3 is 2-3200, be preferably 3100-3200, reduce conducting resistance Rds(on like this) effect and the effect of the micro-electric current of increase better.Described in each, active cell 3 comprises: P-doped region 32 and the P+ doped region 34 be formed in described P-doped region 32 and two N+ doped regions 36, described P+ doped region 34 is arranged in the below of inside, described P-doped region 32, and described two N+ doped regions 36 are symmetrically set in described P-doped region 32.Described in each, the thickness d 1 of P-doped region 32 is preferably 3um, and described in each, the thickness d 2 of N+ doped region 36 is preferably 0.5um.
Refer to Fig. 4, it is that existing power device contrasts schematic diagram with the conducting resistance of the power device of application gate liner structure of the present invention, wherein, odd number (01 in abscissa, 03, 05, 07 ...) resistance value Rds(on when representing existing power device conducting), its mean value is about 4.6 ohm, even number (02, 04, 06, 08 ...) represent application gate liner structure of the present invention power device conducting time resistance value Rds(on), its mean value is about 4.15 ohm, as can be seen here, adopt the conducting resistance Rds(on of the power device of gate liner structure of the present invention) can 10% be reduced.
Refer to Fig. 5, it is that existing power device contrasts schematic diagram with the source-drain electrode puncture voltage of the power device of application gate liner structure of the present invention, wherein, odd number (01 in abscissa, 03, 05, 07 ...) represent the source-drain electrode breakdown voltage value BVdss of existing power device, even number (02, 04, 06, 08 ...) represent the source-drain electrode breakdown voltage value BVdss of power device of application gate liner structure of the present invention, as can be seen here, compare existing power device, the source-drain electrode breakdown voltage value BVdss of the power device of gate liner structure of the present invention is adopted not change.
Refer to Fig. 6, it is that existing power device contrasts schematic diagram with the conducting voltage of the power device of application gate liner structure of the present invention, wherein, odd number (01,03,05,07 in abscissa ...) represent the conducting voltage Vf of existing power device, even number (02,04,06,08 ...) represent the conducting voltage Vf of power device of application gate liner structure of the present invention, as can be seen here, compare existing power device, adopt the conducting voltage Vf central value of the power device of gate liner structure of the present invention not change.
In sum, the invention provides a kind of gate liner structure reducing power device conducting resistance, wherein gate liner structure is made up of several gate liner bars, and several active cell is formed below this gate liner bar, micro-electric current can be increased, also effectively reduce the conducting resistance of the power device of this gate liner structure of application, conducting resistance about reduces to original 90% simultaneously.
These are only preferred embodiment of the present invention, be not limited to the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. one kind can be reduced the gate liner structure of power device conducting resistance, it is characterized in that, comprise: the first drift layer, the several active cells be formed in described first drift layer, the passivation layer being formed at several gate liner bars on described first drift layer and several active cell and being formed on described several active cell and several gate liner bars, above the first drift layer between two adjacent active cells of the centre of gate liner bar described in each.
2. the gate liner structure reducing power device conducting resistance according to claim 1, it is characterized in that, described in each, gate liner bar is rectangular-shaped.
3. the gate liner structure reducing power device conducting resistance according to claim 1, is characterized in that, described in each, the width of gate liner bar is 2-10um, and the spacing between adjacent two gate liner bars is 5-15um.
4. the gate liner structure reducing power device conducting resistance according to claim 3, is characterized in that, described in each, the width of gate liner bar is 6um, and the spacing between adjacent two gate liner bars is 9um.
5. the gate liner structure reducing power device conducting resistance according to claim 1, it is characterized in that, also comprise several insulating barrier, the quantity of described insulating barrier equals the quantity of described gate liner bar, and insulating barrier described in each establishes the below being formed at a gate liner bar.
6. the gate liner structure reducing power device conducting resistance according to claim 1, it is characterized in that, also comprise the metal level be formed on described passivation layer and the second drift layer be formed at below described first drift layer, first and second drift layer described is N-type drift layer.
7. the gate liner structure reducing power device conducting resistance according to claim 1, is characterized in that, the area of active cell described in each is 15um × 15um, and the quantity of described active cell is 2-3200.
8. the gate liner structure reducing power device conducting resistance according to claim 1, it is characterized in that, described in each, active cell comprises: P-doped region and the P+ doped region be formed in described P-doped region and two N+ doped regions, described P+ doped region is arranged in the below of inside, described P-doped region, and described two N+ doped regions are symmetrically set in described P-doped region.
9. the gate liner structure reducing power device conducting resistance according to claim 8, is characterized in that, described in each, the thickness of P-doped region is 3um, and described in each, the thickness of N+ doped region is 0.5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410590768.9A CN104282738A (en) | 2014-10-29 | 2014-10-29 | Gate pad structure capable of reducing on resistance of power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410590768.9A CN104282738A (en) | 2014-10-29 | 2014-10-29 | Gate pad structure capable of reducing on resistance of power device |
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| Publication Number | Publication Date |
|---|---|
| CN104282738A true CN104282738A (en) | 2015-01-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410590768.9A Pending CN104282738A (en) | 2014-10-29 | 2014-10-29 | Gate pad structure capable of reducing on resistance of power device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03179779A (en) * | 1989-09-29 | 1991-08-05 | Fuji Electric Co Ltd | Insulated-gate semiconductor device |
| CN102683409A (en) * | 2011-03-10 | 2012-09-19 | 凹凸电子（武汉）有限公司 | Methods for fabricating transistors including circular trenches |
| WO2014163058A1 (en) * | 2013-03-31 | 2014-10-09 | 新電元工業株式会社 | Semiconductor device |
| CN204144265U (en) * | 2014-10-29 | 2015-02-04 | 深圳市可易亚半导体科技有限公司 | The gate liner structure of power device conducting resistance can be reduced |
-
2014
- 2014-10-29 CN CN201410590768.9A patent/CN104282738A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03179779A (en) * | 1989-09-29 | 1991-08-05 | Fuji Electric Co Ltd | Insulated-gate semiconductor device |
| CN102683409A (en) * | 2011-03-10 | 2012-09-19 | 凹凸电子（武汉）有限公司 | Methods for fabricating transistors including circular trenches |
| WO2014163058A1 (en) * | 2013-03-31 | 2014-10-09 | 新電元工業株式会社 | Semiconductor device |
| CN204144265U (en) * | 2014-10-29 | 2015-02-04 | 深圳市可易亚半导体科技有限公司 | The gate liner structure of power device conducting resistance can be reduced |
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Application publication date: 20150114 |
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