CN104253160B - A kind of B4 Flash with convex surface grid structure - Google Patents
A kind of B4 Flash with convex surface grid structure Download PDFInfo
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- CN104253160B CN104253160B CN201410375182.0A CN201410375182A CN104253160B CN 104253160 B CN104253160 B CN 104253160B CN 201410375182 A CN201410375182 A CN 201410375182A CN 104253160 B CN104253160 B CN 104253160B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
Abstract
The present invention relates to nonvolatile memory, and in particular to a kind of B4 Flash with convex surface grid structure, grid structure is followed successively by tunnel oxide, charge storage layer, block media layer and conductive layer from bottom to top；Wherein, tunnel oxide is the convex-surface type structure of the lateral middle part protuberance of top surface two；Meanwhile, the charge storage layer is the lateral middle part protuberance of top surface two and bottom surface from the arch bridge-type structure of two lateral medial recess and is completely covered in the upper surface of the tunnel oxide.The present invention can make charge storage layer to the tunnelling of substrate more than the tunnelling that charge storage layer is injected from gate pole by using convex surface grid structure in B4 Flash, such that it is able to suppressing or even eliminating the appearance of erasing saturation, improve erasing speed.
Description
Technical field
The present invention relates to nonvolatile memory, and in particular to a kind of B4-Flash with convex surface grid structure.
Background technology
Flash memory is one kind of non-volatile memory device, and, using floating gate come data storage, and floating boom is general for traditional flash memory
Made using polysilicon (poly) material.
For NOR flash memory mnemon, it is most important limit its size continue reduce be grid shortening long.This is mainly
Because channel hot electron (channel Hot Electrons, abbreviation CHE) injection compiling mode requires that drain terminal has certain electricity
Pressure, and this voltage has a great impact to penetrating for source and drain end, it is inapplicable for short channel device channel hot electron mode.Separately
An outer problem is compared with NAND and AND data storage devices, which has limited the compiling rate of NOR flash memory.According to document
" G.Servalli, et al., IEDM Tech.Dig., 35_1,2005 " is predicted, the physics of the grid diminution long of conventional flash memory structure
The limit is 130nm.
Article " the A 60nm NOR Flash Memory Cell delivered according to Shuo Ji Shukuri et al.
Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot
Electron Injection " refer to the device of B4 (Back Bias Assisted Band-to-Band)-Flash Memory
The principle of part size reduction.
As shown in figure 1, typical floating boom B4-Flash structures are by substrate 10, tunnel oxide (tunnel oxide) 11,
Charge storage layer (floating boom, floating gate, FG) 12, block media layer 13 and conductive layer (control gate, control
Gate, CG, or gate pole) 14 compositions.Include source electrode (source) and drain electrode (drain) in substrate.The structure stores information
Principle be：When compiling, a larger voltage is applied on conductive layer 14, and by source-drain electrode and Substrate ground, due to tunnel
Wearing effect makes the electron tunneling in substrate 10 cross tunnel oxide 11, stores in charge storage layer 12.When erasing, apply one
Negative electricity is depressed into conductive layer 14, and source-drain electrode and substrate 10 are grounded, and the electronics reverse tunnel of charge storage layer 12 returns substrate 10.For
The speed of compiling and erasing is set to improve the tunnel oxide, it is necessary to relatively thin, but so thin thickness can enable the holding of electric charge
Durability reduction in power and compiling/erase process.But the speed of erasing is directly proportional to electric-field intensity, and electric field is bigger, erasing speed
Degree is faster.There are two tunnelling processes in the structure carries out erase process：One is that electronics is tunneling to lining from charge storage layer 12
Bottom 10；Two is that electronics enters in charge storage layer 12 from grid by block media layer 13.
With continued reference to shown in Fig. 1, in traditional floating boom B4-Flash structures, due to each layer (tunnel oxide 11, electric charge
Accumulation layer 12, block media layer 13, conductive layer 14) upper and lower surface is horizontal plane and arranged in parallel, therefore compiling and when wiping
Power line be by the parallel distribution of each layer, wipe start when charge storage layer 12 in electronics quantity it is many, tunnel oxide
Electric field of the electric field of layer 11 much larger than block media layer 13；But with the carrying out of erasing, the middle capture of charge storage layer 12
Electronics is gradually decreased, therefore electric field in tunnel oxide 11 is constantly reduced and the electric field in block media layer 13 is continuously increased,
Electric-field intensity is equal at two when wiping completely.Therefore, tunnelling speed of the electron tunneling to substrate 10 in charge storage layer 12
Can weaken with the decrease of the electric field of tunnel oxide 11, and can be gradually through the tunnelling that conductive layer 14 is tunneling in charge storage layer 12
Enhancing.When the speed of two tunnellings is equal, the electronics in charge storage layer 12 loses and injection reaches dynamic balance, enters
The state of saturation is wiped, prevents erasing from proceeding, erasing speed reduction.
The problem that prior art is present：Because existing floating boom B4-Flash technologies still using the grid structure of plane, are deposited
In the problem of erasing saturation.
Patent (CN 102376770A) discloses a kind of floating-gate device and its method, and the floating-gate device includes：Substrate, tool
There is channel region；Floating boom dielectric substance, it is square over the channel region；Floating boom, on floating boom dielectric substance, and including：Polysilicon
Material, and impurity, in polycrystalline silicon material, and are configured as being interacted to resist substantial thermal sensation with polycrystalline silicon material
Raw polycrystalline silicon material crystallite dimension change；Control gate dielectric, on floating boom；And control gate, on control gate dielectric.
The patent is come to produce interaction with Re Chu with polycrystalline silicon material by the impurity adulterated in polysilicon gate material
The change of the crystallite dimension of polycrystalline silicon material is resisted during reason, and the storage of floating-gate device electric charge is set relative to threshold voltage
Characteristic.But because the structure is identical with traditional Flash structures, the upper following table of the floating boom dielectric substance that it includes and floating boom
Face is a horizontal plane, therefore in programming process, the distribution of its power line is identical with shown in Fig. 1, therefore is still present
There is the problem of erasing saturation.
The content of the invention
The defect that the present invention exists according to B4-Flash of the prior art, there is provided one kind has convex-surface type grid structure
B4-Flash, wherein, the grid structure is arranged at an active area substrate, positioned at the grid structure two bottom sides
Source doping region and drain doping region are formed with active area substrate, one is formed between the source doping region and drain doping region
Raceway groove；
The grid structure is followed successively by tunnel oxide, charge storage layer, block media layer and conductive layer from bottom to top；
Wherein, the convex-surface type structure that the tunnel oxide swells for the lateral middle part of top surface two, and the tunnel oxide
Top surface is a smooth convex cambered surface；
The charge storage layer is the arch bridge-type structure of the lateral middle part protuberance of top surface two and the lateral medial recess in bottom surface two, institute
The top surface and bottom surface for stating charge storage layer are a smooth cambered surface to be completely covered in the upper surface of the tunnel oxide；
The polysilicon or nanocrystalline that the storage medium layer is adulterated from N-type or p-type.
Above-mentioned B4-Flash, wherein, block media layer and conductive layer with the shape phase of the charge storage layer
Same and thickness is different.
Above-mentioned B4-Flash, wherein, the substrate is silicon substrate.
Above-mentioned B4-Flash, wherein, the tunnel oxide is silica.
Above-mentioned B4-Flash, wherein, the conductive layer is polysilicon.
Above-mentioned B4-Flash, wherein, the raceway groove is P-type channel.
Above-mentioned B4-Flash, wherein, the substrate is two lateral middle parts with the contact surface of the tunnel oxide bottom
The convex cambered surface of protuberance.
Above-mentioned B4-Flash, wherein, the block media layer is silicon dioxide layer or silicon oxide-silicon nitride-dioxy
SiClx (ONO) layer.
Above-mentioned B4-Flash, wherein, the charge storage layer thickness is 50-100nm, and the conductive layer thickness is 150-
200nm。
Above-mentioned B4-Flash, wherein, when block media layer is for silica, the block media thickness degree is
5-15nm；
When the block media layer for silicon oxide-silicon nitride-silicon dioxide layer when, then the block media layer bottom
The thickness of silica is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, and the thickness of top silicon dioxide silicon is 2nm-
5nm。
Above-mentioned B4-Flash, wherein, the maximum gauge of the tunnel oxide is no more than in 5nm.
Above-mentioned B4-Flash, wherein, n-type doping is carried out to the storage medium layer from phosphorus or arsenic.
Above-mentioned B4-Flash, wherein, p-type doping is carried out to the storage medium layer from boron or boron fluoride.
Using B4-Flash provided by the present invention erasing when, can make charge storage layer to substrate tunnelling more than from
Grid injects the tunnelling of charge storage layer, such that it is able to suppress even to eliminate the appearance for wiping saturation, improves erasing speed.
Brief description of the drawings
By the detailed description made to non-limiting example with reference to the following drawings of reading, the present invention and its feature, outward
Shape and advantage will become more apparent upon.Identical mark indicates identical part in whole accompanying drawings.Not deliberately proportionally
Draw accompanying drawing, it is preferred that emphasis is purport of the invention is shown.
Fig. 1 is the power line and structural representation of typical floating boom B4-Flash devices；
Fig. 2 a are the principle schematic of B4-Flash memories；
Fig. 2 b are the electron energy band schematic diagram of drain terminal；
Fig. 2 c are the electron energy band schematic diagram of source；
Fig. 3 is the power line and structural representation of B4-Flash of the present invention with convex-surface type grid structure.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
The invention provides a kind of B4-Flash with convex surface grid structure, shown in reference picture 3, the grid structure is set
On an active area (active area, AA) substrate 10, formed in the active area substrate 10 of grid structure two bottom sides
There are source doping region (source) and drain doping region (drain), a ditch is formed between source doping region and drain doping region
Road (channel).One it is optional but simultaneously embodiment without limiting be, the raceway groove P-type channel (P-channel).
Wherein, above-mentioned grid structure is followed successively by tunnel oxide 11, charge storage layer 12, block media layer from bottom to top
13 and conductive layer 14.
In an embodiment of the present invention, tunnel oxide 11 is the convex-surface type structure of the lateral middle part protuberance of top surface two, while
The top surface of the tunnel oxide 11 is also a smooth convex cambered surface.Charge storage layer 12 is the lateral middle part protuberance of top surface two and bottom
Face is from the arch bridge-type structure of two lateral medial recess, while the top surface of the charge storage layer 12 and bottom surface are a smooth cambered surface
To be completely covered in the upper surface of tunnel oxide 11.
Further, an optional implementation method is that substrate 10 is both sides with the contact surface of the bottom of tunnel oxide 11
To the convex cambered surface that middle part is swelled, and then so that the lateral medial recess in bottom surface two of tunnel oxide 11, forms one and is deposited with electric charge
The shape identical tunnel oxide 11 of reservoir 12.It should be appreciated to those skilled in the art that tunnel oxide 11 and substrate 10
Contact surface for convex surface be only a preferably implementation method, the implementation method is not limited in actual applications, for example exist
In some other implementation method, the section that substrate 10 is contacted with tunnel oxide 11 has no effect on for horizontal plane to the present invention.
In an embodiment of the present invention, block media layer 13 and conductive layer 14 is identical with the shape of charge storage layer 12 and thickness
Degree is different.One optional but simultaneously implementation method is without limiting, and shape and the electric charge of block media layer 13 and conductive layer 14 are stored
The shape of layer 12 is identical and thickness is different, i.e., block media layer 13 also encircles bridge-like structure to be covered in charge storage layer 12 in one
Upper surface, likewise, conductive layer 14 also encircles bridge-like structure to be covered in the upper surface of block media layer 13 for one.Of the invention
In another implementation method, the two bottom sides of block media layer 13 are to medial recess being covered in the upper table of charge storage layer 12
Face, but the top planes of block media layer 13 are a horizontal plane, therefore it is covered in the conduction of 13 upper surface of block media layer
The bottom of layer 14 is also a horizontal plane；Meanwhile, when the bottom of conductive layer 14 is a horizontal plane, its top planes can be two lateral
The convex-surface type structure of middle part protuberance, or be horizontal plane.
In an embodiment of the present invention, one it is optional but simultaneously implementation method is without limiting, tunnel oxide 11 is oxidation
Silicon, conductive layer 14 is polysilicon layer (poly silicon), and block media layer 13 is silica or selects silica-nitridation
Silicon-silica (Oxide-Nitride-Oxide, abbreviation ONO) layer.From ONO three-deckers as the He of charge storage layer 12
Dielectric layer between conductive layer 14, this is that, because the brilliant combination of oxide layer and base is good compared with nitration case, and nitration case is placed in the middle, then can hinder
The extension of gear defect (such as pinhole), so three-decker complementary can lack, is conducive to boost device performance.
In embodiments of the invention, one optional but simultaneously implementation method is without limiting, and above-mentioned charge storage layer 12 can
From polysilicon layer or nanocrystalline (nanocrystalline).Current Flash devices typically use polysilicon as floating boom,
But the nanocrystalline material that can bring more preferable performance in the present invention, can be also used as the floating boom of Flash devices；Meanwhile, should
Charge storage layer 12 is the material layer with n-type doping type or p-type doping type, is doped by charge storage layer 12
Carry out the threshold voltage (Voltage threshold, Vt) of adjusting means.Optionally, N-type impurity includes phosphorus (P), arsenic (As) etc., P
Type impurity includes boron (B), boron fluoride (BF2) etc..
In one embodiment of the invention, the grid for preparing the floating boom B4-Flash devices with convex surface grid are a length of
50nm, the thickness that convex surface grid structure bends each layer is：The maximum gauge of tunnel oxide 11 is no more than in 5nm, further excellent
Choosing, the height of the top both sides of tunnel oxide 11 is 3nm；The thickness of charge storage layer 12 is 50-100nm, preferably
90nm；The thickness of conductive layer 14 is 150-200nm, preferably 175nm；In the present invention, because block media layer 13 is optional simultaneously
It is silica or ono dielectric layer, therefore thickness is also different in both cases：When block media layer is silica
When, block media 13 thickness of layer are 5-15nm, preferably 8nm；When block media layer 13 is ono dielectric layer, then the stop is situated between
The bottom silicon dioxide silicon thickness of matter layer 13 is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, top silicon dioxide silicon thickness
It is 2nm-5nm, 13 gross thickness of preferred block media layer are 15nm.
Each upper and lower contact surface degree of crook of layer is uniform, and charge storage layer 12, block media layer 13 and conductive layer 14 are everywhere
Thickness is uniform.
The operation principle with regard to B4-Flash devices provided by the present invention is described further below.Fig. 2 a show
Two steps that BTBT (Band-to-Band Tunneling)-HE is produced：(1) for BTBT is produced；(2) it is the acceleration of electronics.
Fig. 2 b show the energy band diagram of drain terminal, and Fig. 2 c show the energy band diagram of source, can learn that BTBT is by source voltage terminal according to Fig. 2 c
1.8V is suppressed.
The BTBT-HE that backgate bias is assisted is produced shown in model reference picture 2a to Fig. 2 c, wherein, 3 are expressed as depletion layer
(depletion layer), 4 is accumulation layer (accumulation layer), and 5 is the N-type ring-shaped area (N- for being close to source/drain
halo).The generation of B4-HEs needs two steps：1st, the generation of BTBT is controlled by vertical electric field (Vg-Vd)；2nd, produced
Depletion layer 3 in BTBT electronics accelerated by knot electric field (Vd-Vb).Source is tied electric field and is hung down because being applied with 1.8V voltages
Straight electric field is all weakened, and causes compiling to be suppressed.Under the assistance accelerated to BTBT-HE of such backgate bias, source and drain end
Voltage difference can so ensure that device size can be reduced with very little.
In the B4-Flash provided using the present invention when write operation is performed, a larger electricity is applied on conductive layer 14
Pressure, and source and drain doping area and substrate 10 are grounded, because tunneling effect makes electron tunneling cross tunnel oxide 11, store in electric charge
In accumulation layer 12；When erasing, apply a negative electricity and be depressed into conductive layer 14, and source and drain doping area and substrate 10 are grounded, electric charge is deposited
The electronics reverse tunnel of reservoir 12 returns substrate 10.In the floating boom B4-Flash devices with convex surface grid, because power line is
Perpendicular to dielectric layer surface distribution, so in the structure of convex surface grid, the power line between substrate and grid is no longer as in Fig. 1
Parallel distribution like that in typical floating boom B4-Flash devices, but deposited perpendicular to block media layer 13, electric charge from conductive layer 14
Reservoir 12 and tunnel oxide 11 simultaneously focus on substrate 10.As shown in figure 3, the density of power line represents the size of electric-field intensity,
Such electric force lines distribution makes grid be continuously increased to the electric-field intensity of substrate.In erasing, charge storage layer to lining can be made
The tunnelling at bottom, such that it is able to suppress even to eliminate the appearance for wiping saturation, is carried more than the tunnelling that charge storage layer is injected from gate pole
Erasing speed high.
The B4-Flash of convex surface grid structure provided by the present invention can completely compatible existing CMOS making technologies, processing procedure
Change small, can be prepared based on gate first or gate last techniques, while the structure of the present invention is applied into HKMG
Flash preparation technologies in be equally applicable, and can effectively reduce device critical dimension (Critical Dimension,
CD)。
In sum, because the B4-Flash of present invention offer is due to the grid structure with convex surface, can deposit electric charge
Reservoir is more than the tunnelling that charge storage layer is injected from gate pole to the tunnelling of substrate, such that it is able to suppress even to eliminate erasing saturation
Occur, improve erasing speed.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (13)
1. a kind of B4-Flash with convex-surface type grid structure, it is characterised in that the grid structure is arranged at an active area
Substrate, source doping region and drain doping region are formed with the active area substrate of the grid structure two bottom sides,
A raceway groove is formed between the source doping region and drain doping region；
The grid structure is followed successively by tunnel oxide, charge storage layer, block media layer and conductive layer from bottom to top；
Wherein, the tunnel oxide is the convex-surface type structure of the lateral middle part protuberance of top surface two, and the tunnel oxide top surface
It is a smooth convex cambered surface；
The charge storage layer is the arch bridge-type structure of the lateral middle part protuberance of top surface two and the lateral medial recess in bottom surface two, the electricity
The top surface of lotus accumulation layer and bottom surface are a smooth cambered surface to be completely covered in the upper surface of the tunnel oxide；
The polysilicon or nanocrystalline that the storage medium layer is adulterated from N-type or p-type.
2. B4-Flash as claimed in claim 1, it is characterised in that the block media layer and conductive layer with the electric charge
The shape of accumulation layer is identical and thickness is different.
3. B4-Flash as claimed in claim 1, it is characterised in that the substrate is silicon substrate.
4. B4-Flash as claimed in claim 1, it is characterised in that the tunnel oxide is silica.
5. B4-Flash as claimed in claim 1, it is characterised in that the conductive layer is polysilicon.
6. B4-Flash as claimed in claim 1, it is characterised in that the raceway groove is P-type channel.
7. B4-Flash as claimed in claim 1, it is characterised in that substrate contact with the tunnel oxide bottom
Face is the convex cambered surface of two lateral middle part protuberances.
8. B4-Flash as claimed in claim 1, it is characterised in that the block media layer is silicon dioxide layer or titanium dioxide
Silicon-silicon nitride-silicon dioxide (ONO) layer.
9. B4-Flash as claimed in claim 1, it is characterised in that the charge storage layer thickness is 50-100nm, described
Conductive layer thickness is 150-200nm.
10. B4-Flash as claimed in claim 8, it is characterised in that described when block media layer is for silica
Block media thickness degree is 5-15nm；
When the block media layer for silicon oxide-silicon nitride-silicon dioxide layer when, then the block media layer bottom silicon dioxide
The thickness of silicon is 2nm-5nm, and the thickness of middle nitride silicon is 6nm-10nm, and the thickness of top silicon dioxide silicon is 2nm-5nm.
11. B4-Flash as claimed in claim 1, it is characterised in that the maximum gauge of the tunnel oxide be no more than in
5nm。
12. B4-Flash as claimed in claim 1, it is characterised in that N-type is carried out to the storage medium layer from phosphorus or arsenic
Doping.
13. B4-Flash as claimed in claim 1, it is characterised in that entered to the storage medium layer from boron or boron fluoride
Row p-type is adulterated.
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| KR102559237B1 (en) * | 2018-03-12 | 2023-07-26 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211913A (en) * | 2006-12-27 | 2008-07-02 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| CN102290444A (en) * | 2011-08-31 | 2011-12-21 | 上海宏力半导体制造有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory |
| CN102683398A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) gate structure, manufacture method, and semiconductor device |
| CN102832175A (en) * | 2012-09-11 | 2012-12-19 | 上海华力微电子有限公司 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
Family Cites Families (1)
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| US6580135B2 (en) * | 2001-06-18 | 2003-06-17 | Macronix International Co., Ltd. | Silicon nitride read only memory structure and method of programming and erasure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211913A (en) * | 2006-12-27 | 2008-07-02 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
| CN102290444A (en) * | 2011-08-31 | 2011-12-21 | 上海宏力半导体制造有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory |
| CN102683398A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) gate structure, manufacture method, and semiconductor device |
| CN102832175A (en) * | 2012-09-11 | 2012-12-19 | 上海华力微电子有限公司 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
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