CN104241246A - Electric fuse structure, forming method of electric fuse structure, semiconductor device, and forming method of semiconductor device - Google Patents
Electric fuse structure, forming method of electric fuse structure, semiconductor device, and forming method of semiconductor device Download PDFInfo
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- CN104241246A CN104241246A CN201310231978.4A CN201310231978A CN104241246A CN 104241246 A CN104241246 A CN 104241246A CN 201310231978 A CN201310231978 A CN 201310231978A CN 104241246 A CN104241246 A CN 104241246A
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Abstract
The invention provides an electric fuse structure, a forming method of the electric fuse structure, a semiconductor device and a forming method of the semiconductor device. The forming method of the electric fuse structure comprises the steps that firstly, a nano-wire is formed on a semiconductor substrate; secondly, the substrate is etched by partial thickness so that the nano-wire can protrude out of the surface of the semiconductor substrate; finally, ions are doped at the two ends of the nano-wire to form the electric fuse structure. According to the technical scheme, the method is simple, the formed electric fuse structure is novel, and the diversity of the formed electric fuse structure is achieved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to electric fuse structure and forming method thereof, semiconductor device and forming method thereof.
Background technology
In integrated circuit fields, fuse (Fuse) refers to some connecting lines that can fuse formed in integrated circuits.At first, fuse is the redundant circuit for connecting in integrated circuit, finds that integrated circuit has defect, just utilize fuse reparation or replace defective circuit once detect.Fuse is generally laser fuse (Laser Fuse) and electric fuse (Electrical Fuse, hereinafter referred to as E-fuse) two kinds.Along with the development of semiconductor technology, E-fuse instead of laser fuse gradually.
General, electric fuse structure can be made with metal (aluminium, copper etc.) or silicon, in prior art, a kind of typical electric fuse structure as shown in Figure 1, this electric fuse structure is formed on fleet plough groove isolation structure (STI) 100 in the semiconductor substrate, it comprises anode 101 and negative electrode 103, and the fuse 102 of the fine strip shape be connected with both between anode 101 and negative electrode 103, its Anodic 101 and negative electrode 103 surface have contact plunger 104.Time between anode 101 and negative electrode 103 by larger immediate current, fuse 102 is fused.Wide and the thickness according to the actual bar of fuse 102, the electric current needed for concrete blow out fuse 102 is not quite similar, and is generally hundreds of milliampere.Fuse 102 is not by under the state that fuses, and electric fuse structure place is low resistance state (if resistance is R), and when fuse 102 is by under the state after fusing, electric fuse structure place is high-impedance state (if resistance is for infinitely great).
Can realize by electric current the characteristic that low-resistance transforms to high resistant because it has, electric fuse structure is except the application in redundant circuit, also have and apply widely, as: built-in self-test (Build in self test, be called for short BIST) technology, self-repair technology, one-time programming (One Time Program, be called for short OTP) chip, SOC (system on a chip) (System On Chip, be called for short SoC) etc.
In prior art, with reference to figure 1, the formation method of electric fuse structure is as follows:
Step S11, provides Semiconductor substrate, forms fleet plough groove isolation structure 100 in described Semiconductor substrate;
Step S12, form polysilicon layer on described fleet plough groove isolation structure 100 surface, form patterned mask layer on the surface of polysilicon layer, with described patterned mask layer for mask etching polysilicon layer, formation two ends are roomy, and the semiconductor structure of the intermediate elongated be connected with two ends.
Step S13, remove described mask layer, metal silicide is formed at described semicon-ductor structure surface, metal silicide surface at the two ends of described semiconductor structure forms conductive plunger 104, form anode 101 and negative electrode 103, the elongated semiconductor structure between described anode 101 and negative electrode 103 is fuse 102.
But electric fuse structure that prior art is formed and forming method thereof is single, and usually forms electric fuse when forming planar transistor, such as, at formation non-planar transistor, (such as all-around-gate transistor (Gate-All-Around, GAA) forms electric fuse, becomes the problem needing solution badly.
Summary of the invention
The problem that the present invention solves is to provide electric fuse structure and forming method thereof, semiconductor device and forming method thereof, realizes the variation of electric fuse structure and formation method.
For solving the problem, The embodiment provides a kind of formation method of electric fuse structure, comprising:
Semiconductor substrate is provided;
Nano wire is formed in described Semiconductor substrate;
The described Semiconductor substrate of etched portions thickness, make described nano wire be raised in Semiconductor substrate, and the two ends of described nano wire is supported by Semiconductor substrate, has interval between mid portion and described Semiconductor substrate;
Carry out ion doping to the two ends of described nano wire, form negative electrode and the anode of electric fuse structure, the region on described nano wire between negative electrode and anode is fuse area.
Alternatively, by Doped ions in described Semiconductor substrate, described nano wire is formed.
Alternatively, the ion of doping at least comprises B.
Alternatively, described ion also comprises C, Si, N, Ge.
Alternatively, the described Semiconductor substrate of etched portions thickness, makes after described nano wire is raised in Semiconductor substrate, also to comprise step:
Carry out recrystallization annealing temperature.
Alternatively, the method for the described Semiconductor substrate of etched portions thickness is wet etching.
Alternatively, the etching agent that described wet etching adopts comprises THAM or THEM.
Alternatively, also comprise: before the negative electrode forming electric fuse structure and anode, the zone line to described nano wire carries out ion doping, forms the fuse area doped with ion.
Alternatively, after formation is doped with the fuse area of ion, described nano wire is repaired.
Alternatively, the method for described reparation is thermal oxidation technology or annealing process.
Alternatively, also comprise: form multiple conductive plunger, described multiple conductive plunger is electrically connected with described negative electrode and anode respectively.
Present invention also offers a kind of electric fuse structure, comprising:
Semiconductor substrate;
Nano wire, is raised in described semiconductor substrate surface and two ends are supported by described Semiconductor substrate, has interval between the mid portion of nano wire and described Semiconductor substrate;
Negative electrode and anode, lay respectively at the two ends of described nano wire;
Fuse area, the negative electrode on described nano wire and between anode.
Alternatively, described fuse area is interior doped with ion.
Alternatively, also comprise: the interlayer dielectric layer covering described negative electrode, anode and fuse area; Run through multiple conductive plungers of described interlayer dielectric layer, described multiple conductive plunger is electrically connected with described negative electrode and anode respectively
Invention further provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided;
The first nano wire and the second nano wire is formed in described Semiconductor substrate;
The described Semiconductor substrate of etched portions thickness, described first nano wire and the second nano wire is made to be raised in Semiconductor substrate, and the two ends of described first nano wire and the second nano wire support by Semiconductor substrate, all have interval between mid portion and described Semiconductor substrate;
Form the grid structure of coated described first nanowire surface;
Carry out ion doping at the two ends of the first nano wire, form source electrode and the drain electrode of all-around-gate transistor;
Ion doping is carried out at two ends to described second nano wire, and form negative electrode and the anode of electric fuse structure, the region on described second nano wire between negative electrode and anode is fuse area.
Alternatively, Doped ions in described Semiconductor substrate, forms described first nano wire and the second nano wire.
Alternatively, described ion at least comprises B.
Alternatively, described ion also comprises C, Si, N, Ge.
Alternatively, the described Semiconductor substrate of etched portions thickness, makes after described first nano wire and the second nano wire be raised in Semiconductor substrate, also to comprise step:
Carry out recrystallization annealing temperature.
Alternatively, the method for the described Semiconductor substrate of etched portions thickness is wet etching.
Alternatively, the etching agent that described wet etching adopts comprises THAM or THEM.
Alternatively, the described source electrode of formation all-around-gate transistor and the negative electrode of the step of drain electrode and described formation electric fuse structure and the step of anode are carried out simultaneously.
Alternatively, also comprise: formed before grid structure, the mid portion to described first nano wire and the second nano wire carries out ion doping, form mid portion doped with the first nano wire of ion and mid portion the second nano wire doped with ion.
Alternatively, to described first nano wire and the ionic type that the mid portion of the second nano wire adulterates and the ionic type adulterated at the two ends of the first nano wire and the ionic type that adulterates at the two ends of described second nano wire identical.
Alternatively, also comprise: form mid portion doped with the first nano wire of ion and mid portion doped with after the second nano wire of ion, described first nano wire and the second nano wire are repaired.
Alternatively, the method for described reparation is annealing process or thermal oxidation technology.
Alternatively, also comprise: form the interlayer dielectric layer covering described all-around-gate transistor and electric fuse structure; In described interlayer dielectric layer, form multiple conductive plunger, described multiple conductive plunger is electrically connected with the source electrode of described all-around-gate transistor and the negative electrode of drain electrode and electric fuse structure and anode respectively.
In addition, present invention also offers a kind of semiconductor device, comprising:
Semiconductor substrate;
Full encirclement transistor, is positioned at described semiconductor substrate surface;
Described full encirclement transistor comprises the source electrode and the drain electrode that the first nano wire, the grid structure of coated described first nano wire, described first nano wire are positioned at described grid structure both sides, and the channel region that on described first nano wire, region is formed between described source electrode and drain electrode;
Electric fuse structure, is positioned at described semiconductor substrate surface, isolated with described full encirclement transistor;
Described electric fuse structure comprises the second nano wire, is positioned at negative electrode and the anode at described second nano wire two ends and the fuse area on described nano wire between described negative electrode and anode.
Alternatively, source electrode and the drain electrode of described all-around-gate transistor and the anode of electric fuse structure identical with the ionic type adulterated in negative electrode.
Alternatively, doped with ion in the channel region of described all-around-gate transistor and the fuse area of electric fuse structure, the anode of described channel region and the ionic type of doping in fuse area and the source electrode of all-around-gate transistor and drain electrode and electric fuse structure is identical with the ionic type adulterated in negative electrode.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of electric fuse structure, first form nano wire on a semiconductor substrate, the Semiconductor substrate of etched portions thickness afterwards, make described nano wire be raised in semiconductor substrate surface, then at the two ends Doped ions of described nano wire, to form electric fuse structure.Technique scheme method is simple, and the electric fuse structure of formation is novel, achieves the diversity of the electric fuse structure of formation.
Further, by Doped ions in described Semiconductor substrate to form nano wire, form protruding nano wire by the Semiconductor substrate of etched portions thickness afterwards, and carry out recrystallization annealing temperature and impel nano wire crystallization.Adopt such scheme, even if common body silicon substrate, body germanium substrate or germanium silicon substrate also can form the electric fuse structure of novel structure, reduce further cost prepared by electric fuse structure, expand the range of application of electric fuse structure.
The nano wire that the electric fuse structure of the embodiment of the present invention is adulterated by two ends is formed, and its structure is simple, the various structures of electric fuse.
In the formation method of semiconductor device, form the first nano wire and the second nano wire be separated with it on a semiconductor substrate, described first nano wire follow-up formation all-around-gate transistor, and the follow-up formation electric fuse structure of described second nano wire, achieve the diversity of the formation method of semiconductor device, and the electric fuse structure formed is novel; In addition because described electric fuse structure and all-around-gate transistor are arranged in same semi-conductive substrate, the novel structure of described semiconductor device, range of application is wider.
Further, the described source electrode of formation all-around-gate transistor and the negative electrode of the step of drain electrode and described formation electric fuse structure and the step of anode are carried out simultaneously, namely the step forming described electric fuse structure colonizes among the step of formation all-around-gate transistor, formed in the process of described semiconductor device, extra processing step can not be increased and production cost low.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the electric fuse of prior art;
Fig. 2 A to Figure 15 C is the cross-sectional view of the forming process of a kind of semiconductor device of first embodiment of the invention;
Figure 16 ~ 17 are cross-sectional view of the forming process of another kind of semiconductor device in first embodiment of the invention;
Figure 18 is the cross-sectional view of the forming process of a kind of electric fuse structure in second embodiment of the invention;
Figure 19 is the cross-sectional view of the forming process of another kind of electric fuse structure in second embodiment of the invention.
Embodiment
As described in background, prior art forms electric fuse when forming planar transistor usually, and its formation method and structure are comparatively single.
After research, inventor provide a kind of electric fuse structure and forming method thereof, semiconductor device and forming method thereof, electric fuse structure can be formed while formation all-around-gate transistor, thus effectively realize the method and structure diversity forming semiconductor device.
In the formation method of electric fuse structure, first in Semiconductor substrate, form nano wire, form two ends by the described Semiconductor substrate of etched portions thickness and there is Semiconductor substrate support, the spaced nano wire of tool between centre and Semiconductor substrate; Afterwards, by the doping of nano wire two ends, form negative electrode and the anode of electric fuse structure respectively, and the fuse area between cathode and anode.
In the formation method of semiconductor device, two sections of nano wires are formed in Semiconductor substrate, to form two ends by Semiconductor substrate described in etched portions there is Semiconductor substrate support afterwards, middle with Semiconductor substrate tool spaced two sections of nano wires being raised in semiconductor substrate.Wherein one section of nanowire surface forms grid structure, and forms full source electrode and drain electrode of surrounding transistor at the two ends Doped ions of this section of nano wire; And after another section of nano wire two ends Doped ions, formation comprises two ends and is respectively negative electrode and anode, and be the electric fuse structure of fuse area between negative electrode and anode.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First embodiment
In the first embodiment of the present invention, inventor provide a kind of formation method at semiconductor device, while formation all-around-gate transistor, form electric fuse structure.
Incorporated by reference to reference to figure 2A, 2B, 2C, wherein, Fig. 2 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention, and Fig. 2 B is the cross-sectional view of Fig. 2 A along X-X ' direction; Fig. 2 C is the cross-sectional view of Fig. 2 A along Y-Y ' direction.
There is provided Semiconductor substrate 200, described Semiconductor substrate 200 for providing platform for subsequent technique, and forms nano wire.Described Semiconductor substrate 200 comprises first area I and second area II, and wherein said first area I is for the formation of all-around-gate transistor, and described second area II is for the formation of electric fuse structure.
Described Semiconductor substrate 200 can be the silicon of monocrystalline, polycrystalline or non crystalline structure, germanium, GaAs or SiGe (SiGe) compound, also can be the substrate that silicon-on-insulator (SOI) is made.Existing substrate all can be used as substrate of the present invention, will not enumerate at this.
In embodiments of the invention, described Semiconductor substrate 200 is monocrystalline substrate, and compared to SOI substrate, monocrystalline substrate can save the preparation cost of semiconductor device.Described monocrystalline substrate, alternatively doped with P type ion, is N-Sub.
Please continue to refer to Fig. 2 A, 2B, 2C, respectively to Doped ions in the subregion of described first area I and second area II, thus form the first nano wire 210 and the second nano wire 220.Described first nanometer 210 after Doped ions and the second nanometer 220 are amorphous silicon structures.
In the present embodiment, can first at described Semiconductor substrate 200 surface coverage photoresist layer, and after photoetching process, graphical described photoresist layer exposes described first nano wire 210 and the second nano wire 220, and with photoresist layer be mask to Doped ions in described Semiconductor substrate 200 to form described first nanometer 210 and the second nanometer 220.
In the present embodiment, the ion be doped in Semiconductor substrate 200 at least comprises B, except B, also can comprise C, Si, N, Ge.
It should be noted that, in other embodiments except the present embodiment, the advanced patterning process by other determines the position of described first nanometer 210 and the second nanometer 220, and carries out ion doping technique, form described first nanometer 210 and the second nanometer 220, do not repeat them here.
Please refer to shown in Fig. 5 A ~ 5C, Fig. 5 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 5 B is the cross-sectional view of Fig. 6 A along X-X ' direction; Fig. 5 C is the cross-sectional view of Fig. 5 A along Y-Y ' direction.
Etch described Semiconductor substrate 200, the described Semiconductor substrate 200 of remove portion thickness, the Semiconductor substrate 200a after making described first nano wire 210 and the second nano wire 220 be raised in etching.Described first nano wire 210 and the second nano wire 220 have support 500 for two ends, and zone line and described Semiconductor substrate 200a have interval 230, thus in unsettled structure.
In this enforcement, etch described Semiconductor substrate 200, formation described first nano wire 210 of hanging structure and the concrete steps of the second nano wire 220 comprise:
First reference diagram 3A, 3B, 3C, wherein, Fig. 3 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 3 B is the cross-sectional view of Fig. 3 A along X-X ' direction; Fig. 3 C is the cross-sectional view of Fig. 3 A along Y-Y ' direction.
In described Semiconductor substrate 200, be positioned at above described first nanometer 210 and the second nanometer 220 and cover the first mask layer 301, and with described first mask layer 301 for Semiconductor substrate described in mask etching 200, with the Semiconductor substrate 200 of the segment thickness except removing described first nanometer 210 and the second nanometer 220.
Wherein, the degree of depth of the first nanometer 210 and the second nanometer 220 is stated described in the thickness removing described Semiconductor substrate 200 is greater than, to form convex described first nanometer 210 and the second nanometer 220 and the pedestal 200b for supporting described first nanometer 210x and the second nanometer 220x, described pedestal 200b material is identical with described Semiconductor substrate 200 material.
In the present embodiment, the technique etching described Semiconductor substrate 200 can adopt anisotropic dry etch process or wet-etching technology.Particularly, dry etching agent can comprise CF
4, SF
6, O
2deng gas.
It should be noted that, in other embodiments of the invention, all right: before formation first mask layer 300, form the hard mask layer (not shown) covering described semiconductor-on-insulator substrate surface.The material of described hard mask layer is silica, silicon nitride or silicon oxynitride, and for the protection of Semiconductor substrate 200 surface, the forming process of described hard mask layer does not repeat them here.But do not arrange described hard mask layer can't affect in the present embodiment, in described Semiconductor substrate 200, determine that the object of the first nanometer 210 and the second nanometer 220 realizes.
Referring again to Fig. 4 A, 4B, 4C, wherein, Fig. 4 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 4 B is the cross-sectional view of Fig. 4 A along X-X ' direction; Fig. 4 C is the cross-sectional view of Fig. 4 A along Y-Y ' direction.
Remove described first mask layer 301, and form the second mask layer 302 at the two ends of the pedestal 200b of convex described first nanometer 210 and the second nanometer 220 and below.
In conjunction with reference to shown in figure 4B and 4C, described second mask layer 302 comprises the sidepiece 3023 of both sides, the end 3022 at two ends of the pedestal 200b being covered in described first nanometer 210 and the second nanometer 220 and below along YY ' direction, and the covering part 3021 be positioned at above the first nanometer 210 and the second nanometer 220 two ends, described second mask layer 302 is the two ends of the pedestal 200b of coated described first nanometer 210 of semi-surrounding structure and the second nanometer 220 and below.
Continue with reference to figure 5A, 5B, 5C, with described second mask layer 302 for mask, adopt the pedestal 200b that wet-etching technology continues the described Semiconductor substrate of etching and is positioned at below described first nanometer 210 and the second nanometer 220.To form Semiconductor substrate 200a and two ends have support 500, middle the first nano wire 210 and the second nano wire 220 in vacant state.
In the present embodiment, described wet-etching technology is alternatively with TMAH(tetramethyl aqua ammonia) or TMEH(tetraethyl aqua ammonia) for etching agent.
In etching process; described pedestal 200b two ends are retained based on described second mask layer 302; and pedestal 200b mid portion is removed; support 500 is formed at the two ends of described first nanometer 210x and the second nanometer 220; and in the below of described first nano wire 210 and the second nano wire 220, between supporting 500 at corresponding two, form interval 230.
It should be noted that; in other embodiments except the present embodiment; while the two ends of the pedestal 200b of coated described first nanometer 210 of described second mask layer 302 and the second nanometer 220 and below; also can cover the surface of described Semiconductor substrate; and the second mask layer thickness covering described Semiconductor substrate is less than described support 200b thickness; thus guarantee to form support 500, these simply change all in protection scope of the present invention.
Again combine with reference to 5A ~ 5C and 6A ~ 6C, the interval 230 formed below described first nano wire 210x and the second nano wire 220x, be conducive to the follow-up gate dielectric layer and the gate electrode layer that have enough space formation to cover described first nano wire 210x.Wherein, the height at described interval 230 is chosen as about 1 μm.
It should be noted that, in other embodiments of the invention, as long as make the first nano wire 210 and the second nano wire 220 unsettled, the follow-up gate dielectric layer and gate electrode layer having enough space to be formed to cover described first nano wire 210.Described interval 230 height and the size not circumscribed for the support 500 that supports two described nano wires.
In the present embodiment, described first nano wire 210 and the second nano wire 220 are amorphous silicon material.
The material of described first mask layer 301, second mask layer 302 comprises silicon nitride, all kinds of mask layer material such as carborundum or photoresistance.
The techniques such as in the present embodiment, the material of described first mask layer 301 and the second mask layer 302 is photoresistance (PR), and its formation process is exposure, development, do not repeat them here.
Please refer to Fig. 6 A, 6B, 6C, wherein, Fig. 6 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 6 B is the cross-sectional view of Fig. 6 A along X-X ' direction; Fig. 6 C is the cross-sectional view of Fig. 6 A along Y-Y ' direction.
After removing described second mask layer 302 shown in Fig. 5, carry out crystallization annealing process, impel described first nano wire 210 and the second nano wire 220 crystallization in amorphous silicon structures, form the first nano wire 210a and the second nano wire 220a.Described first nano wire 210a is used for follow-up formation all-around-gate transistor, and described second nano wire 220a is used for follow-up formation electric fuse structure.
In the present embodiment, described crystallization annealing process comprises: be 600 DEG C ~ 950 DEG C by the first nano wire 210 and the second nano wire 220 in temperature, pressure is heat 1 ~ 60 minute under 0.1 ~ 60 holder condition, make the first nano wire 210 and the second nano wire 220 crystallization of amorphous silicon structures, form described first nano wire 210a and the second nano wire 220a.
Incorporated by reference to reference to figure 7A, 7B, 7C, wherein, Fig. 7 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 7 B is the cross-sectional view of Fig. 7 A along X-X ' direction; Fig. 7 C is the cross-sectional view of Fig. 7 A along Y-Y ' direction.
On described Semiconductor substrate 200a, form the 3rd mask layer 310 covering the two ends of described first nano wire 210a and the two ends of the second nano wire 220a.In embodiments of the invention, the material of described 3rd mask layer 310 is chosen as resistance material, and its formation process comprises the techniques such as exposure, development.
With described 3rd mask layer 310 for mask, shown in the first nano wire 210a that two ends have support to centre is unsettled and second nano wire 220a(Fig. 6 A ~ 6C) mid portion doping, form mid portion doped with the first nano wire 210b of ion and mid portion the second nano wire 220b doped with ion.
After the mid portion Doped ions of described first nano wire 210a, effectively can improve the carrier mobility of the channel region of the all-around-gate transistor of follow-up formation.First nano wire 210b can be used as the channel region of the all-around-gate transistor of follow-up formation doped with the mid portion of ion.After mid portion Doped ions to described second nano wire 220a(as shown in figs. 6 a and 6 c), when source electrode and the drain electrode applying electric current of the electric fuse structure to follow-up formation, the ion of doping can be impelled to assemble in one end of the second nano wire 220b, to cause the change of the second nano wire 220b resistance everywhere on Y-Y ' direction, thus the second nano wire 220b somewhere resistance on Y-Y ' direction is made to increase to certain value or fuse.Second nano wire 220b can be used as the fuse area of the electric fuse structure of follow-up formation doped with the mid portion of ion.
The ionic type of described doping can be selected according to actual conditions, both can be N-type ion, also can be P type ion.In an embodiment of the present invention, N-type heavy doping can be selected.
It should be noted that, in the present embodiment, mid portion is still square doped with the second nano wire 220b of ion along the section shape in X-X ' direction doped with the first nano wire 210b of ion, mid portion.
It should be noted that, in other embodiments of the invention, shown in Fig. 7 A ~ 7C to shown in the first nano wire 210a and second nano wire 220a(Fig. 6 A ~ 6C) mid portion Doped ions perform with the step alternative forming the first nano wire 210b and the second nano wire 220b.Mid portion Doped ions to the first nano wire 210a and the second nano wire 210b effectively can improve the all-around-gate transistor of follow-up formation and the performance of electric fuse structure, even if but do not perform above-mentioned steps also can not affect the present invention formed all-around-gate transistor and electric fuse structure object realize.
Incorporated by reference to reference to figure 8A, 8B, 8C, wherein, Fig. 8 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Fig. 8 B is the cross-sectional view of Fig. 8 A along X-X ' direction; Fig. 8 C is the cross-sectional view of Fig. 8 A along Y-Y ' direction.
Formed mid portion there is the first nano wire 210b(of doping as shown in Fig. 7 A, 7B, 7C) and mid portion there is the second nano wire 220b(of doping as shown in Fig. 7 A, 7B, 7C) after, remove described 3rd mask layer 310(as shown in Fig. 7 A, 7B, 7C).The technique of described 3rd mask layer 310 of described removal is cineration technics or etching technics, and the technique removing described 3rd mask layer 310 is well known to those skilled in the art, and does not repeat them here.
The surface of described first nano wire 210b and the second nano wire 220b and two end faces are repaired, forms the repair layer 240 of the described first nano wire 210b of parcel, the second nano wire 220b and described Semiconductor substrate 200a.
Inventor finds, in previous process, formed to Doped ions in described first nano wire 210a as shown in figs. 6 a-6 c and the second nano wire 220a mid portion doped with in the first nano wire 210b of ion and the process of the second nano wire 220b produce that powerful impulsive force easily causes follow-up formation damage is caused to the first nano wire 210b shown in Fig. 7 A ~ 7C and the second nano wire 220b surface; And, when removing described 3rd mask layer 310, also easy damage being caused to the first nano wire 210b and the second nano wire 220b surface and two respective end faces, thus affecting the performance of the semiconductor device of follow-up formation.If repaired the first nano wire 210b damaged and the second nano wire 220b surface and two end faces, contribute to the performance improving semiconductor device.Described reparation can adopt annealing process or thermal oxidation technology.
In the present embodiment, thermal oxidation technology is preferably adopted to be repaired the first nano wire 210b and the second nano wire 220b surface and two end faces.Concrete thermal oxidation technology condition comprises: temperature is 1000 ~ 1200 DEG C, and pressure is 0.1 ~ 60 holder, and the time is 1 ~ 60 minute, and described thermal oxidation technology actual conditions can be determined according to actual conditions.
After thermal oxidation technology, not only can form the repair layer 240 of the second nano wire 220b of the described first nano wire 210b of parcel and doping, and the first nano wire 210c and the second nano wire 220c becomes circle along the cross sectional shape in X-X ' direction from square after repairing, this structure can increase the grid width of all-around-gate transistor further, improves the performance of all-around-gate transistor in semiconductor device.In the present embodiment, the material of described repair layer 240 is silica, and described repair layer 240 obtains by after oxidized portion first nano wire 210b and part second nano wire 220b.
It should be noted that, the step of above-mentioned formation repair layer 240 can optionally perform.Formation repair layer 240 contributes to the damage that reparation abovementioned dopant technique causes nano wire, is beneficial to the performance improving semiconductor device.If but do not form the object realization that described repair layer also can not affect the present embodiment follow-up formation all-around-gate transistor and electric fuse structure.
Please refer to Fig. 9 A, 9B, 9C, wherein, Fig. 9 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention, and, for ease of understanding the present invention, grid structure in Fig. 9 A is shown in broken lines, and in Fig. 9 B X-X ' pointing needle right be the cross-sectional view of the first nano wire 211C; Fig. 9 C is the cross-sectional view of Fig. 9 A along Y-Y ' direction.
After repairing formation first nano wire 210c and the second nano wire 220c, remove repair layer 240, form the grid structure 250 covering described first nano wire 210c surface.
Wherein, the forming step of described grid structure 250 comprises: form the gate dielectric layer 251 covering described first nano wire 210c surface; Afterwards, the gate electrode layer 252 covering described gate dielectric layer 251 is formed.Wherein, the material of described gate dielectric layer 251 is silica or high K dielectric, and the material of described gate electrode layer 252 is polysilicon or metal, does not repeat them here.
It should be noted that, because the 2nd II also need not form all-around-gate transistor, therefore, before formation grid structure 250, can first adopt the 4th mask layer 320 to cover the second nano wire 220c of second area II.
Incorporated by reference to reference to figure 10A, 10B, 10C, wherein, Figure 10 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 10 B is the cross-sectional view of Figure 10 A along X-X ' direction; Figure 10 C is the cross-sectional view of Figure 10 A along Y-Y ' direction.
Grid structure 250 described in etched portions exposes the two ends of described first nano wire 210c, and the sidewall of remaining grid structure 250 forms side wall 260 after etching, exposes the two ends 211c of described first nano wire 210c simultaneously.Gate electrode layer 252 after etching in remaining grid structure 250 is follow-up for the grid as all-around-gate transistor.Described side wall 260 is not damaged for protecting remaining grid structure 250 during follow-up doping, and defines source electrode and the drain electrode of the follow-up full encirclement transistor that will be formed with the first exposed nano wire 210c two ends 211c.The material of described side wall 260 is silicon nitride, silicon oxynitride etc.
Please refer to Figure 11 A, 11B, 11C, wherein, Figure 11 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 11 B is the cross-sectional view of Figure 11 A along X-X ' direction; Figure 11 C is the cross-sectional view of Figure 11 A along Y-Y ' direction.
Remove described 4th mask layer 320, and form the 5th mask layer 330 being positioned at the second nano wire 220c surface, described 5th mask layer 330 covers the overlying regions of Doped ions in the middle of described second nano wire 220c, and exposes the two ends of the second nano wire 220c.In embodiments of the invention, described 5th mask layer 330 is chosen as photoresist layer.
It should be noted that, all the other except this enforcement are not in the embodiment of the middle part Doped ions of the second nano wire 220a shown in Fig. 5, described 5th mask layer 330 need cover described second nano wire 220a zone line, just can for the negative electrode of follow-up formation electric fuse structure and anode to expose described second nano wire 220a two ends.
With described grid structure 250, side wall 260 and the 5th mask layer 330 for mask, adulterate to the two ends 211c of described first nano wire 210c exposed and the two ends 221c of the second nano wire 220c, form the first source region 213 and the first drain region 212 that are positioned at first area I and the second source region 223 and the second drain region 222 being positioned at second area II.
Described first source region 213 and the first drain region 212 for follow-up formation as the source electrode of all-around-gate transistor and drain electrode.Described second source region 223 and the second drain region 222 are for the follow-up negative electrode as electric fuse structure and anode, and follow-up described negative electrode and anode are electrically connected with conductive plunger separately, make the fuse area inside between negative electrode and anode have electric current to pass through.
In embodiments of the invention, described first source region, drain region 212, second, source region 213, first 223 and the second drain region 222 are formed in same processing step, namely carry out simultaneously, can not increase extra processing step.
It should be noted that, in an embodiment of the present invention, the first nano wire 210c that unsettled to centre and two ends have a support and the ionic type that the mid portion of the second nano wire 220c adulterates and the ionic type adulterated in the two ends to the first nano wire 210c and the ionic type adulterated to the two ends of described second nano wire 220c identical.
Please refer to Figure 12 A, 12B, 12C, wherein, Figure 12 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 12 B is the cross-sectional view of Figure 12 A along X-X ' direction; Figure 12 C is the cross-sectional view of Figure 12 A along Y-Y ' direction.
Form the metal silicide layer 270 covering described first source region, drain region 212, second, source region 213, first 223 and the second surface, drain region 222.Described metal silicide layer 270 is for reducing the conductive plunger of follow-up formation and the contact resistance of interface between described first source region, drain region 222, second, source region 213, first 223 and the second drain region 222.
Please refer to Figure 13 A, 13B, 13C, wherein, Figure 13 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 13 B is the cross-sectional view of Figure 13 A along X-X ' direction; Figure 13 C is the cross-sectional view of Figure 13 A along Y-Y ' direction.
After forming metal silicide layer 270, remove the 5th mask layer 330 as shown in Figure 12 A and 12C.The technique removing described 5th mask layer 330 is etching technics or cineration technics, does not repeat them here.
Incorporated by reference to reference to figure 14A, 14B, 14C, wherein, Figure 14 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 14 B is the cross-sectional view of Figure 15 A along X-X ' direction; Figure 14 C is the cross-sectional view of Figure 15 A along Y-Y ' direction.
Form the interlayer dielectric layer 400 covering described grid structure 250, side wall 260, metal silicide layer 270 and Semiconductor substrate 200a surface.
Described interlayer dielectric layer 400 is for the adjacent conducting element such as conductive plunger, all-around-gate transistor of follow-up isolation.The material of described interlayer dielectric layer 400 is silica, silicon nitride or silicon oxynitride etc., and its formation process is chemical vapor deposition method, does not repeat them here.
In embodiments of the invention, the material of described interlayer dielectric layer 400 is silicon oxynitride, further, described interlayer dielectric layer 400 fills full described interval 230, wraps up the second nano wire 220c, because the capacity of heat transmission of interlayer dielectric layer 400 is more weak, when follow-up applying electric current is to electric fuse structure, the heat that electric fuse structure produces cannot spread in time, therefore, the change in resistance of electric fuse structure can be comparatively large, contributes to fusing.
It should be noted that, when being formed with metal silicide layer 270, described metal silicide layer 270 is also a part for electric fuse structure.Therefore, the material of described metal silicide layer 270 is autoregistration polysilicon thing (salicide) or non-silicide (non-silicide), such as WSi
2, CoSi
2or NiPtSi etc.
Incorporated by reference to reference to figure 15A, 15B, 15C, wherein, Figure 15 A is the plan structure schematic diagram of the forming process of the semiconductor device of first embodiment of the invention; Figure 15 B is the cross-sectional view of Figure 15 A along X-X ' direction; Figure 15 C is the cross-sectional view of Figure 16 along Y-Y ' direction.
Form the multiple conductive plungers 280 being positioned at described interlayer dielectric layer 400, described multiple conductive plunger 280 is electrically connected with the first source region, drain region 222, second, source region 213, first 223 and the second drain region 222 respectively.
Described conductive plunger 280, for being electrically connected the source electrode of all-around-gate transistor and drain electrode, the negative electrode of electric fuse structure and anode, is namely electrically connected the first source region, drain region 212, second, source region 213, first 223 and the second drain region 222.
In the present embodiment, the forming step of described conductive plunger 280 comprises: etch described interlayer dielectric layer 400 and form multiple opening (sign), and described multiple opening exposes the first source region, drain region 222, second, source region 213, first 223 and surface, the second drain region 222 respectively; In described multiple opening, filled conductive material forms conductive plunger 280.The material of described conductive plunger 280 is tungsten, copper, aluminium etc.
In an embodiment of the present invention, because the first source region, drain region 212, second, source region 213, first 223 and the second drain region 222 surface coverage have metal silicide layer 270, therefore, described opening exposes metal silicide layer 270 surface.Described multiple conductive plunger 280 is formed in same processing step, thus effectively saves processing step.
After above-mentioned steps completes, completing of the semiconductor device of the present embodiment.Because electric fuse adopts nano wire to make, and the channel region of all-around-gate transistor also adopts nano wire to make.Therefore, electric fuse can be formed while the channel region forming all-around-gate transistor.Further, the negative electrode of electric fuse structure and anode are also formed while the source electrode forming all-around-gate transistor and drain electrode, can not increase extra processing step, and formation process is simple, and adds the diversity realizing semiconductor device, and range of application is wider.
Accordingly, please continue to combine with reference to figure 15A, 15B, 15C, inventor additionally provides a kind of semiconductor device, comprising:
Semiconductor substrate 200a, described Semiconductor substrate 200a can be the silicon of monocrystalline, polycrystalline or non crystalline structure, germanium, GaAs or SiGe (SiGe) compound, also can be the substrates that silicon-on-insulator (SOI) is made.In the present embodiment, described Semiconductor substrate 200a is chosen as monocrystalline substrate;
The all-around-gate transistor (sign) being positioned at described semiconductor substrate surface and the electric fuse structure (sign) of isolating with it;
Wherein, described all-around-gate transistor comprises on the grid structure 250 covering described first nano wire 210c, described first nano wire 210c, be positioned at source electrode (i.e. the first source region 213) and the drain electrode (i.e. the first drain region 222) of described grid structure 250 both sides, and on described first nano wire 210, the channel region that the region between described source electrode and drain electrode is formed;
Described electric fuse structure comprise be positioned at described second nano wire two ends negative electrode (i.e. the second source region 223) and anode (i.e. the second drain region 222) and the second nano wire 220c on, the fuse area that between described negative electrode and anode, region is formed.
In the present embodiment, the anode of the source electrode of described all-around-gate transistor and drain electrode and electric fuse structure is identical with the ionic type adulterated in negative electrode; Have doping in the channel region of described all-around-gate transistor and the fuse area of electric fuse structure, the anode of the source electrode of described channel region and the Doped ions type in fuse area and all-around-gate transistor and drain electrode and electric fuse structure is identical with the ionic type adulterated in negative electrode.
In the present embodiment, also comprise: the side wall 260 being positioned at described grid structure 250 sidewall; Cover the interlayer dielectric layer 400 of described all-around-gate transistor, electric fuse structure; Be positioned at described interlayer dielectric layer 400, and the conductive plunger 280 be electrically connected with the source electrode (the first source region 211) of all-around-gate transistor and the negative electrode (the second source region 221) of drain (the first drain region 212) and electric fuse structure and anode (the second drain region 222); Be positioned at the metal silicide layer 270 of the source electrode of described all-around-gate transistor and the negative electrode of drain electrode and electric fuse structure and anode surface, be electrically connected with described conductive plunger 280.The material of described metal silicide layer 270 is WSi
2, CoSi
2or NiPtSi.
More descriptions about described semiconductor device, please refer to the associated description in the formation method of aforementioned semiconductor device.
In first embodiment of the invention, not only comprise all-around-gate transistor in described semiconductor device, also comprise electric fuse structure, and the fuse area of described electric fuse structure is formed by nano wire, the area of section vertical with the sense of current due to it is little, and resistance is high, easily fuses.And when having doping in described fuse area, the migration by charge carrier makes the change of its internal resistance rate, thus reaches the object of fusing.Achieve the variation of electric fuse structure and forming method thereof, and the integrated level of semiconductor device is high, range of application is wider.
It should be noted that behind described first source region, drain region 212, second, source region 213, first 223 of formation and the second drain region 222, directly form described interlayer dielectric layer 400; Afterwards, offer for follow-up formation metallic conduction connector 280 in described interlayer dielectric layer 400, and after exposing the through hole (being display in figure) in described first source region, drain region 212, second, source region 213, first 223 and the second drain region 222, in through hole, form the metal silicide layer 270 be covered on described first source region, drain region 212, second, source region 213, first 223 and the second drain region 222, and finally form semiconductor device as shown in figure 15 c.These simply change all in the bright protection range of we.
Or be, in other embodiments, with reference to shown in Figure 16, in described second source region 223 and the second drain region 222 of formation, described 5th mask layer 330 shown in Figure 12 A ~ 12C can be removed, afterwards in described first drain region 212, source region 213, first and described second nano wire 220c surface coverage metal silicide layer 270.
Afterwards, with reference to shown in Figure 17, to dielectric layer 400 between described Semiconductor substrate 200a upper caldding layer, the described metallic conduction connector 280 of formation described interlayer dielectric layer 400 in.Thus the semiconductor device formed as shown in figure 16.
Second embodiment
Different from the first embodiment, in the second embodiment of the present invention, provide a kind of formation method of electric fuse structure, described electric fuse structure might not parasitize in the forming step of all-around-gate transistor, and nano wire on a semiconductor substrate that can be independent forms electric fuse structure.
Please refer to Figure 18, Semiconductor substrate 300 is provided.Described Semiconductor substrate 300 can be the silicon of monocrystalline, polycrystalline or non crystalline structure, germanium, GaAs or SiGe (SiGe) compound, also can be the substrate that silicon-on-insulator (SOI) is made.
In the present embodiment, described Semiconductor substrate 300 is chosen as monocrystalline substrate.
In described Semiconductor substrate 300, form nano wire 290, described nano wire 290 matches with follow-up formation nano thread structure.
The method that this enforcement forms described nano wire 290 is chosen as: Doped ions in described Semiconductor substrate 300, forms described nano wire 290.Now, described nano wire 290 is in amorphous silicon structures.
In the present embodiment, described ion at least comprises B.Alternatively, except B, described ion also can comprise C, Si, N, Ge
Afterwards, the described Semiconductor substrate 300 of etched portions thickness, makes described nano wire 290 be raised in above described Semiconductor substrate 300.The two ends of the described nano wire 290 of its protrusions are supported by described Semiconductor substrate 300, and have interval between mid portion and described Semiconductor substrate 300, thus the interior nano wire 290 forming projection.Described nano wire 290 is for the formation of electric fuse structure.
In this enforcement, the detailed process that described nano wire 290 is formed comprises:
After described Semiconductor substrate 300 is formed the nano wire 290 of amorphous silicon structures, the described Semiconductor substrate of etched portions thickness, Semiconductor substrate 300 surface after making described nano wire be raised in etching.Wherein, the two ends of described nano wire 290 are supported by described Semiconductor substrate 300, and have interval between mid portion and described Semiconductor substrate 300.Concrete etching technics please refer to described in enforcement 1, does not repeat them here.
Afterwards, described nano wire 290 crystallization that annealing process makes amorphous silicon structures is carried out.Nano wire 290 after crystallization is for the formation of the electric fuse structure comprising negative electrode, anode and fuse area.
In the doping of the two ends of described nano wire 290, form negative electrode 241 and the anode 242 of electric fuse structure, and on described nano wire 290, the follow-up fuse area for the formation of electric fuse structure in the region between described negative electrode 241 and anode 242 (sign).
In this enforcement, also comprise: before the negative electrode 241 forming electric fuse structure and anode 242, to the mid portion Doped ions of described nano wire 290, for the fuse area of follow-up formation doped with ion.Follow-up when applying the signal of telecommunication to the electric fuse structure formed, along with the migration of charge carrier, to cause in fuse area resistivity everywhere to change, thus fuse.
It should be noted that, after the nano wire completing described middle doping is formed, can repair the surface of described nano wire and two end faces.In the present embodiment, thermal oxidation technology can be adopted to repair described nano wire, form the repair layer of the described nano wire of parcel.This renovation technique, can effectively to alleviate in the journey of the zone line Doped ions of the above-mentioned nano wire 290 to described formation produce powerful impulsive force and damage that final nano wire 290 surface formed is caused.
It should be noted that, in the present embodiment, also comprise: form the interlayer dielectric layer 600 covering described electric fuse structure; Form the multiple conductive plungers 281 being positioned at interlayer dielectric layer 600, described multiple conductive plunger 281 is electrically connected with described negative electrode and anode respectively, to realize the signal of telecommunication to be applied on negative electrode and anode.
It should be noted that, in the present embodiment, for reducing conductive plunger 280 and the contact resistance of negative electrode 241, anode 242 interface, can also comprise: form the metal silicide layer 273 being positioned at described negative electrode 241, anode 242 surface.
After above-mentioned steps completes, completing of the electric fuse structure of the present embodiment, the processing step of the electric fuse structure of formation is simple, achieves the variation of electric fuse structure formation method.
Meanwhile, please continue to refer to Figure 18, the electric fuse structure that said method is formed, comprising:
Semiconductor substrate 300;
Be raised in the nano wire 290 on described Semiconductor substrate 300 surface, described nano wire 290 is supported by Semiconductor substrate 300 for two ends, has interval between the mid portion of described nano wire 290 and described Semiconductor substrate 300.
The negative electrode 241 of described electric fuse structure and anode 242 lay respectively at the two ends of described nano wire 290, and its inside is doped with ion; And nano wire 290 region between described negative electrode 241 and anode 242 forms the fuse area stating electric fuse structure.
In the present embodiment, in described fuse area, there is doping.
Above-mentioned electric fuse structure also comprises: the metal silicide layer 273 covering described negative electrode 241, anode 242 surface; Cover the interlayer dielectric layer 600 of described negative electrode 241, anode 242 and fuse area; Run through multiple conductive plungers 281 of described interlayer dielectric layer 600, described conductive plunger 281 contacts with metal silicide layer 273, and is electrically connected with described negative electrode 241 and anode 242 respectively.
It should be noted that, after the described negative electrode 241 of formation, anode 242, can be formed directly in described interlayer dielectric layer 600, offer on described interlayer dielectric layer 600 afterwards for follow-up formation metallic conduction connector 281, and after exposing the through hole (being display in figure) of described negative electrode 241, anode 242, the metal silicide layer 273 be covered on described negative electrode 241, anode 242 is formed, the final electric fuse structure formed as shown in figure 18 in through hole.These simply change all in the bright protection range of we.
Or be, with reference to shown in Figure 19, direct in described nano wire 290 surface coverage metal silicide layer 274 after the described negative electrode 241 of formation, anode 242.Afterwards again to dielectric layer 600 between described Semiconductor substrate 300 upper caldding layer, thus form described metallic conduction connector 281 in described interlayer dielectric layer 600, form electric fuse structure as shown in figure 19.
In the present embodiment, because the fuse area of described electric fuse structure is formed by nano wire, the area of section vertical with the sense of current due to it is little, and resistance is high, easily fuses.And when having doping in described fuse area, the migration by charge carrier makes the change of its internal resistance rate, thus reaches the object of fusing.Achieve the variation of electric fuse structure and forming method thereof.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (30)
1. a formation method for electric fuse structure, is characterized in that, comprising:
Semiconductor substrate is provided;
Nano wire is formed in described Semiconductor substrate;
The described Semiconductor substrate of etched portions thickness, make described nano wire be raised in Semiconductor substrate, and the two ends of described nano wire is supported by Semiconductor substrate, has interval between mid portion and described Semiconductor substrate;
Carry out ion doping to the two ends of described nano wire, form negative electrode and the anode of electric fuse structure, the region on described nano wire between negative electrode and anode is fuse area.
2. the formation method of electric fuse structure as claimed in claim 1, is characterized in that, by Doped ions in described Semiconductor substrate, form described nano wire.
3. the formation method of electric fuse structure as claimed in claim 2, it is characterized in that, the ion of doping at least comprises B.
4. the formation method of electric fuse structure as claimed in claim 3, it is characterized in that, described ion also comprises C, Si, N, Ge.
5. the formation method of electric fuse structure as claimed in claim 2, is characterized in that, the described Semiconductor substrate of etched portions thickness, makes after described nano wire is raised in Semiconductor substrate, also to comprise step:
Carry out recrystallization annealing temperature.
6. the formation method of electric fuse structure as claimed in claim 3, it is characterized in that, the method for the described Semiconductor substrate of etched portions thickness is wet etching.
7. the formation method of electric fuse structure as claimed in claim 6, it is characterized in that, the etching agent that described wet etching adopts comprises THAM or THEM.
8. the formation method of electric fuse structure as claimed in claim 1, is characterized in that, also comprise: before the negative electrode forming electric fuse structure and anode, the zone line to described nano wire carries out ion doping, forms the fuse area doped with ion.
9. the formation method of electric fuse structure as claimed in claim 8, is characterized in that, after formation is doped with the fuse area of ion, repairs described nano wire.
10. the formation method of electric fuse structure as claimed in claim 9, it is characterized in that, the method for described reparation is thermal oxidation technology or annealing process.
The formation method of 11. electric fuse structures as claimed in claim 1, it is characterized in that, also comprise: form multiple conductive plunger, described multiple conductive plunger is electrically connected with described negative electrode and anode respectively.
12. 1 kinds of electric fuse structures, is characterized in that, comprising:
Semiconductor substrate;
Nano wire, is raised in described semiconductor substrate surface and two ends are supported by described Semiconductor substrate, has interval between the mid portion of nano wire and described Semiconductor substrate;
Negative electrode and anode, lay respectively at the two ends of described nano wire;
Fuse area, the negative electrode on described nano wire and between anode.
13. electric fuse structures as claimed in claim 12, is characterized in that, doped with ion in described fuse area.
14. electric fuse structures as claimed in claim 12, is characterized in that, also comprise: the interlayer dielectric layer covering described negative electrode, anode and fuse area; Run through multiple conductive plungers of described interlayer dielectric layer, described multiple conductive plunger is electrically connected with described negative electrode and anode respectively.
The formation method of 15. 1 kinds of semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided;
The first nano wire and the second nano wire is formed in described Semiconductor substrate;
The described Semiconductor substrate of etched portions thickness, described first nano wire and the second nano wire is made to be raised in Semiconductor substrate, and the two ends of described first nano wire and the second nano wire support by Semiconductor substrate, all have interval between mid portion and described Semiconductor substrate;
Form the grid structure of coated described first nanowire surface;
Carry out ion doping at the two ends of the first nano wire, form source electrode and the drain electrode of all-around-gate transistor;
Ion doping is carried out at two ends to described second nano wire, and form negative electrode and the anode of electric fuse structure, the region on described second nano wire between negative electrode and anode is fuse area.
The formation method of 16. semiconductor device as claimed in claim 15, is characterized in that,
Doped ions in described Semiconductor substrate, forms described first nano wire and the second nano wire.
The formation method of 17. semiconductor device as claimed in claim 16, it is characterized in that, described ion at least comprises B.
The formation method of 18. semiconductor device as claimed in claim 17, it is characterized in that, described ion also comprises C, Si, N, Ge.
The formation method of 19. semiconductor device as claimed in claim 15, is characterized in that, the described Semiconductor substrate of etched portions thickness, makes after described first nano wire and the second nano wire be raised in Semiconductor substrate, also to comprise step:
Carry out recrystallization annealing temperature.
The formation method of 20. semiconductor device as claimed in claim 15, is characterized in that, the method for the described Semiconductor substrate of etched portions thickness is wet etching.
The formation method of 21. semiconductor device as claimed in claim 20, it is characterized in that, the etching agent that described wet etching adopts comprises THAM or THEM.
The formation method of 22. semiconductor device as claimed in claim 15, is characterized in that, the described source electrode of formation all-around-gate transistor and the negative electrode of the step of drain electrode and described formation electric fuse structure and the step of anode are carried out simultaneously.
The formation method of 23. semiconductor device as claimed in claim 15, it is characterized in that, also comprise: before forming grid structure, mid portion to described first nano wire and the second nano wire carries out ion doping, forms mid portion doped with the first nano wire of ion and mid portion the second nano wire doped with ion.
The formation method of 24. semiconductor device as claimed in claim 23, it is characterized in that, to described first nano wire and the ionic type that the mid portion of the second nano wire adulterates and the ionic type adulterated at the two ends of the first nano wire and the ionic type that adulterates at the two ends of described second nano wire identical.
The formation method of 25. semiconductor device as claimed in claim 23, it is characterized in that, also comprise: form mid portion doped with the first nano wire of ion and mid portion doped with after the second nano wire of ion, described first nano wire and the second nano wire are repaired.
The formation method of 26. semiconductor device as claimed in claim 25, is characterized in that, the method for described reparation is annealing process or thermal oxidation technology.
The formation method of 27. semiconductor device as claimed in claim 15, is characterized in that, also comprise: form the interlayer dielectric layer covering described all-around-gate transistor and electric fuse structure; In described interlayer dielectric layer, form multiple conductive plunger, described multiple conductive plunger is electrically connected with the source electrode of described all-around-gate transistor and the negative electrode of drain electrode and electric fuse structure and anode respectively.
28. 1 kinds of semiconductor device, is characterized in that, comprising:
Semiconductor substrate;
Full encirclement transistor, is positioned at described semiconductor substrate surface;
Described full encirclement transistor comprises the source electrode and the drain electrode that the first nano wire, the grid structure of coated described first nano wire, described first nano wire are positioned at described grid structure both sides, and the channel region that on described first nano wire, region is formed between described source electrode and drain electrode;
Electric fuse structure, is positioned at described semiconductor substrate surface, isolated with described full encirclement transistor;
Described electric fuse structure comprises the second nano wire, is positioned at negative electrode and the anode at described second nano wire two ends and the fuse area on described nano wire between described negative electrode and anode.
29. semiconductor device as claimed in claim 28, is characterized in that, the anode of the source electrode of described all-around-gate transistor and drain electrode and electric fuse structure is identical with the ionic type adulterated in negative electrode.
30. semiconductor device as claimed in claim 28, it is characterized in that, doped with ion in the channel region of described all-around-gate transistor and the fuse area of electric fuse structure, the anode of described channel region and the ionic type of doping in fuse area and the source electrode of all-around-gate transistor and drain electrode and electric fuse structure is identical with the ionic type adulterated in negative electrode.
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