CN104241189B - The manufacture method of groove - Google Patents
The manufacture method of groove Download PDFInfo
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- CN104241189B CN104241189B CN201310234433.9A CN201310234433A CN104241189B CN 104241189 B CN104241189 B CN 104241189B CN 201310234433 A CN201310234433 A CN 201310234433A CN 104241189 B CN104241189 B CN 104241189B
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- etching step
- groove
- manufacture method
- curtain layer
- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The present invention provides a kind of manufacture method of groove.This method comprises the following steps：One substrate is provided；An at least insulating barrier is formed on the substrate；A curtain layer of hard hood is formed on the insulating barrier；The curtain layer of hard hood is patterned, to obtain the patterning curtain layer of hard hood with an opening；One first etching step is carried out, along insulating barrier described in the opening etching, to form a groove；A photoresistance is filled to pattern on curtain layer of hard hood with described in the groove；One second etching step is carried out, with the patterning curtain layer of hard hood of etching part and the patterning curtain layer of hard hood is exposed；One the 3rd etching step is carried out, to remove the patterning curtain layer of hard hood；And one the 4th etching step is carried out, to remove the photoresistance.Sulfuric acid can be provided easily in the macromolecule produced by etching step using the manufacture method of the groove of the present invention to remove, and will not injure insulating barrier.
Description
Technical field
The present invention is about a kind of manufacture method of semiconductor subassembly, and in particular to a kind of manufacture method of groove,
Belong to technical field of semiconductors.
Background technology
Semiconductor integrated circuit industry quickly development.With IC materials and the development in design so that each generation of IC
In generation, possesses circuit smaller than the previous generation and complicated.However, these development also improve the complexity of IC techniques, in order to realize
These advanced IC, are also required to the development of equity in IC technique.During IC develops, when IC physical dimensions (such as technique
The getable minimal modules (or line) of institute) while be gradually reduced, the density of functional unit is (such as in per unit chip area
Inline thermomechanical components) gradually increase therewith.
In existing mosaic texture technique, curtain layer of hard hood is formed on insulating barrier, afterwards, curtain layer of hard hood definition is recycled
The shape of groove.Then, curtain layer of hard hood and insulating barrier are removed using dry etching steps.Afterwards, conductive material is refilled (such as golden
Belong to material) in groove, to form mosaic texture.
Figure 1A microscope figure is referred to, in dry etching steps, many undesired macromolecules is had and residues in insulation
On layer, so, it need to remove macromolecule using cleaning in subsequent technique.
Figure 1B microscope figure is referred to, when carrying out cleaning using hydrofluoric acid (HF), insulating barrier can be injured, after causing
The critical size (Critical dimension, CD) of continuous metal wire is inconsistent, or even can reduce the resistance of metal wire, Jin Erying
Ring the reliability of semiconductor subassembly.
Accordingly, it is desirable to provide a kind of manufacture method of groove, the problem of this manufacture method can improve existing met with.
The content of the invention
In order to solve the above technical problems, it is an object of the invention to provide a kind of manufacture method of groove, using this method
The problem of can improving existing met with.
To reach above-mentioned purpose, the present invention provides a kind of manufacture method of groove, comprised the following steps：One substrate is provided；
An at least insulating barrier is formed on the substrate；A curtain layer of hard hood is formed on the insulating barrier；Pattern the hardcoat
Curtain layer, to obtain the patterning curtain layer of hard hood with an opening；One first etching step is carried out, described in the opening etching
Insulating barrier, to form a groove；A photoresistance is filled to pattern on curtain layer of hard hood with described in the groove；Carry out one second
Etching step, with the patterning curtain layer of hard hood of etching part and exposes the patterning curtain layer of hard hood；Carry out one the 3rd
Etching step, to remove the patterning curtain layer of hard hood；And one the 4th etching step is carried out, to remove the photoresistance.
The insulating barrier includes silicon oxide layer, silicon nitride layer or combinations of the above.
In the manufacture method of above-mentioned groove, it is preferable that the thickness of the insulating barrier is about 50-300nm.
In the manufacture method of above-mentioned groove, it is preferable that the curtain layer of hard hood includes polysilicon, silicon nitride or above-mentioned group
Close.
In the manufacture method of above-mentioned groove, it is preferable that the thickness of the curtain layer of hard hood is about 50-200nm.
In the manufacture method of above-mentioned groove, it is preferable that the depth-to-width ratio of the groove is about 7/1-10/1.
In the manufacture method of above-mentioned groove, it is preferable that the cleaning is to use sulfuric acid.
In the manufacture method of above-mentioned groove, it is preferable that first etching step includes dry etching method.
In the manufacture method of above-mentioned groove, it is preferable that second etching step, the 3rd etching step with it is described
4th etching step is carried out in same reaction cavity.
In the manufacture method of above-mentioned groove, it is preferable that second etching step, the 3rd etching step with it is described
4th etching step is dry etch steps.
Brief description of the drawings
Figure 1A is one to illustrate macromolecule is residued on insulating barrier in the prior art microscope figure.
Figure 1B is one to illustrate to use in the prior art during hydrofluoric acid progress cleaning to the wound caused by insulating barrier
Harmful microscope figure.
Fig. 2A -2G are a series of profiles to illustrate the flow of the manufacture method of the groove of one embodiment of the invention.
Fig. 3 A-3E are a series of sections to illustrate the flow of the manufacture method of the groove of second embodiment of the invention
Figure.
Fig. 4 be a manufacture method to illustrate groove of the present invention after persulfuric acid step, obtain with uniform-dimension
Groove microscope figure.
Primary clustering symbol description：
11 first etching steps
12 second etching steps
13 the 3rd etching steps
14 the 4th etching steps
110 substrates
120 insulating barriers
120a patterned insulation layers
122 first insulating barriers
124 second insulating barriers
124a patterns the second insulating barrier
126 the 3rd insulating barriers
126a patterns the 3rd insulating barrier
130 curtain layer of hard hood
130a patterns curtain layer of hard hood
132 first curtain layer of hard hood
132a patterns the first curtain layer of hard hood
134 second curtain layer of hard hood
135 openings
137 grooves
140 photoresistances
The photoresistance of 140a residuals
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, it is cited below particularly go out preferable implementation
Example, and coordinate institute's accompanying drawings, it is described in detail below：
Below especially exemplified by going out embodiments of the invention, and institute's accompanying drawings are coordinated to elaborate.The component of following examples and
Design is, for the invention disclosed by simplification, to be not limited to the present invention.The present invention may use weight in each embodiment
Multiple reference symbol and/or use word.These replicators are, for simplification and clearly purpose, to be not limited to each with word
Relation between individual embodiment and/or the structure.In addition, referring to forming first structure feature positioned at the second structure in specification
On feature, it is the embodiment directly contacted that it, which includes first structure feature and the second architectural feature, and first is also included in addition
There is the embodiment of other structures feature between architectural feature and the second architectural feature in addition, that is, first structure feature and second
Architectural feature and non-direct contact.
Fig. 2A -2G are referred to, the present invention provides a kind of manufacture method of groove.Referring to Fig. 2A, there is provided substrate 110, shape
Into an at least insulating barrier 120 on substrate 110.
Substrate 110 may include：Elemental semiconductor comprising silicon or germanium, exists with crystalline state, polycrystalline state or amorphous structure；
Compound semiconductor includes carborundum (silicon carbide), GaAs (gallium arsenic), gallium phosphide
(gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) and indium antimonide
(indium antimonide)；Alloy semiconductor includes sige alloy (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide
(AlInAs), aluminum gallium arsenide (AlGaAs), Gallium indium arsenide (GaInAs), InGaP (GaInP) and phosphorus arsenic gallium indium
(GaInAsP)；Or other suitable materials；Or combinations of the above.
It may include a variety of components, such as transistor, resistance or other existing semiconductor subassemblies in substrate 110.
Furthermore, substrate 110 also may include other conductive layers (such as copper, aluminium or its alloy) and insulating barrier (such as silica, nitridation
Silicon).Here for explanation is simplified, it is only represented with a smooth substrate.
Insulating barrier 120 includes silicon oxide layer, silicon nitride layer or combinations of the above.Although only showing single layer insulating in figure
120, however, the number of plies of insulating barrier 120 is not limited thereto, people in the art scholar can adjust absolutely according to the demand of practical application
The number of plies of edge layer 120.
In an embodiment, insulating barrier 120 is made up of three-decker, and first layer is formed on substrate 110 and it is
100nm silicon oxide layer, the second layer is 50nm silicon nitride, and third layer is 200nm silicon oxide layer.
Insulating barrier 120 can be formed by any suitable technique, for example chemical vapour deposition technique, high density plasma enhanced chemical gas
Phase sedimentation, spin coating process, sputter and/or other suitable methods.The thickness of insulating barrier 120 is about 50-300nm, compared with
Good is about 50-200nm.
Referring again to Fig. 2A, curtain layer of hard hood (hard mask layer) 130 is formed on insulating barrier 120.Hard cover screen
Layer 130 includes single or multiple lift 130, and its material includes polysilicon, silicon nitride or combinations of the above.Although only being shown in figure single
Layer curtain layer of hard hood 130, however, the number of plies of curtain layer of hard hood 130 is not limited thereto, people in the art scholar can be according to practical application
Demand and the number of plies for adjusting curtain layer of hard hood 130.
Curtain layer of hard hood 130 can be formed by any suitable technique, such as chemical vapour deposition technique, high density plasma enhanced chemical
Vapour deposition process, spin coating process, sputter and/or other suitable methods.The thickness of curtain layer of hard hood 130 is about 50-
200nm, preferably about 50-100nm.
In an embodiment, curtain layer of hard hood 130 is double-layer structure, and the first Rotating fields are 100nm polysilicon, second layer knot
Structure is 50nm silicon nitride.
Fig. 2 B are referred to, curtain layer of hard hood 130 is patterned, to obtain the patterning curtain layer of hard hood 130a with an opening 135.
Patternized technique such as lithography process.
Fig. 2 C are referred to, the first etching step 11 are carried out, along the etching isolation layer 120 of opening 135, to form groove 137.
There is groove 137 depth-to-width ratio (aspect ratio, h/w) to be about 7/1-10/1.First etching step 11 includes dry etching method.
After the first etching step 11, patterned insulation layer 120a is obtained.
Fig. 2 D are referred to, filling photoresistance 140 is in groove 137 with patterning on curtain layer of hard hood 130a.
Refer to Fig. 2 E, carry out the second etching step 12, with the patterning curtain layer of hard hood 130a of etching part and expose
Pattern curtain layer of hard hood 130a, therefore, the photoresistance 140a remained.
Fig. 2 F are referred to, the 3rd etching step 13 is carried out, to remove patterning curtain layer of hard hood 130a.
Fig. 2 G are referred to, the 4th etching step 14 is carried out, to remove the photoresistance 140a of residual, and exposes groove 137 to the open air again.
It is noted that when manufacture method of the present invention is applied to make mosaic texture, after the 4th etching step 14, position can be exposed to the open air
Conductive layer (not shown) in the lower section of groove 137, therefore, when subsequent technique filling metal material (such as tungsten) is in groove
In 137, available for the metal material being electrically connected with beneath trenches and conductive layer and groove.
After Fig. 2 G, the manufacture method of groove of the present invention also includes：With cleaning remove residue in the insulating barrier it
On a macromolecule, wherein cleaning is uses sulfuric acid.
Above-mentioned second etching step 12, the 3rd etching step 13 and the 4th etching step 14 are entered in same reaction cavity
OK, that is, in (in-situ) in situ three kinds of etching steps are carried out.In addition, the second etching step 12, the 3rd etching step 13 and
Four etching steps 14 are all dry-etching (dry etching) step.
In a preferred embodiment, the second etching step 12 and the 4th etching step 14 are including the use of oxygenous (O2)、CF4、
C4F6Reacting gas, and the 3rd etching step 13 is including the use of containing hydrogen bromide (HBr), Cl2、SF6Reacting gas.
It is noted that in the prior art, in dry etching steps, many undesired macromolecules can be produced and residued in absolutely
(Figure 1A is referred on edge layer), and the macromolecule remained is not easy to be removed with sulfuric acid, therefore, is removed using hydrofluoric acid (HF),
However, insulating barrier (referring to Figure 1B) can be injured using hydrofluoric acid, and then influence the reliability of semiconductor subassembly.
Different from prior art, present invention filling photoresistance 140 is in groove 137 with patterning on curtain layer of hard hood 130a
(referring to Fig. 2 D), afterwards, carries out the second etching step 12, the 3rd etching step 13 and the 4th etching step in same cavity
14, because the reacting gas in etching process can be reacted with photoresistance 140, produced macromolecule composition is different from existing difficulty
With the macromolecule of removal, therefore, macromolecule of the invention can easily pass through sulfuric acid removal, and will not injure insulating barrier 120.
Fig. 3 A-3E are referred to, it shows the manufacture method of the groove of second embodiment of the invention.
Fig. 3 A are referred to there is provided substrate 110, an at least insulating barrier 120 are formed on substrate 110, and form hardcoat
Curtain layer 130 is on insulating barrier 120.
In an embodiment, substrate 110 is silicon substrate.Insulating barrier 120 includes the first insulating barrier 122, the second insulating barrier 124
With the 3rd insulating barrier 126.Curtain layer of hard hood 130 includes the first curtain layer of hard hood 132 and the second curtain layer of hard hood 134.
It may include a variety of components, such as transistor, resistance or other existing semiconductor subassemblies in substrate 110.
Furthermore, substrate 110 also may include other conductive layers (such as copper, aluminium or its alloy) and insulating barrier (such as silica, nitridation
Silicon).Here for explanation is simplified, it is only represented with a smooth substrate.
Insulating barrier 120 can be formed with curtain layer of hard hood 130 each via any suitable technique, such as chemical vapor deposition
Method, high density plasma enhanced chemical vapor deposition method, spin coating process, sputter and/or other suitable methods.
In an embodiment, the first insulating barrier 122 is 100nm silicon oxide layer, and the second insulating barrier 124 is 50nm nitridation
Silicon, the 3rd insulating barrier 126 is 200nm silicon oxide layer, and the first curtain layer of hard hood 132 is 100nm polysilicon, the second curtain layer of hard hood
134 be 50nm silicon nitride.
Fig. 3 B are referred to, Patternized technique first is carried out to the second curtain layer of hard hood 134, to form the second curtain layer of hard hood of patterning
(not shown), afterwards, recycles the second curtain layer of hard hood of patterning as mask, to form the first curtain layer of hard hood of patterning
132a.Afterwards, the first etching step 11 is carried out to insulating barrier 120, to form groove 137.After the first etching step 11,
The second insulating barrier 124a of patterning is obtained with patterning the 3rd insulating barrier 126a.
Fig. 3 C are referred to, filling photoresistance 140 is in groove 137 with patterning on the first curtain layer of hard hood 132a.
Fig. 3 D are referred to, the second etching step 12 is carried out, curtain layer of hard hood 132a and exposure are patterned with the first of etching part
Expose the first patterning curtain layer of hard hood 132a, the photoresistance 140a remained.
Then, the 3rd etching step and the 4th etching step (not shown) are carried out, to remove the first patterning hardcoat
The curtain layer 132a and photoresistance 140a of residual.
Afterwards, Fig. 3 E are referred to, after the photoresistance 140a of residual is removed, and groove 137 are exposed to the open air again.Notably
It is that, when manufacture method of the present invention is applied to make mosaic texture, after the 4th etching step (not shown in Fig. 3 D), can expose
Dew is located at the conductive layer (not shown) of the lower section of groove 137, therefore, when subsequent technique filling metal material (such as tungsten) is in ditch
In groove 137, available for the metal material being electrically connected with beneath trenches and conductive layer and groove.
After Fig. 3 E, the manufacture method of groove of the present invention also includes：With cleaning remove residue in the insulating barrier it
On a macromolecule, wherein cleaning is uses sulfuric acid.
Above-mentioned second etching step 12, the 3rd etching step (not shown in Fig. 3 D) and the 4th etching step are (in Fig. 3 D not
Display) it is to be carried out in same reaction cavity, that is, carry out three kinds of etching steps in (in-situ) in situ.In addition, the second etching
Step 12, the 3rd etching step and the 4th etching step are all dry-etching (dry etching) step.
In a preferred embodiment, the second etching step 12 and the 4th etching step are including the use of oxygenous (O2)、CF4、
C4F6Reacting gas, and the 3rd etching step is including the use of containing hydrogen bromide (HBr), Cl2、SF6Reacting gas.
Fig. 4 microscope figure is referred to, it shows the manufacture method of the present invention after persulfuric acid step, obtain having
The groove of even size.
From above-described embodiment, by the manufacture method of groove provided by the present invention, by filling photoresistance 140 in ditch
With (referring to Fig. 2 D and Fig. 3 C) on patterning curtain layer of hard hood 130a in groove 137, afterwards, the second erosion is carried out in same cavity
Step 12, the 3rd etching step 13 and the 4th etching step 14 are carved, because the reacting gas in etching process can enter with photoresistance 140
Row reaction, produced macromolecule composition is different from the existing macromolecule for being difficult to remove, therefore, the high score produced by etching step
Son can provide sulfuric acid removal easily, and will not injure insulating barrier 120.
Although the present invention is disclosed above with several preferred embodiments, so it is not limited to the present invention, any affiliated
Have usually intellectual in technical field, without departing from the spirit and scope of the present invention, arbitrarily change and retouch when that can make,
Therefore protection scope of the present invention is when depending on being defined that right is defined.
Claims (9)
1. a kind of manufacture method of groove, comprises the following steps：
One substrate is provided；
An at least insulating barrier is formed on the substrate；
A curtain layer of hard hood is formed on the insulating barrier；
The curtain layer of hard hood is patterned, to obtain the patterning curtain layer of hard hood with an opening；
One first etching step is carried out, along insulating barrier described in the opening etching, to form a groove；
A photoresistance is filled to pattern on curtain layer of hard hood with described in the groove；
One second etching step is carried out, with the patterning curtain layer of hard hood of etching part and the patterning hard cover screen is exposed
Layer；
One the 3rd etching step is carried out, to remove the patterning curtain layer of hard hood；And
One the 4th etching step is carried out, to remove the photoresistance；
Wherein, second etching step, the 3rd etching step and the 4th etching step are in same reaction cavity
In be carried out continuously, and the substrate in second etching step between the 3rd etching step, and the described 3rd
Etching step does not all move out the reaction cavity between the 4th etching step.
2. the manufacture method of groove as claimed in claim 1, wherein, the insulating barrier include silicon oxide layer, silicon nitride layer or
Combinations of the above.
3. the manufacture method of groove as claimed in claim 1, wherein, the thickness of the insulating barrier is 50-300nm.
4. the manufacture method of groove as claimed in claim 1, wherein, the curtain layer of hard hood include polysilicon, silicon nitride or on
The combination stated.
5. the manufacture method of groove as claimed in claim 1, wherein, the thickness of the curtain layer of hard hood is 50-200nm.
6. the manufacture method of groove as claimed in claim 1, wherein, the depth-to-width ratio of the groove is 7/1-10/1.
7. the manufacture method of groove as claimed in claim 1, wherein after the 4th etching step is carried out, still including：
A cleaning is carried out, to remove the macromolecule residued on the insulating barrier, wherein, the cleaning is to use sulphur
Acid.
8. the manufacture method of groove as claimed in claim 1, wherein, first etching step includes dry etching method.
9. the manufacture method of groove as claimed in claim 1, wherein, second etching step, the 3rd etching step
It is dry etch steps with the 4th etching step.
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| CN201310234433.9A CN104241189B (en) | 2013-06-13 | 2013-06-13 | The manufacture method of groove |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310234433.9A CN104241189B (en) | 2013-06-13 | 2013-06-13 | The manufacture method of groove |
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| CN104241189B true CN104241189B (en) | 2017-09-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270265A (en) * | 1992-09-01 | 1993-12-14 | Harris Corporation | Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure |
| TW507324B (en) * | 2000-08-30 | 2002-10-21 | Motorola Inc | Method for forming an electrically conductive interconnection between two semiconductor layers, and multilayer semiconductor device |
| CN1260777C (en) * | 2002-12-27 | 2006-06-21 | 海力士半导体有限公司 | Method for producing semiconductor device contact pad |
-
2013
- 2013-06-13 CN CN201310234433.9A patent/CN104241189B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270265A (en) * | 1992-09-01 | 1993-12-14 | Harris Corporation | Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure |
| TW507324B (en) * | 2000-08-30 | 2002-10-21 | Motorola Inc | Method for forming an electrically conductive interconnection between two semiconductor layers, and multilayer semiconductor device |
| CN1260777C (en) * | 2002-12-27 | 2006-06-21 | 海力士半导体有限公司 | Method for producing semiconductor device contact pad |
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| Publication number | Publication date |
|---|---|
| CN104241189A (en) | 2014-12-24 |
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