CN104241114B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN104241114B CN104241114B CN201310231922.9A CN201310231922A CN104241114B CN 104241114 B CN104241114 B CN 104241114B CN 201310231922 A CN201310231922 A CN 201310231922A CN 104241114 B CN104241114 B CN 104241114B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided, sequentially forms etching stopping layer, low k dielectric, cushion and hard mask layer on a semiconductor substrate；The first opening is formed in hard mask layer, to expose cushion；Wet cleaning processes are performed, using cleaning fluid of the basic solvent as the wet-cleaning；The second opening is formed in cushion and low k dielectric；Copper metal interconnection structure is formed in low k dielectric；Copper metal layer is formed in copper metal interconnection structure.According to the present invention, the hydrofluoric acid for substituting dilution using basic solvent, it is possible to prevente effectively from producing the defects of occurring when being subsequently formed the second opening, improves the process window of integration etching as the cleaning fluid for forming after the first opening the wet-cleaning implemented.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method for improving dual damascene process.
Background technology
In the back-end process of semiconductor devices（BEOL）In, generally use dual damascene process is formed in semiconductor devices
Copper metal interconnection layer, Figure 1A-Fig. 1 E show a kind of dual damascene process process.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, using chemical vapor deposition method in Semiconductor substrate 100
On sequentially form etching stopping layer 101, low k dielectric 102, cushion 103 and hard mask layer 104.
On a semiconductor substrate 100 formed with front-end devices, to put it more simply, being not shown in legend.The front-end devices
Refer to the device formed before BEOL, the concrete structure of front-end devices is not defined herein.The ultralow k of generally use is situated between
Electric material forms low k dielectric 102, and the ultra low k dielectric materials refer to dielectric constant（K values）Dielectric material less than 2.Buffering
103 OMCTS by stacking gradually from bottom to top of layer（Prestox is cyclized tetrasiloxane）Layer 103a and TEOS（Tetraethyl orthosilicate）Layer
103b is formed, and TEOS layers 103b effect is to avoid mechanical stress from being situated between ultralow k in the copper-connection metal of follow-up grinding filling
The porous structure of electric material causes to damage, the OMCTS layers 103a mistake functioned as between ultra low k dielectric materials and TEOS
Material layer is crossed to increase adhesive force therebetween.Hard mask layer 104 is by the metal hard mask layer that stacks gradually from bottom to top
104a and oxide hard-mask layer 104b is formed, and the structure of this double-deck hard mask layer can ensure Dual graphing or multiple
Patterned craft precision.
Then, as shown in Figure 1B, the first opening 105 is formed in hard mask layer 104, to expose the cushion 103 of lower section.
First opening 105 is used as the patterns of the grooves in copper metal interconnection structure, and it can include multiple with different characteristic size
Figure.
Then, as shown in Figure 1 C, the second opening 106 is formed in cushion 103 and low k dielectric 102, described second opens
Mouth 106 is used as the patterns of the through hole in copper metal interconnection structure, and it can also include multiple figures with different characteristic size.
Then, as shown in figure iD, it is mask with hard mask layer 104, performs integration etching（All-in-one Etch）Work
Skill etch buffer layers 103 and low k dielectric 102（I.e. synchronous etch buffer layers 103 and low k dielectric 102）, with low k dielectric
Copper metal interconnection structure 107 is formed in layer 102.
Produced after the first opening 105 is formed, it is necessary to perform a wet cleaning processes with removing etching hard mask layer 104
Raw residue and impurity, to ensure that the formation of follow-up second opening 106 has good process window.Due to DHF（Dilution
Hydrofluoric acid）With preferable cleaning efficiency, therefore, those skilled in the art's generally use DHF（The hydrofluoric acid of dilution）As institute
State the cleaning fluid of wet-cleaning.However, due to the constraint of device feature size, the thickness of the TEOS layers 103b in cushion 103
Value is smaller, and the loss for the TEOS that DHF is triggered is particularly problematic.The problem it is critical that TEOS loss may cause
Expose the part OMCTS layer 103a below TEOS layers 103b, in the forming process of the follow-up second opening 106, need at first
The ODL to be formed（Organic dielectric layer）Chemical reaction occurs with the part OMCTS layers 103a exposed and forms a kind of serious shadow
The material of etching efficiency is rung, causes the depth value of partial graphical in the second opening 106 too low, is implementing integrated etching
Afterwards, the bottom for the partial graphical in the copper metal interconnection structure 107 as shown in Fig. 1 E occur does not contact with etching stopping layer 101,
And then copper metal interconnection structure 107 is caused the problem of part interconnection open occur.Chemical reaction between above-mentioned OMCTS and ODL
Mechanism be：The carbon in free fluorine attack OMCTS in the DHF of residual, induction produce the silicon key being activated（Si-）；In order to increase
Strong ODL and thereon it is square into BARC（Bottom antireflective coating）Between tack, ODL top formed with play infiltration
The HMDS of layer effect（HMDS）, the amido in HMDS reconfigures to form Si-N-H-F bases with silicon key and free fluorine
Group, the group can cause the decline of etch-rate.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, etching stopping layer, low k dielectric, cushion and hard mask layer are sequentially formed on the semiconductor substrate；Described hard
The first opening is formed in mask layer, to expose the cushion；Wet cleaning processes are performed, using basic solvent as described wet
The cleaning fluid of method cleaning；The second opening is formed in the cushion and the low k dielectric；The shape in the low k dielectric
Into copper metal interconnection structure.
Further, the pH value of the basic solvent is 9.0-11.0.
Further, first opening is used as the pattern of the groove in the copper metal interconnection structure, second opening
Pattern as the through hole in the copper metal interconnection structure.
Further, using the hard mask layer as mask, with cushion described in step etching and the low k dielectric, with institute
State and the copper metal interconnection structure is formed in low k dielectric.
Further, after the etching terminates, in addition to the etching exposed by the copper metal interconnection structure is removed
The step of stop-layer and implementation etching post processing.
Further, after the etching post processing, it is additionally included in the copper metal interconnection structure and forms copper metal layer
The step of.
Further, formed before the copper metal layer, in addition on the bottom and side wall of the copper metal interconnection structure
The step of sequentially forming copper metal diffusion impervious layer and copper metal Seed Layer.
Further, the cushion is cyclized tetrasiloxane layer and teos layer structure by the prestox being laminated from bottom to top
Into.
Further, the hard mask layer is made up of the metal hard mask layer and oxide hard-mask layer being laminated from bottom to top.
Further, the constituent material of the metal hard mask layer is TiN, BN, AlN or its combination.
Further, the constituent material of the oxide hard-mask layer includes SiO2Or SiON, and relative to the metallic hard
The constituent material of mask layer has preferable etching selectivity.
According to the present invention, it is clear as the wet method implemented is formed after the first opening that the hydrofluoric acid of dilution is substituted using basic solvent
The cleaning fluid washed, it is possible to prevente effectively from the defects of occurring when being subsequently formed the second opening is produced, the technique for improving integration etching
Window.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 D are the device that is obtained respectively the step of implementation successively according to existing exemplary dual damascene process
The schematic cross sectional view of part；
Fig. 1 E are the schematic of the defects of exemplary dual damascene process implemented shown by Figure 1A-Fig. 1 D occurs afterwards
Profile；
Fig. 2A-Fig. 2 F are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 3 is the flow chart that dual damascene process is improved according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Improvement dual damascene process method.Obviously, execution of the invention is not limited to the technical staff institute of semiconductor applications
The specific details being familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention is also
There can be other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
Below, reference picture 2A- Fig. 2 F and Fig. 3 improve double damascenes to describe method according to an exemplary embodiment of the present invention
Remove from office the detailed step of technique.
Reference picture 2A- Fig. 2 F, it illustrated therein is method according to an exemplary embodiment of the present invention and implement the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, using chemical vapor deposition method in Semiconductor substrate 200
On sequentially form etching stopping layer 201, low k dielectric 202, cushion 203 and hard mask layer 204.
On semiconductor substrate 200 formed with front-end devices, to put it more simply, being not shown in legend.The front-end devices
Refer to the device formed before BEOL, the concrete structure of front-end devices is not defined herein.
Material preferred SiCN, SiC, SiN or BN of etching stopping layer 201, its as subsequent etch low k dielectric 202 with
While forming the etching stopping layer of upper copper metal interconnection structure, the copper in lower floor's copper metal interconnection line can be prevented to be diffused into
The dielectric substance layer on upper strata（Such as low k dielectric 202）In.
The constituent material of low k dielectric 202 can be selected from the common various low k-value dielectric materials in this area, including but not
It is 2.2 to be limited to silicate compound (Hydrogen Silsesquioxane, referred to as HSQ), k values that k values are 2.5-2.9
Methane-siliconic acid salt compound (Methyl Silsesquioxane, abbreviation MSQ), the HOSP that k values are 2.8TM（Honeywell companies
The advanced low-k materials of the mixture based on organic matter and Si oxide of manufacture）And the SiLK that k values are 2.65TM（Dow
A kind of advanced low-k materials of Chemical companies manufacture）Etc..Generally use ultra low k dielectric materials form low k dielectric
202, the ultra low k dielectric materials refer to dielectric constant（K values）Dielectric material less than 2.
Cushion 203 includes OMCTS layer 203a and TEOS layer 203b, the TEOS layers 203b stacked gradually from bottom to top work
With being to avoid mechanical stress from causing to damage to the porous structure of ultra low k dielectric materials in the copper-connection metal of follow-up grinding filling
Wound, the OMCTS layers 203a transition material layer functioned as between ultra low k dielectric materials and TEOS is to increase therebetween
Adhesive force.
Hard mask layer 204 includes the metal hard mask layer 204a and oxide hard-mask layer stacked gradually from bottom to top
204b, the structure of this double-deck hard mask layer can ensure Dual graphing or the craft precision of multiple graphical, ensure in
The depth of whole groove figures and the uniformity of side wall profile formed needed for hard mask layer 204, i.e., will first have different spies
The channel patterns for levying size are formed in oxide hard-mask layer 204b, then using oxide hard-mask layer 204b as mask etch gold
Category hard mask layer 204a makes the groove figure of required formation in hard mask layer 204.Metal hard mask layer 204a composition material
Material includes TiN, BN, AlN or its arbitrary combination, preferably TiN；Oxide hard-mask layer 204b constituent material includes
SiO2, SiON etc., and require that it has preferable etching selectivity relative to metal hard mask layer 204a constituent material.
Then, as shown in Figure 2 B, the first opening 205 is formed in hard mask layer 204, to expose the cushion 203 of lower section.
First opening 205 is used as the patterns of the grooves in copper metal interconnection structure, and it can include multiple with different characteristic size
Figure.
According to the situation of the figure of required formation, need to implement the patterning process of the channel patterns twice or repeatedly, every time
Implementation comprises the following steps：ODL layers are sequentially formed on oxide hard-mask layer 204b（Organic dielectric layer）, BARC layer（Bottom
Portion's ARC）With PR layers（Photoresist layer）；Photoetching, development treatment are carried out to PR layers, to form channel patterns in PR layers；
Using the PR layers of patterning as mask, BARC layer, ODL layers and oxide hard-mask layer 204b are etched successively, in oxide hardmask
Channel patterns are formed in layer 204b；PR layers, BARC layer and the ODL layers of patterning are removed using techniques such as ashing.Finally, with it
The oxide hard-mask layer 204b of channel patterns needed for middle formation whole is mask, etches metal hard mask layer 204a, completes the
The making of one opening 205.
Next, wet cleaning processes are performed, using basic solvent（Alkaline solvent）It is clear as the wet method
The cleaning fluid washed.The preferred 9.0-11.0 of pH value of the basic solvent.Meeting the basic solvent of the pH value condition includes the U.S.
E.I.Du Pont Company produce EKC, for EKC functional component, including oxidant, etchant, chelating agent, pH value conditioning agent,
Corrosion inhibiter and water.
Then, as shown in Figure 2 C, the second opening 206 is formed in cushion 203 and low k dielectric 202, described second opens
Mouth 206 is used as the patterns of the through hole in copper metal interconnection structure, and it can also include multiple figures with different characteristic size.
According to the situation of the figure of required formation, need to implement the patterning process of the through-hole pattern twice or repeatedly, every time
Implementation comprises the following steps：Sequentially form ODL layers, HMDS layers, BARC layer and PR layers on semiconductor substrate 200, covering the
One opening 205；Photoetching, development treatment are carried out to PR layers, to form through-hole pattern in PR layers；PR layers using patterning is cover
Film, BARC layer, HMDS layers, ODL layers, cushion 203 and part low k dielectric 202 are etched successively, be situated between in cushion 203 and low k
Through-hole pattern is formed in electric layer 202；PR layers, BARC layer, HMDS layers and the ODL layers of patterning are removed using techniques such as ashing.
Because the basic solvent will not cause to damage to the TEOS layers 203b in cushion 203, would not also cause
The exposure of OMCTS layers 203a below TEOS layers 203b, therefore, the ODL of formation will not form Si-N-H-F bases with OMCTS
The chemical reaction of group.
Then, as shown in Figure 2 D, it is mask with hard mask layer 204, performs integrated etching technics synchronization etch buffer layers
203 and low k dielectric 202, to form copper metal interconnection structure 207 in low k dielectric 202, i.e., synchronous formation copper metal is mutual
Link the groove and through hole in structure 207.The integration is etched in when exposing etching stopping layer 201 and terminated.
Then, as shown in Figure 2 E, the etching stopping layer 201 exposed by copper metal interconnection structure 207 is removed, so that copper is golden
Category interconnection structure 207 connects with the front-end devices being formed in Semiconductor substrate 200.In the present embodiment, using dry etching
The removal of etching stopping layer 201 described in process implementing.Then, before filling copper metal in copper metal interconnection structure 207, perform
Last handling process is etched, to remove residue and impurity caused by foregoing etching process, ensures the diffusion of subsequent deposition copper metal
Deposition quality both when barrier layer and copper metal Seed Layer.
Then, as shown in Figure 2 F, copper metal layer 208 is formed in copper metal interconnection structure 207.Form copper metal layer 208
It can use the various suitable technologies that be familiar with of those skilled in the art, such as electroplating technology and the chemistry then implemented
Mechanical milling tech.The purpose for implementing cmp is the surface for the surface and hard mask layer 204 for making copper metal layer 208
Concordantly.
Formed before copper metal layer 208, copper metal need to be sequentially formed on the bottom of copper metal interconnection structure 207 and side wall
Diffusion impervious layer 209 and copper metal Seed Layer 210, copper metal diffusion impervious layer 209 can prevent copper in copper metal layer 208 to
Diffusion in low k dielectric 202, copper metal Seed Layer 210 can strengthen copper metal layer 208 and copper metal diffusion impervious layer 209
Between tack.Those skilled in the art institute can be used by forming copper metal diffusion impervious layer 209 and copper metal Seed Layer 210
The various suitable technologies being familiar with, for example, forming copper metal diffusion impervious layer 209 using physical gas-phase deposition, adopt
Copper metal Seed Layer 210 is formed with sputtering technology or chemical vapor deposition method.The material of copper metal diffusion impervious layer 209 is
Metal, metal nitride or its combination, preferably Ta and TaN combination or Ti and TiN combination..
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, can pass through
Subsequent technique completes the making of whole semiconductor devices.According to the present invention, the hydrofluoric acid conduct of dilution is substituted using basic solvent
The cleaning fluid for the wet-cleaning implemented is formed after the first opening 205, it is possible to prevente effectively from when generation is subsequently formed the second opening 206
The defects of appearance, improve the process window of integration etching.
Reference picture 3, it illustrated therein is the stream that method according to an exemplary embodiment of the present invention improves dual damascene process
Cheng Tu, for schematically illustrating the flow of whole manufacturing process.
In step 301, there is provided Semiconductor substrate, sequentially form etching stopping layer, low k dielectric on a semiconductor substrate
Layer, cushion and hard mask layer；
In step 302, the first opening is formed in hard mask layer, to expose cushion；
In step 303, wet cleaning processes are performed, using cleaning fluid of the basic solvent as the wet-cleaning；
In step 304, the second opening is formed in cushion and low k dielectric；
In step 305, copper metal interconnection structure is formed in low k dielectric；
Within step 306, copper metal layer is formed in copper metal interconnection structure.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, sequentially forms etching stopping layer, low k dielectric, cushion and hard on the semiconductor substrate
Mask layer, the cushion is cyclized tetrasiloxane layer by the prestox being laminated from bottom to top and teos layer is formed；
The first opening is formed in the hard mask layer, to expose the cushion；
Wet cleaning processes are performed, using cleaning fluid of the basic solvent as the wet-cleaning, to avoid generation from being subsequently formed
The defects of occurring during the second opening；
The second opening is formed in the cushion and the low k dielectric；
Copper metal interconnection structure is formed in the low k dielectric.
2. according to the method for claim 1, it is characterised in that the pH value of the basic solvent is 9.0-11.0.
3. according to the method for claim 1, it is characterised in that first opening is used as in the copper metal interconnection structure
Groove pattern, it is described second opening be used as the copper metal interconnection structure in through hole pattern.
4. according to the method for claim 1, it is characterised in that using the hard mask layer as mask, delay with described in step etching
Layer and the low k dielectric are rushed, to form the copper metal interconnection structure in the low k dielectric.
5. according to the method for claim 4, it is characterised in that after the etching terminates, in addition to removal passes through institute
The step of stating etching stopping layer and the implementation etching post processing that copper metal interconnection structure exposes.
6. according to the method for claim 5, it is characterised in that after the etching post processing, be additionally included in the copper
The step of copper metal layer is formed in metal interconnection structure.
7. according to the method for claim 6, it is characterised in that formed before the copper metal layer, be additionally included in the copper
The step of copper metal diffusion impervious layer and copper metal Seed Layer are sequentially formed on the bottom of metal interconnection structure and side wall.
8. according to the method for claim 1, it is characterised in that the hard mask layer is covered by the metallic hard being laminated from bottom to top
Film layer and oxide hard-mask layer are formed.
9. according to the method for claim 8, it is characterised in that the constituent material of the metal hard mask layer be TiN, BN,
AlN or its combination.
10. according to the method for claim 9, it is characterised in that the constituent material of the oxide hard-mask layer includes SiO2
Or SiON, and there is preferable etching selectivity relative to the constituent material of the metal hard mask layer.
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| CN201310231922.9A CN104241114B (en) | 2013-06-09 | 2013-06-09 | A kind of manufacture method of semiconductor devices |
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| US10242876B2 (en) * | 2015-03-26 | 2019-03-26 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
| CN112863999B (en) * | 2019-11-26 | 2023-10-27 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN116130353A (en) * | 2023-01-03 | 2023-05-16 | 芯众享(成都)微电子有限公司 | Method for forming trench structure with complex geometric section on semiconductor surface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300291C (en) * | 2002-09-09 | 2007-02-14 | 三菱瓦斯化学株式会社 | Cleaning composition |
| CN101154046A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for double-mosaic structure |
| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
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| US6583047B2 (en) * | 2000-12-26 | 2003-06-24 | Honeywell International, Inc. | Method for eliminating reaction between photoresist and OSG |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300291C (en) * | 2002-09-09 | 2007-02-14 | 三菱瓦斯化学株式会社 | Cleaning composition |
| CN101154046A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for double-mosaic structure |
| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
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