CN104241107A - Semiconductor structure and making method thereof - Google Patents
Semiconductor structure and making method thereof Download PDFInfo
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- CN104241107A CN104241107A CN201310224713.1A CN201310224713A CN104241107A CN 104241107 A CN104241107 A CN 104241107A CN 201310224713 A CN201310224713 A CN 201310224713A CN 104241107 A CN104241107 A CN 104241107A
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- grid
- contact plug
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- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims description 52
- 238000004519 manufacturing process Methods 0.000 claims description 35
- 239000011159 matrix material Substances 0.000 claims description 24
- 229910010038 TiAl Inorganic materials 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- 229910052721 tungsten Inorganic materials 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 1
- 230000009286 beneficial effect Effects 0.000 description 16
- 230000008569 process Effects 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 5
- 229910010037 TiAlN Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004491 TaAlN Inorganic materials 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor structure comprising a first contact plug and at least two gate stacking structures; each gate stacking structure is formed on an active zone or an isolation zone, and comprises a metal grid electrode; the first contact plug is clamped between the gate stacking structures, and made of the material being same with that of the metal grid electrode; a second contact plug is positioned above part of the first contact plug and part of the gate stacking structure; correspondingly, the invention also provides a making method of the semiconductor structure; the structure and method can enlarge a technical window when the contact plug is formed, and effectively prevents over-etching phenomenon in a contact hole forming step.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly relate to a kind of semiconductor structure and manufacture method thereof.
Background technology
The manufacture method of existing semiconductor device comprises: as shown in Figure 1, form grid 14 and side wall 16 over the semiconductor substrate 10, described grid 14 is formed in described Semiconductor substrate 10 through gate dielectric layer 12, described side wall 16 covers side relative in described grid 14, then forms source/drain region 20 and contact layer 18 (as metal silicide layer); As shown in Figure 2, form the dielectric layer 22 of planarization, the dielectric layer 22 of described planarization covers described grid 14 and side wall 16; Then, utilize mask, etch described dielectric layer 22, to form contact plug.
Wherein, the step forming described contact plug comprises: first, as shown in Figure 3, in described dielectric layer 22, forms contact hole 30, contact layer 18 described in grid 14 described in described contact hole 30 expose portion and expose portion; Subsequently, as shown in Figure 4, fill described contact hole 30, form conductive layer 34; Then, as shown in Figure 5, conductive layer 34 described in planarization is to expose described dielectric layer 22; Finally, conveniently the step of semiconductor fabrication process completes the manufacture of this semiconductor device.
But above-mentioned manufacture method exists certain weak point: the first, along with spacing between semiconductor device (pitch) is more and more less, cause process window when forming contact plug more and more less; The second, owing to there is certain difference in height distance between top portions of gates and contact layer, so formed in the process of contact hole at etch media layer, easily caused the appearance of carving phenomenon, in order to prevent the appearance of carving phenomenon, often need to adopt comparatively complicated etching technics, thus add the complexity of semiconductor fabrication process.
Therefore, need a kind of new semiconductor structure fabrication processes, solve the problem.
Summary of the invention
The invention provides a kind of semiconductor device and manufacture method thereof, be not only beneficial to the process window expanded when forming contact plug, and in the process forming contact hole, effectively prevent the appearance of carving phenomenon.
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor structure, this manufacture method comprises the following steps:
Form at least two stacking matrixes of grid and side wall on a semiconductor substrate, the stacking matrix of each described grid is formed in active area or isolated area, the stacking matrix of each described grid comprises gate dielectric layer and pseudo-grid, described pseudo-grid are formed on described semiconductor base through described gate dielectric layer, and described side wall to be formed on described gate dielectric layer around described pseudo-grid and described gate dielectric layer or described side wall and around described pseudo-grid;
Form material layer, described material layer exposes described pseudo-grid and described side wall and is sandwiched between the stacking matrix of each described grid;
Remove described pseudo-grid and described material layer, to form groove;
After groove described in the first filled with conductive material, the first electric conducting material described in planarization, to expose described side wall;
Disconnect described first electric conducting material of described side wall periphery, to form at least two electric conductors, each described electric conductor is only connected to the described active area of the peripheral side of described side wall, and forms grid stacked structure and the first contact plug;
Described grid stacked structure and the first contact plug form the second contact plug.
According to another aspect of the present invention, additionally provide a kind of manufacture method of semiconductor structure, this manufacture method comprises the following steps:
Form at least two stacking matrixes of grid on a semiconductor substrate, the stacking matrix of each described grid is formed in active area or isolated area, and the stacking matrix of each described grid comprises gate dielectric layer and pseudo-grid, and described pseudo-grid are formed on described semiconductor base through described gate dielectric layer;
Form mask layer, described mask layer is around the stacking matrix of described grid and expose described active area at least partially, to form contact zone;
Form material layer, described material layer is filled described contact zone and is exposed described pseudo-grid and described mask layer;
Remove described pseudo-grid and described material layer, to form groove;
After groove described in the first filled with conductive material, the first electric conducting material described in planarization, to expose described mask layer, forms grid stacked structure and the first contact plug;
Described grid stacked structure and the first contact plug form the second contact plug.
According to a further aspect of the invention, additionally provide a kind of semiconductor structure, comprise: the first contact plug, the second contact plug and at least two grid stacked structures, each described grid stacked structure is formed in active area or isolated area, and each described grid stacked structure includes metal gates; Described first contact plug is sandwiched between each described grid stacked structure, and described first contact plug material is identical with described metal gate material; Described second contact plug is positioned on described first contact plug of part and the described grid stacked structure of part.
Compared with prior art, technical scheme tool provided by the invention is adopted to have the following advantages:
(1) when adopting replacement gate process, by making material layer identical with described pseudo-grid material, can when removing pseudo-grid, the described material layer of synchronous removal, to form groove; Then, after groove described in filled with conductive material, electric conducting material described in planarization, can expose described side wall and form grid stacked structure and the first contact plug; Be beneficial to and make full use of limited spacing, in the space occupied by described spacing, all fill described electric conducting material to form described contact plug, that is, self-registered technology can be adopted to form described contact plug, be beneficial to the process window expanded when forming contact plug; And the described pseudo-grid of synchronous removal and described material layer, be beneficial to Simplified flowsheet and reduce the damage of removal operation to semiconductor base;
(2) in the process of formation second contact plug, due to the upper surface of the first contact plug and the upper surface flush of grid stacked structure, so in etch media layer forms contact hole on the first contact plug and grid stacked structure, there will not be the phenomenon of carving.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 to Fig. 5 is the generalized section of each intermediate structure when forming semiconductor structure in prior art;
Fig. 6 is the manufacture method flow chart of semiconductor structure according to an embodiment of the invention;
Fig. 7 to Figure 17 is for according to the generalized section of the present invention's specific embodiment according to each stage of the semiconductor structure of flow manufacturing shown in Fig. 6;
Figure 18 is the manufacture method flow chart of semiconductor structure in accordance with another embodiment of the present invention; And
Figure 19 to Figure 27 is for according to the schematic top plan view of another specific embodiment of the present invention according to each stage of the semiconductor structure of flow manufacturing shown in Figure 18.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can in different example repeat reference numerals and/or letter.This repetition is to simplify and clearly object, itself does not indicate the relation between discussed various embodiment and/or setting.In addition, the invention provides the example of various specific technique and material, but those skilled in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.It should be noted that parts illustrated in the accompanying drawings are not necessarily drawn in proportion.Present invention omits the description of known assemblies and treatment technology and process to avoid unnecessarily limiting the present invention.
According to an aspect of the present invention, a kind of manufacture method of semiconductor structure is provided.Below, composition graphs 7 to Figure 17 is described the manufacture method of semiconductor structure in Fig. 6 particularly by one embodiment of the present of invention.As shown in Figure 6, this manufacture method comprises the following steps:
In step S101, semiconductor base 100 is formed at least two stacking matrixes of grid and side wall 106, the stacking matrix of each described grid is formed in active area or isolated area 101, the stacking matrix of each described grid comprises gate dielectric layer 102 and pseudo-grid 104, described pseudo-grid 104 are formed on described semiconductor base 100 through described gate dielectric layer 102, and described side wall 106 to be formed on described gate dielectric layer 102 around described pseudo-grid 104 and described gate dielectric layer 102 or described side wall 106 and around described pseudo-grid 104.
Particularly, as shown in Figure 7, semiconductor base 100 is formed at least two stacking matrixes of grid and side wall 106, the stacking matrix of described grid is formed at (each described active area is isolated by described isolated area 101) in active area or isolated area 101, the stacking matrix of each described grid comprises gate dielectric layer 102 and pseudo-grid 104, described pseudo-grid 104 are formed on described semiconductor base 100 through described gate dielectric layer 102, and described side wall 106 is around described pseudo-grid 104 and described gate dielectric layer 102 (the present embodiment; Be beneficial to and reduce parasitic capacitance), or described side wall 106 to be formed on described gate dielectric layer 102 and around described pseudo-grid 104 (other embodiments).
Wherein, in the present embodiment, described semiconductor base 100 can be silicon substrate, and preferably, described semiconductor base 100 is silicon epitaxy layer, and described semiconductor base 100 also can be silicon-on-insulator (SOI).Described gate dielectric layer 102 can select hafnium sill, as HfO
2, one in HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or its combination, or, can Al be selected
2o
3, La
2o
3, ZrO
2or a kind of in LaAlO or its combination and the combination with hafnium sill thereof.Side wall 106 can comprise one in silicon nitride, silica, silicon oxynitride, carborundum or its combination.Side wall 106 can have sandwich construction.Described pseudo-grid 104 can be doping or unadulterated polysilicon or amorphous silicon (doped chemical can be B, P or As etc.), be preferably doping or unadulterated polysilicon, be beneficial to the size accurately controlling described pseudo-grid 104, then, be beneficial to the size of the grid accurately controlling follow-up formation.In other embodiments, described pseudo-grid 104 also can be other insulating material differing from described side wall 106 material, other semi-conducting materials differing from described semiconductor base 100 material, or, be electric conducting material.
After its formation before continuous material layer, also need to form source/drain region 120.In the present embodiment, described source/drain region 120 can be formed afterwards injecting in described silicon substrate ion (e.g., doped with boron, phosphorus or arsenic), and described source/drain region 120 can be the silicon materials of N-type or P type.And form contact layer 122 (as metal silicide layer) on surface, described source/drain region 120.
In addition, in other embodiments, the step forming described source/drain region 120 also can comprise: first, with the stacking matrix of described grid for mask, described semiconductor base 100 forms groove, to expose described semiconductor base 100 material; Subsequently, with described semiconductor base 100 material exposed for seed crystal, generate semi-conducting material, to fill described groove.
For PMOS device, described semi-conducting material is Si
1-Xge
x, the span of X is 0.1 ~ 0.7, as 0.2,0.3,0.4,0.5 or 0.6; For nmos device, described semi-conducting material is the span of the atomicity percentage of SiC, C is 0.2% ~ 2%, as 0.5%, 1% or 1.5%.Can in the reactant generating silicon, mix the reactant that comprises Doped ions composition and directly form described semi-conducting material.Subsequently, the described source/drain region 120 exposed forms metal silicide layer (being also formed with described metal silicide layer on described pseudo-grid 104), be beneficial to the contact resistance between the first contact plug and described semiconductor base 100 reducing follow-up formation.In other embodiments, after described metal silicide layer also can be formed at and remove described pseudo-grid 104, before filled conductive material.
In step s 102, form material layer 140, described material layer 140 exposes described pseudo-grid 104 and described side wall 106 and is sandwiched between the stacking matrix of each described grid, preferably, described material layer 140 material is identical with described pseudo-grid 104 material, can remove described material layer 140 like this while the pseudo-grid 104 of removal.
Particularly, first, as shown in Figure 8, form material layer 140, described material layer 140 covers the stacking matrix of described grid and fills the space between the stacking matrix of each described grid; Subsequently, as shown in Figure 9, material layer 140 described in planarization, to expose described pseudo-grid 104 and described side wall 106.
Described material layer 140 material can be identical with described pseudo-grid 104 material, can when the pseudo-grid 104 of follow-up removal, the described material layer 140 of synchronous removal, is beneficial to Simplified flowsheet and reduces the damage of removal operation to semiconductor base.Cmp (CMP) technique can be adopted to perform planarization Operation.
In step s 103, remove described pseudo-grid 104 and described material layer 140, to form groove 108.
Particularly, as shown in Figure 10, described pseudo-grid 104 and described material layer 140 is removed, to form groove 108.The anisotropic etch process such as reactive ion etching (RIE) can be adopted to perform described removal operation.
In step S104, after filling described groove 108 with the first electric conducting material 160, the first electric conducting material 160 described in planarization, to expose described side wall 106, as is illustrated by figs. 11 and 12.Wherein, the material of described first electric conducting material 160 comprises the combination of a kind of or its combination and W, Al or TiAl and Cu in W, Al, TiAl.In presents, " combination of W, Al or TiAl and Cu " means: the diapire and the sidewall that first cover described groove 108 with W, Al or TiAl layer, then is formed on W, Al or TiAl layer with Cu layer, is beneficial to minimizing Cu and spreads to described semiconductor base 100.
Preferably, before described first electric conducting material 160 of filling, form the first contact layer (not shown), described first contact layer covers diapire and the sidewall of described groove 108.Described first contact layer can comprise one in TiN, TiAlN or its combination, is beneficial to the contact resistance between reduction by first electric conducting material 160 and contact layer 122.
In step S105, disconnect described first electric conducting material 160 of described side wall 106 periphery, to form at least two electric conductors, each described electric conductor is only connected to the described active area of the described peripheral side of side wall 106, and forms grid stacked structure and the first contact plug.
Particularly, after the first electric conducting material 160 described in planarization, described first electric conducting material 160 is divided into two parts, a part is present in the inner side of described side wall 106, be positioned on described gate dielectric layer 102, and another part is looped around the periphery of described side wall 106, is positioned on described active area.Due to the first electric conducting material 160 being positioned at described side wall 106 periphery be one interconnective, so need to disconnect described first electric conducting material 160 being positioned at described side wall 106 periphery, to form at least two electric conductors, wherein, each described electric conductor is only connected to the described active area of the described peripheral side of side wall 106.Thus, be present in the first electric conducting material 160 (i.e. metal gates) inside described side wall 106 and described gate dielectric layer 122 and described side wall 106 and constitute grid stacked structure, and the first electric conducting material 160 be filled between described side wall 106 periphery defines the first contact plug.
In step s 106, described grid stacked structure and the first contact plug form the second contact plug.
Particularly, first, as shown in figure 13, form the dielectric layer 200 of planarization, the dielectric layer 200 of described planarization covers described grid stacked structure and described first contact plug; Then, as shown in figure 14, in the dielectric layer 200 of described planarization, form contact hole 210, described contact hole 210 is positioned on described grid stacked structure and on described first contact plug, grid stacked structure described in expose portion and described first contact plug of part; Then, as shown in Figure 15 and Figure 16, the second electric conducting material 220 is used to fill described contact hole 210, and the second electric conducting material 220 described in planarization, to expose described dielectric layer 200, form the second contact plug being connected to described first contact plug and described grid stacked structure.Wherein, described second electric conducting material 220 comprises one in W, Al, Cu, TiAl or its combination.
Preferably, before described second electric conducting material 220 of filling, form the second contact layer (not shown), described second contact layer covers diapire and the sidewall of described contact hole 210.Described second contact layer can comprise one in TiN, TiAlN, TaN, TaAlN, TaC or its combination, is beneficial to the contact resistance between reduction by second contact plug and the first contact plug, metal gates.
Alternatively, as shown in figure 17, after formation second contact plug, described dielectric layer 200 is removed by the mode of selective etch.
In the process performing above-mentioned manufacture method, described pseudo-grid 104, described material layer 140 and described dielectric layer 200 all can adopt chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or other technique be applicable to be formed.Wherein, described pseudo-grid 104, described material layer 140 and described dielectric layer 200 all can comprise silica (USG), the silica (as fluorine silex glass, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass) of doping, the one in low k dielectric material (as black diamond, coral etc.) or its combination.Described pseudo-grid 104, described material layer 140 and described dielectric layer 200 all can have sandwich construction.Described dielectric layer 200 material and described pseudo-grid 104 may be the same or different.Cmp (CMP) technique can be adopted to perform described planarization Operation.
According to another aspect of the present invention, a kind of manufacture method of semiconductor structure is additionally provided.Below, the manufacture method of semiconductor structure in Figure 18 is described in conjunction with Figure 19 to Figure 27 particularly by one embodiment of the present of invention.As shown in figure 18, this manufacture method comprises the following steps:
In step s 201, as shown in Figures 18 and 19, semiconductor base (not shown) is formed at least two stacking matrixes of grid, the stacking matrix of each described grid is formed in active area 103 and isolated area 101, the stacking matrix of each described grid comprises gate dielectric layer (not shown) and pseudo-grid 104, and described pseudo-grid 104 are formed on described semiconductor base through described gate dielectric layer;
In step S202, as shown in figure 20, form mask layer 105, described mask layer 105 around the stacking matrix of described grid and expose described active area 103 (please refer to Figure 19) (in the present embodiment, expose the whole active areas 103 outside the stacking matrix of described grid at least partially, in other embodiments, can active area 103 described in expose portion), to form contact zone.Preferably, the surface of contact zone is formed the contact layer 122 being beneficial to and reducing source/drain region contact resistance.Wherein, described mask layer 105 can be arbitrary insulating material, as the one in silicon nitride, silicon oxynitride, carborundum or fire sand or its combination (as can be sandwich construction).Described mask layer 105 can adopt depositing-etching technique to be formed;
In step S203, as shown in figure 21, form material layer 140, described material layer 140 is filled described contact zone and is exposed described pseudo-grid 104 and described mask layer 105, and described material layer 140 material is identical with described pseudo-grid 104 material.Wherein, described material layer 140 material and described pseudo-grid 104 material are adulterate or the polysilicon of undoped or amorphous silicon;
In step S204, as shown in figure 22, described pseudo-grid 104 (exposing described gate dielectric layer 102) and described material layer 140 (exposing described contact layer 122) is removed, to form groove;
In step S205, as shown in figure 23, after filling described groove with the first electric conducting material 160, the first electric conducting material 160 described in planarization, to expose described mask layer 105, forms grid stacked structure and the first contact plug.Wherein, described first electric conducting material 160 comprises the combination of a kind of or its combination and W, Al or TiAl and Cu in W, Al, TiAl;
In step S206, as shown in Figure 24 to Figure 27, described grid stacked structure and the first contact plug form the second contact plug.Wherein, first, as shown in figure 24, form the dielectric layer 200 of planarization, the dielectric layer 200 of described planarization covers described grid stacked structure and described first contact plug; Then, as shown in figure 25, contact hole is formed in the dielectric layer 200 of described planarization, first contact plug described in described contact holes exposing part and the described grid stacked structure of part (for clarity, be represented by dotted lines in figure be positioned at the first contact plug under dielectric layer 200 and grid stacked structure); Then, as shown in figure 26, after filling described contact hole with the second electric conducting material 220, second electric conducting material 220 described in planarization, to expose described dielectric layer 200, forms the second contact plug, wherein, described second electric conducting material 220 comprises one in W, Al, Cu, TiAl or its combination.Alternatively, as shown in figure 27, after formation second contact plug, described dielectric layer 200 is removed by the mode of selective etch.
The composition of the other materials involved by the present embodiment and manufacturing process, with described in previous embodiment, repeat no more.
Compared with prior art, the manufacture method of semiconductor structure provided by the present invention has the following advantages:
(1) when adopting replacement gate process, by making material layer material identical with described pseudo-grid material, can when removing pseudo-grid, the described material layer of synchronous removal, to form groove; Then, after groove described in filled with conductive material, electric conducting material described in planarization, can expose described side wall and form grid stacked structure and the first contact plug; Be beneficial to and make full use of limited spacing, described electric conducting material is all filled to form described first contact plug in the space occupied by described spacing, that is, self-registered technology can be adopted to form described first contact plug, be beneficial to process window when expanding formation the first contact plug; And the described pseudo-grid of synchronous removal and described material layer, be beneficial to Simplified flowsheet and reduce the damage of removal operation to semiconductor base;
(2) in the process of formation second contact plug, due to the upper surface of the first contact plug and the upper surface flush of grid stacked structure, so in etch media layer forms contact hole on the first contact plug and grid stacked structure, there will not be the phenomenon of carving.
According to a further aspect of the invention, additionally provide a kind of semiconductor structure, please refer to Figure 16 and Figure 17.As shown in the figure, described semiconductor structure comprises: the first contact plug and at least two grid stacked structures, and each described grid stacked structure is formed in active area or isolated area 101, and each described grid stacked structure includes metal gates; Described first contact plug is sandwiched between each described grid stacked structure, and described first contact plug material is identical with described metal gate material; Described second contact plug is positioned on described first contact plug of part and the described grid stacked structure of part.
Particularly, described active area or isolated area 101 are arranged in semiconductor base 100, described active area are formed with source/drain region 120 and contact layer 122 (described contact layer 122 can be by the metal silicide layer formed after the top layer of described source/drain region 120 and metal reaction).
The described grid stacked structure be positioned in active area or isolated area 101 comprises gate dielectric layer 102, metal gates and side wall 106, described metal gates is formed on described semiconductor base 100 through described gate dielectric layer 102, described side wall 106 is around described metal gates and described gate dielectric layer 102, or described side wall 106 to be formed on described gate dielectric layer 102 and around described metal gates.
The material being sandwiched in described first contact plug between each described grid stacked structure is identical with the material of described metal gates, comprises the combination of a kind of or its combination and W, Al or TiAl and the Cu in W, Al, TiAl.
Described second contact plug is formed on described first contact plug and described grid stacked structure, and be connected with described first contact plug of part and the described grid stacked structure of part, wherein, described second contact plug material comprises one in W, Al, Cu, TiAl or its combination.
Preferably, also there is the first contact layer (not shown) between described first contact plug and contact layer 122, wherein, described first contact layer comprises one in TiN, TiAlN or its combination.
Preferably, between described second contact plug and the first contact plug 180 and grid stacked structure, also there is the second contact layer (not shown), wherein, described second contact layer comprises one in TiN, TiAlN, TaN, TaAlN, TaC or its combination.
Compared with prior art, semiconductor structure provided by the present invention has the following advantages: the first contact plug occupies spaces all between grid stacked structure, not only takes full advantage of limited spacing, and is easy to manufacture; Second contact plug is positioned on the first contact plug and grid stacked structure, is in same level bottom it, and its manufacturing process of contact plug with this structure is relatively simple, is easy to equally manufacture.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (10)
1. a manufacture method for semiconductor structure, the method comprises the following steps:
At semiconductor base (100) upper formation at least two stacking matrixes of grid and side wall (106), the stacking matrix of each described grid is formed in active area or isolated area (101), the stacking matrix of each described grid comprises gate dielectric layer (102) and pseudo-grid (104), described pseudo-grid (104) are formed on described semiconductor base (100) through described gate dielectric layer (102), it is upper and around described pseudo-grid (104) that described side wall (106) is formed at described gate dielectric layer (102) around described pseudo-grid (104) and described gate dielectric layer (102) or described side wall (106),
Form material layer (140), described material layer (140) exposes described pseudo-grid (104) and described side wall (106) and is sandwiched between the stacking matrix of each described grid;
Remove described pseudo-grid (104) and described material layer (140), to form groove (108);
After filling described groove (108) with the first electric conducting material (160), the first electric conducting material (160) described in planarization, to expose described side wall (106);
Disconnect described first electric conducting material (160) that described side wall (106) is peripheral, to form at least two electric conductors, each described electric conductor is only connected to the described active area of described side wall (106) peripheral side, and forms grid stacked structure and the first contact plug; And
Described grid stacked structure and the first contact plug form the second contact plug.
2. a manufacture method for semiconductor structure, the method comprises the following steps:
At the upper formation of semiconductor base (100) at least two stacking matrixes of grid, the stacking matrix of each described grid is formed in active area or isolated area (101), the stacking matrix of each described grid comprises gate dielectric layer (102) and pseudo-grid (104), and described pseudo-grid (104) are formed on described semiconductor base (100) through described gate dielectric layer (102);
Form mask layer (105), described mask layer (105) is around the stacking matrix of described grid and expose described active area at least partially, to form contact zone;
Form material layer (140), described material layer (140) is filled described contact zone and is exposed described pseudo-grid (104) and described mask layer (105);
Remove described pseudo-grid (104) and described material layer (140), to form groove;
After filling described groove with the first electric conducting material (160), the first electric conducting material (160) described in planarization, to expose described mask layer (105), forms grid stacked structure and the first contact plug; And
Described grid stacked structure and the first contact plug form the second contact plug.
3. method according to claim 1 and 2, is characterized in that:
Described material layer (140) material and described pseudo-grid (104) material are adulterate or the polysilicon of undoped or amorphous silicon.
4. method according to claim 1 and 2, is characterized in that:
Described first electric conducting material (160) comprises the combination of a kind of or its combination and W, Al or TiAl and Cu in W, Al, TiAl.
5. method according to claim 1 and 2, is characterized in that, the step that described grid stacked structure and the first contact plug are formed the second contact plug comprises:
Form the dielectric layer (200) of planarization, the dielectric layer (200) of described planarization covers described grid stacked structure and described first contact plug;
Contact hole (210) is formed, the first contact plug described in described contact hole (210) expose portion and the described grid stacked structure of part in the dielectric layer (200) of described planarization;
After filling described contact hole (210) with the second electric conducting material (220), the second electric conducting material (220) described in planarization, to expose described dielectric layer (200), forms the second contact plug.
6. method according to claim 5, is characterized in that, after forming the second contact plug, removes described dielectric layer (200).
7. the method according to claim 5 or 6, is characterized in that:
Described second electric conducting material (220) comprises one in W, Al, Cu, TiAl or its combination.
8. method according to claim 1 and 2, is characterized in that:
Described material layer (140) material is identical with described pseudo-grid (104) material.
9. a semiconductor structure, described semiconductor structure comprises the first contact plug, the second contact plug and at least two grid stacked structures, each described grid stacked structure is formed in active area or isolated area, and each described grid stacked structure includes metal gates, it is characterized in that:
Described first contact plug is sandwiched between each described grid stacked structure, and described first contact plug material is identical with described metal gate material; And
Described second contact plug is positioned on described first contact plug of part and the described grid stacked structure of part.
10. semiconductor structure according to claim 9, is characterized in that:
Described first contact plug material comprises the combination of a kind of or its combination and W, Al or TiAl and Cu in W, Al, TiAl.
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| CN102024744A (en) * | 2009-09-16 | 2011-04-20 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| KR20110069305A (en) * | 2009-12-17 | 2011-06-23 | 주식회사 동부하이텍 | Flash memory device and method of manufacturing the same |
| CN102468174A (en) * | 2010-11-18 | 2012-05-23 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
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| US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
| CN102024744A (en) * | 2009-09-16 | 2011-04-20 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| KR20110069305A (en) * | 2009-12-17 | 2011-06-23 | 주식회사 동부하이텍 | Flash memory device and method of manufacturing the same |
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Application publication date: 20141224 |