CN104202062A - USB difference receiver in wide common mode input field - Google Patents
USB difference receiver in wide common mode input field Download PDFInfo
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- CN104202062A CN104202062A CN201410494574.9A CN201410494574A CN104202062A CN 104202062 A CN104202062 A CN 104202062A CN 201410494574 A CN201410494574 A CN 201410494574A CN 104202062 A CN104202062 A CN 104202062A
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Abstract
The invention discloses a circuit structure for a USB difference receiver in a wide common mode input field. The circuit comprises an input differential signal level removal circuit and a current bias circuit (M 8-M 13); the circuit further comprises amplifiers (M 0-M 7) of two pairs of difference input geminate transistors. According to the circuit structure, the amplifiers of the two pairs of the difference input geminate transistors are connected to the front and the rear of the differential signal level removal circuit respectively, and through the adoption of the self-adapting current bias circuit, the amplifiers can work normally in the wide common mode input field.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, and be more particularly to the design of USB differential receiver.
Background technology
In USB physical layer circuit, the data that differential receiver is responsible for USB to receive are converted into and meet the electrical characteristic that usb protocol requires.For example usb protocol to signal high-tension minimum value, low level maximum specify, require design circuit need to meet code requirement.Will be subject to the situation impacts such as operating voltage, temperature, transmission attenuation, outside electromagnetic interference when the real work due to usb signal, protocol requirement is generally stricter, and must meet protocol requirement.Wherein the common-mode voltage of differential signal is required as 0.8V ~ 2.5V, the differential data signals of this relative 3.3V is a very wide common-mode input range.
Differential signal receiver has good anti-common mode disturbances ability, and this is also in serial communication, conventionally to adopt differential signal to transmit the reason of data, and differential receiver is used to recover the differential signal of reception.USB agreement requires its electrology characteristic differential receiver: need to accept wider common-mode voltage input range (0.8V ~ 2.5V); Can the signal of recognition differential sub-signal difference more than certain limit, make it have enough differential signal resolution.Can not meet the demands for the most of amplifiers of wider common-mode input range, the input of General N MOS type is high to pipe amplifier input common mode voltage, and pmos type is inputted pipe amplifier.
In order to expand the common-mode input range of amplifier, technology, by nmos type input is combined to pipe amplifier to pipe amplifier and pmos type input, forms the structure of complementary output now.A kind of single-ended receiver of USB of new molded breadth common-mode input range is provided in the present invention.
Summary of the invention
In view of the needs of USB differential receiver to wide common-mode input range, the invention provides a kind of USB differential receiver circuit of wide common-mode input range.
Above-mentioned purpose of the present invention, will be achieved by the following technical programs:
A kind of USB differential receiver circuit of new molded breadth common-mode input range, it is characterized in that: the USB differential receiver circuit of described a kind of wide common-mode input range comprises a pair of differential data signals D0+, D0-, two-way bias current IBIAS1, IBIAS2 and IBIAS1 current mirror circuit, IBIAS2 current mirror circuit, described circuit also comprises that two pairs of difference input the amplifier to pipe, and the USB differential receiver circuit of described a kind of wide common-mode input range also comprises voltage movement circuit.
Further, the current mirror circuit of described bias current IBIAS1 comprises metal-oxide-semiconductor M8, the drain electrode of described metal-oxide-semiconductor M8 connects biasing circuit IBIAS1, the drain electrode of described metal-oxide-semiconductor M8 is connected with grid, the source ground of described metal-oxide-semiconductor M8, the grid that the grid of described metal-oxide-semiconductor M8 is connected to metal-oxide-semiconductor M6 provides tail current for amplifier, and described metal-oxide-semiconductor M6, M8 is N-type MOS.
Further, the current mirror circuit of described bias current IBIAS2 comprises metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, described metal-oxide-semiconductor M13 drain electrode is with grid short circuit and be connected to bias current IBIAS2, described metal-oxide-semiconductor M13 source ground, the grid of described metal-oxide-semiconductor M12 is connected with the grid of metal-oxide-semiconductor M13, the source of described metal-oxide-semiconductor M12 is connected with the drain electrode of metal-oxide-semiconductor M6, the drain electrode of described metal-oxide-semiconductor M10 is connected with grid short circuit and with the drain electrode of metal-oxide-semiconductor M12, the source electrode of described metal-oxide-semiconductor M10 is connected with power supply, the grid of described metal-oxide-semiconductor M11 is connected with the grid of metal-oxide-semiconductor M10, the source electrode of described metal-oxide-semiconductor M11 and power supply phase, the grid of described metal-oxide-semiconductor M9 and drain electrode short circuit and being connected with the drain electrode of metal-oxide-semiconductor M11, the source ground of described metal-oxide-semiconductor M9, the grid of described metal-oxide-semiconductor M9 is connected to metal-oxide-semiconductor M7 and provides another road tail current for amplifier.When the common mode electrical level of input lower when differential pair tube metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 can not be opened, the drain voltage of metal-oxide-semiconductor M6 is very low, thereby bias current IBIAS2 is mirrored onto MOS12, be further mirrored to another road of differential receiver tail circuit metal-oxide-semiconductor M7 by metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11.
Further, described metal-oxide-semiconductor M9, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 is P type metal-oxide-semiconductor.
Further, described two pairs of difference input comprises metal-oxide-semiconductor M0 to the amplifier of pipe, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7, described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 are that a pair of difference input is to pipe, the grid of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 is connected respectively to the differential data signals D0+ of input, D0-, the source shorted of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 and be connected to the drain-gate of metal-oxide-semiconductor M6, the source ground of described metal-oxide-semiconductor M6, the grid of described metal-oxide-semiconductor M6 is connected with metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 is connected respectively to differential data signals D1+, D1-, the source shorted of described metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 and be connected to the drain-gate of metal-oxide-semiconductor M7, the source ground of described metal-oxide-semiconductor M7, the grid of described metal-oxide-semiconductor M7 is connected with the grid of metal-oxide-semiconductor M9, the drain electrode of described metal-oxide-semiconductor M4 is connected with the drain electrode of metal-oxide-semiconductor M0 drain electrode and metal-oxide-semiconductor M2, and the grid of described metal-oxide-semiconductor M4 and drain electrode short circuit, the drain electrode of described metal-oxide-semiconductor M5 is connected with the drain electrode of metal-oxide-semiconductor M1 and the drain electrode of metal-oxide-semiconductor M3, the source electrode of the source electrode of described metal-oxide-semiconductor M4 and metal-oxide-semiconductor M5 is connected with power supply.
Further, described metal-oxide-semiconductor M0, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M4, metal-oxide-semiconductor M5 is P type metal-oxide-semiconductor.
Further, described voltage movement circuit is by the differential data signals D0+ of input and D0-process voltage movement output difference sub-signal D1+ and D1-.
The technical scheme beneficial effect providing of the present invention is: in the time that input common mode electrical level is higher, make the drain voltage comparison high energy of metal-oxide-semiconductor M6 can turn-off metal-oxide-semiconductor M12 and make bias current IBIAS2 can not be mirrored to metal-oxide-semiconductor M7, only differential pair tube metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 work thereby differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 do not work; In the time that input common mode electrical level is lower, metal-oxide-semiconductor M0 and not conducting of metal-oxide-semiconductor M1, at this moment the drain voltage of metal-oxide-semiconductor M6 very low energy metal-oxide-semiconductor M2 is opened bias current IBIAS2 can not be mirrored to metal-oxide-semiconductor M7, thereby the input differential signal of differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 can make differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 work after voltage movement circuit, differential pair tube metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 do not work.By the technical scheme providing, make circuit no matter in high level or low level, almost in full voltage range, can normally work, there is very wide common-mode input range.
Below just accompanying drawing in conjunction with the embodiments, is further described the embodiment of technical scheme provided by the invention, to make the present invention be easier to understand, implement.
Brief description of the drawings
A kind of amplifier architecture without wide common-mode input range of Fig. 1;
Fig. 2 USB differential receiver circuit with wide common-mode input range disclosed by the invention;
A kind of voltage movement circuit of Fig. 3 embodiment of the present invention.
Embodiment
Embodiment will further describe spirit of the present invention, is used for explaining the present invention in this illustrative examples of the present invention and explanation, but can not think limitation of the invention.
Comparison diagram 1 and Fig. 2, in order to solve the narrow problem of common-mode input range in conventional amplifier architecture (example amplifier architecture as shown in Figure 1), the present invention proposes circuit structure as shown in Figure 2.The USB differential receiver circuit of described a kind of new molded breadth common-mode input range comprises a pair of differential data signals D0+, D0-, it is the input signal of differential receiver, the level input range of differential data signals, has proposed requirement to the common-mode input range of differential receiver; Described circuit comprises two-way bias current IBIAS1, IBIAS2 and IBIAS1 current mirror circuit, IBIAS2 current mirror circuit, and two-way bias current provides bias current at different common mode input conditions for differential receiver; Described circuit also comprises that two pairs of difference input the amplifier to pipe, when different common-mode voltage input, opens corresponding input to pipe, and differential receiver can normally be worked; And the USB differential receiver circuit of described a kind of wide common-mode input range also comprises voltage movement circuit, make the input of the applicable differential receiver of common mode incoming level to pipe.
As shown in Figure 2, the current mirror circuit of described bias current IBIAS1 comprises metal-oxide-semiconductor M8, the drain electrode of described metal-oxide-semiconductor M8 connects biasing circuit IBIAS1, the drain electrode of described metal-oxide-semiconductor M8 is connected with grid, the source ground of described metal-oxide-semiconductor M8, the grid of described metal-oxide-semiconductor M8 is connected to the grid of metal-oxide-semiconductor M6, bias current IBIAS1 is mirrored to metal-oxide-semiconductor M6 through metal-oxide-semiconductor M8 according to a certain percentage and provides tail current for amplifier, and described metal-oxide-semiconductor M8 is N-type MOS.
The current mirror circuit of described bias current IBIAS2 comprises metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, described metal-oxide-semiconductor M13 drain electrode is with grid short circuit and be connected to bias current IBIAS2, described metal-oxide-semiconductor M13 source ground, the grid of described metal-oxide-semiconductor M12 is connected with the grid of metal-oxide-semiconductor M13, the source of described metal-oxide-semiconductor M12 is connected with the drain electrode of metal-oxide-semiconductor M6, the drain electrode of described metal-oxide-semiconductor M10 is connected with grid short circuit and with the drain electrode of metal-oxide-semiconductor M12, the source electrode of described metal-oxide-semiconductor M10 is connected with power supply, the grid of described metal-oxide-semiconductor M11 is connected with the grid of metal-oxide-semiconductor M10, the source electrode of described metal-oxide-semiconductor M11 and power supply phase, the grid of described metal-oxide-semiconductor M9 and drain electrode short circuit and being connected with the drain electrode of metal-oxide-semiconductor M11, the source ground of described metal-oxide-semiconductor M9, the grid of described metal-oxide-semiconductor M9 is connected to metal-oxide-semiconductor M7 and in the time that common mode electrical level is lower, provides another road tail current for amplifier.In the time that common mode electrical level is higher, the source voltage terminal of metal-oxide-semiconductor M12 also makes the electric current of IBIAS2 can not be mirrored to by metal-oxide-semiconductor M12 another tail current metal-oxide-semiconductor M7 of amplifier for high; When common mode electrical level is during compared with you, the source voltage terminal of metal-oxide-semiconductor M12 is also mirrored to another tail current metal-oxide-semiconductor M7 of amplifier by metal-oxide-semiconductor M12 for the electric current of the low IBIAS2 of making, and now not conducting of metal-oxide-semiconductor M6.
Described metal-oxide-semiconductor M9, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 is P type metal-oxide-semiconductor.
Described two pairs of difference input comprises metal-oxide-semiconductor M0 to the amplifier of pipe, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7, described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 are that a pair of difference input is to pipe, the grid of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 is connected respectively to the differential data signals D0+ of input, D0-, the source shorted of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 and be connected to the drain-gate of metal-oxide-semiconductor M6, the source ground of described metal-oxide-semiconductor M6, the grid of described metal-oxide-semiconductor M6 is connected with metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 is connected respectively to differential data signals D1+, D1-, the source shorted of described metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 and be connected to the drain-gate of metal-oxide-semiconductor M7, the source ground of described metal-oxide-semiconductor M7, the grid of described metal-oxide-semiconductor M7 is connected with the grid of metal-oxide-semiconductor M9, the drain electrode of described metal-oxide-semiconductor M4 is connected with the drain electrode of metal-oxide-semiconductor M0 drain electrode and metal-oxide-semiconductor M2, and the grid of described metal-oxide-semiconductor M4 and drain electrode short circuit, the drain electrode of described metal-oxide-semiconductor M5 is connected with the drain electrode of metal-oxide-semiconductor M1 and the drain electrode of metal-oxide-semiconductor M3, the source electrode of the source electrode of described metal-oxide-semiconductor M4 and metal-oxide-semiconductor M5 is connected with power supply.In the time that input common mode electrical level is higher, make the drain voltage comparison high energy of metal-oxide-semiconductor M6 can turn-off metal-oxide-semiconductor M12 and make bias current IBIAS2 can not be mirrored to metal-oxide-semiconductor M7, only differential pair tube metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 work thereby differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 do not work; In the time that input common mode electrical level is lower, metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 can not conductings, at this moment the drain voltage of metal-oxide-semiconductor M6 very low energy make metal-oxide-semiconductor M2 open bias current IBIAS2 can not be mirrored to metal-oxide-semiconductor M7, thereby the input differential signal of differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 can make differential pair tube metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 normally to work after voltage movement circuit.
Described metal-oxide-semiconductor M0, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M4, metal-oxide-semiconductor M5 is P type metal-oxide-semiconductor.
Described voltage movement circuit is by the differential data signals D0+ of input and D0-process voltage movement output difference sub-signal D1+ and D1-.Voltage movement level in the present embodiment, can adopt source follower as shown in Figure 3.Described voltage movement level comprises metal-oxide-semiconductor M30, metal-oxide-semiconductor M31, metal-oxide-semiconductor M32, metal-oxide-semiconductor M33; The source ground of described metal-oxide-semiconductor M30, grid is connected with input data D0+; The source electrode of described metal-oxide-semiconductor M32 connects power supply, and grid is connected for source follower provides bias current with bias voltage VBIAS, and the drain electrode of metal-oxide-semiconductor M32 is connected with the drain electrode of metal-oxide-semiconductor M30 and is output port D1+; The source ground of described metal-oxide-semiconductor M31, grid is connected with input data D0-; The source electrode of described metal-oxide-semiconductor M33 connects power supply, and grid is connected for source follower provides bias current with bias voltage VBIAS, and the drain electrode of metal-oxide-semiconductor M33 is connected with the drain electrode of metal-oxide-semiconductor M31 and is output port D1-.
The wide common-mode input range USB differential receiver altogether of the present invention's design, almost can in full voltage range, work, and circuit structure is simple.The above embodiment is considered to the various application of the amplifier that can be used for the wide common-mode input range of requirement.By herein specification of the present invention and the embodiment in institute's year, those skilled in the art can understand other aspects and embodiment easily.
For those skilled in the art, under the premise without departing from the principles of the invention, can also make various concrete distortion and combination, these distortion and combination also should be considered as protection scope of the present invention.
Claims (7)
1. the USB differential receiver circuit of a new molded breadth common-mode input range, it is characterized in that: the USB differential receiver circuit of described a kind of wide common-mode input range comprises a pair of differential data signals D0+, D0-, two-way bias current IBIAS1, IBIAS2 and IBIAS1 current mirror circuit, IBIAS2 current mirror circuit, described circuit also comprises that two pairs of difference input the amplifier to pipe, and the USB differential receiver circuit of described a kind of wide common-mode input range also comprises voltage movement circuit.
2. according to claim 1, the current mirror circuit of described bias current IBIAS1 comprises metal-oxide-semiconductor M8, the drain electrode of described metal-oxide-semiconductor M8 connects biasing circuit IBIAS1, the drain electrode of described metal-oxide-semiconductor M8 is connected with grid, the source ground of described metal-oxide-semiconductor M8, the grid that the grid of described metal-oxide-semiconductor M8 is connected to metal-oxide-semiconductor M6 provides tail current for amplifier, and described metal-oxide-semiconductor M6, M8 is N-type MOS.
3. according to claim 1, the current mirror circuit of described bias current IBIAS2 comprises metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, described metal-oxide-semiconductor M13 drain electrode is with grid short circuit and be connected to bias current IBIAS2, described metal-oxide-semiconductor M13 source ground, the grid of described metal-oxide-semiconductor M12 is connected with the grid of metal-oxide-semiconductor M13, the source of described metal-oxide-semiconductor M12 is connected with the drain electrode of metal-oxide-semiconductor M6, the drain electrode of described metal-oxide-semiconductor M10 is connected with grid short circuit and with the drain electrode of metal-oxide-semiconductor M12, the source electrode of described metal-oxide-semiconductor M10 is connected with power supply, the grid of described metal-oxide-semiconductor M11 is connected with the grid of metal-oxide-semiconductor M10, the source electrode of described metal-oxide-semiconductor M11 and power supply phase, the grid of described metal-oxide-semiconductor M9 and drain electrode short circuit and being connected with the drain electrode of metal-oxide-semiconductor M11, the source ground of described metal-oxide-semiconductor M9, the grid of described metal-oxide-semiconductor M9 is connected to metal-oxide-semiconductor M7 and provides another road tail current for amplifier.
4. according to claim 3, described metal-oxide-semiconductor M9, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 is P type metal-oxide-semiconductor.
5. according to claim 1, described two pairs of difference input comprises metal-oxide-semiconductor M0 to the amplifier of pipe, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7, described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 are that a pair of difference input is to pipe, the grid of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 is connected respectively to the differential data signals D0+ of input, D0-, the source shorted of described metal-oxide-semiconductor M0 and metal-oxide-semiconductor M1 and be connected to the drain-gate of metal-oxide-semiconductor M6, the source ground of described metal-oxide-semiconductor M6, the grid of described metal-oxide-semiconductor M6 is connected with metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 is connected respectively to differential data signals D1+, D1-, the source shorted of described metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3 and be connected to the drain-gate of metal-oxide-semiconductor M7, the source ground of described metal-oxide-semiconductor M7, the grid of described metal-oxide-semiconductor M7 is connected with the grid of metal-oxide-semiconductor M9, the drain electrode of described metal-oxide-semiconductor M4 is connected with the drain electrode of metal-oxide-semiconductor M0 drain electrode and metal-oxide-semiconductor M2, and the grid of described metal-oxide-semiconductor M4 and drain electrode short circuit, the drain electrode of described metal-oxide-semiconductor M5 is connected with the drain electrode of metal-oxide-semiconductor M1 and the drain electrode of metal-oxide-semiconductor M3, the source electrode of the source electrode of described metal-oxide-semiconductor M4 and metal-oxide-semiconductor M5 is connected with power supply.
6. according to claim 5, described metal-oxide-semiconductor M0, metal-oxide-semiconductor M1, metal-oxide-semiconductor M2, metal-oxide-semiconductor M3, metal-oxide-semiconductor M6, metal-oxide-semiconductor M7 are N-type metal-oxide-semiconductor, and described metal-oxide-semiconductor M4, metal-oxide-semiconductor M5 is P type metal-oxide-semiconductor.
7. according to claim 1, described voltage movement circuit is by the differential data signals D0+ of input and D0-process voltage movement output difference sub-signal D1+ and D1-.
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| US20050266810A1 (en) * | 2004-06-01 | 2005-12-01 | Ati Technologies, Inc. | Differential signal comparator |
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Application publication date: 20141210 |