CN104201147A - Formation method for double-shallow trench isolator - Google Patents
Formation method for double-shallow trench isolator Download PDFInfo
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- CN104201147A CN104201147A CN201410459326.0A CN201410459326A CN104201147A CN 104201147 A CN104201147 A CN 104201147A CN 201410459326 A CN201410459326 A CN 201410459326A CN 104201147 A CN104201147 A CN 104201147A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
A formation method for double-shallow trench isolator includes that an oxide layer and a hard mask layer are formed on the surface of a substrate, and the substrate is provided with a first area and a second area; the hard mask layer and the oxide layer on the first area and the second area are etched till the surface of the substrate is exposed, the exposed surface of the first area forms a first part area, and the exposed surface of the second area forms a second part area; the hard mask layer is a mask, the first part area is etched to form a first shallow trench, and the second part area is etched to form a second shallow trench; the second shallow trench is protected, and the mask is taken as the hard mask layer to have the first shallow trench further etched to form a third shallow trench. By the formation method, the double-shallow trench is stable in isolation shape, high in uniformity and good in feature.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of dual shallow trench isolation.
Background technology
Cmos image sensor (CMOS image sensor, CIS) is used in the application that comprises digital camera.In semiconductor technology, CIS is projected to the light of semiconductor base for sensing.In general, these devices have utilized active pixel (active pixel) array (that is, image sensor element or unit) that comprises photodiode and other elements (for example, transistor), transfer image to numerical data or electronic signal.
CIS product comprises pixel region and logic (circuit) region conventionally.Shallow trench isolation is the feature of integrated circuit from (shallow trench isolation, STI), in order to prevent the leakage current (leakage current) between adjacent semiconductor device.
The deleterious current that dark current (dark current) produces under the situation of irradiation not for pixel.The signal of corresponding dark current can be described as dark signal (dark signal).The source of dark current comprises the impurity in silicon wafer, and it can cause damage to silicon wafer lattice because of the interior heat-dissipating (heat buildup) of manufacturing process technology and pixel region.Excessive dark current can produce leakage current and cause image degradation and not good device usefulness.For example, when Pixel Dimensions reduction (, advanced CIS), the electric leakage tolerance limit (tolerance) of dark current also must reduce.
Many methods for the pixel region in CIS and logic region all adopt single shallow trench isolation from.Also, in pixel region and logic region shallow trench isolation from the degree of depth be identical.Yet along with the Pixel Dimensions of CIS is more and more less, in order to increase the photosensitive area of pixel region and the dark current that reduces pixel, it is more shallow that the shallow trench isolation that pixel region is used is done from needs.The shallow trench isolation that pixel region is used is like this from just inconsistent from the degree of depth with the shallow trench isolation of logic region.
Therefore, need to develop a kind of formation method of new dual shallow trench isolation, with the shallow trench isolation of producing two kinds of different depths on same chip from.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of dual shallow trench isolation, with the shallow trench isolation of producing two kinds of different depths on same chip from, thereby increase the photosensitive area of pixel region and reduce the dark current of pixel.
For addressing the above problem, the invention provides a kind of formation method of dual shallow trench isolation, comprising:
At substrate surface, form oxide layer and hard mask layer, described substrate has first area and second area;
Described hard mask layer and oxide layer described in etching on first area and second area, until expose substrate surface, the surface that described first area is exposed forms first region, the surface that described second area is exposed forms second portion region;
Take described hard mask layer as mask, and first region forms the first shallow trench described in etching, and second portion region forms the second shallow trench described in etching;
Protect the second shallow trench, and take described hard mask layer as the first shallow trench formation the 3rd shallow trench described in the further etching of mask.
Optionally, in described hard mask layer surface, form the first photoresist layer, by exposure, development, etching with remove photoresist and expose described substrate surface, to form described first region and second portion region.
Optionally, the thickness of described the first photoresist layer is:
Optionally, described hard mask layer is: the combination of silicon nitride or silicon nitride and silicon oxynitride.
Optionally, the degree of depth of described the 3rd shallow trench is less than or equal to 400nm for being more than or equal to 200nm, and the degree of depth of the first shallow trench, the second shallow trench is less than or equal to 200nm for being more than or equal to 120nm.
Optionally, the step that forms the first shallow trench of first area and the second shallow trench of second area for take hard mask layer as the identical degree of depth of mask etching simultaneously.
Optionally, the step that forms described the 3rd shallow trench comprises, in described hard mask layer surface, forms the second photoresist layer, by exposure, development, etching and described the 3rd shallow trench of formation that removes photoresist; Described the second photoresist layer is protected described second area simultaneously.
Optionally, the thickness of described the second photoresist layer is: be more than or equal to
Optionally, described substrate is semiconductor crystal wafer.
Optionally, described first area is logic region, and described second area is pixel region.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, at substrate surface, form oxide layer and hard mask layer, described substrate has first area and second area; Described hard mask layer and oxide layer described in etching on first area and second area, until expose substrate surface, the surface that described first area is exposed forms first region, the surface that described second area is exposed forms second portion region; Different from existing method, the present invention be take described hard mask layer as mask, and first region forms the first shallow trench described in etching, and second portion region forms the second shallow trench described in etching; Protect the second shallow trench, and take described hard mask layer as the first shallow trench formation the 3rd shallow trench described in the further etching of mask.In the present invention, adopting described hard mask layer is that mask is for etching shallow trench, can prevent from cannot stopping that because of photoresist the shallow trench shape that corrasion causes is unstable, and the dimensional homogeneity of each shallow trench is improved, the pattern of each shallow trench is better, thereby increases the photosensitive area of pixel region and reduce the dark current of pixel.In addition, adopting described hard mask layer is mask, the defect that the byproduct of reaction producing in the time of can also eliminating photoresist as mask causes, and this defect also can not cause larger yield loss when the above technology of 0.13 μ m, but below 0.13 μ m, may cause larger yield loss.
Further, the degree of depth of the second shallow trench is for being more than or equal to 120nm and being less than or equal to 200nm.On the one hand, if the degree of depth of the second shallow trench is greater than 200nm, can cause the processing procedure difficulty of each structure in pixel region to increase, and because the depth-to-width ratio of the second shallow trench is generally 2:1 to 3:1, if the degree of depth of the second shallow trench increases, the width of the second shallow trench also increases thereupon, causes shallow trench isolation from the area that takies too many pixel region, effective area in pixel region reduces, and corresponding image sensor performance declines; And if the degree of depth of the second shallow trench is less than 120nm, the final shallow trench isolation forming, from not having corresponding insulation buffer action, causes corresponding image sensor performance to decline equally.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is each step counter structure schematic diagram of formation method of the existing dual shallow trench isolation of the first;
Fig. 5 to Fig. 9 is each step counter structure schematic diagram of formation method of the existing dual shallow trench isolation of the second;
Figure 10 to Figure 12 is each step counter structure schematic diagram of formation method of the third existing dual shallow trench isolation;
Figure 13 to Figure 17 is each step counter structure schematic diagram of formation method of the dual shallow trench isolation that provides of the embodiment of the present invention.
Embodiment
As described in background, the shallow trench isolation that pixel region is used is from just inconsistent from the degree of depth with the shallow trench isolation of logic region.
In order to make corresponding dual shallow trench isolation, a kind of existing method as shown in Figures 1 to 4.
Please refer to Fig. 1, substrate 100 is provided, substrate 100 comprises pixel region P and logic region L.In substrate 100, form silicon oxide layer 110, on silicon oxide layer 110, form silicon nitride layer 120.
Please refer to Fig. 2, on silicon nitride layer 120, form the first photoresist layer 130, the first photoresist layer 130 is exposed and the technique such as development forms the opening (mark) being positioned on logic region L, and to adopt first photoresist layer 130 with opening be mask, etching is positioned at silicon nitride layer 120, silicon oxide layer 110 and the substrate 100 on logic region L, thereby form, is positioned at the first larger shallow trench 140 of the degree of depth on logic region L.
Please refer to Fig. 3, remove the first photoresist layer 130 shown in Fig. 2 again to expose silicon nitride layer 120, and form the second photoresist layer 150 and again cover silicon nitride layer 120.The second photoresist layer 150 is filled the first shallow trench 140 forming in full Fig. 2, to protect the first shallow trench 140.The second photoresist layer 150 is exposed and the technique such as development forms the opening (mark) being positioned on pixel region P, and to adopt second photoresist layer 150 with described opening be mask, etching is positioned at silicon nitride layer 120, silicon oxide layer 110 and the substrate 100 on pixel region P, thereby form, is positioned at the second less shallow trench 160 of the degree of depth on pixel region P.
Please refer to Fig. 4, remove the second photoresist layer 150 shown in Fig. 3, thereby again expose the first shallow trench 140.Arrive this, form larger the first shallow trench 140 and the second less shallow trench 160 of the degree of depth of the degree of depth.Follow-up again by fill process, can form the dual shallow trench isolation that the degree of depth is different.
In order to make corresponding dual shallow trench isolation, existing another kind of method is as shown in Fig. 5 to 9.
Please refer to Fig. 5, substrate 200 is provided, substrate 200 comprises pixel region P and logic region L.In substrate 200, form silicon oxide layer 210, on silicon oxide layer 210, form silicon nitride layer 220.And on silicon nitride layer 220, form the first photoresist layer 230, the first photoresist layer 230 is exposed and the technique such as development forms the opening (mark) being positioned on pixel region P and logic region L, and to adopt first photoresist layer 230 with opening be mask, etching is positioned at silicon nitride layer 220 and the silicon oxide layer 210 on pixel region P and logic region L, thereby form, is positioned at the first opening 240 on logic region L and is positioned at the second opening 250 on pixel region P.
Please refer to Fig. 6, remove the first photoresist layer 230 shown in Fig. 5.
Please refer to Fig. 7; form the second photoresist layer 270 and cover silicon nitride layer 220; and the second photoresist layer 270 is exposed and the technique such as development; the part that makes the second photoresist layer 270 be positioned at the second opening 250 tops shown in Fig. 6 is removed; now the second photoresist layer 270 is filled full the first opening 240, thus protection the first opening 240.Then second photoresist layer 270 of take is mask, along the second opening 250 etching substrates 200 shown in Fig. 6, thereby forms the first less shallow trench 260 of the degree of depth that is positioned at pixel region P.
Please refer to Fig. 8; remove the second photoresist layer 270 shown in Fig. 7; and form the 3rd photoresist layer 280 and again cover silicon nitride layer 220; and the 3rd photoresist layer 280 is exposed and the technique such as development; the part that makes the 3rd photoresist layer 280 be positioned at the first opening 240 tops shown in Fig. 6 is removed; now the 3rd photoresist layer 280 is filled full the first shallow trench 260, thus protection the first shallow trench 260.Then the 3rd photoresist layer 280 of take is mask, along the first opening 240 etching substrates 200 shown in Fig. 6, thereby forms the second larger shallow trench 290 of the degree of depth that is positioned at logic region L.
Please refer to Fig. 9, remove the 3rd photoresist layer 280 shown in Fig. 8, thereby again expose the first shallow trench 260.Arrive this, form less the first shallow trench 260 and the second larger shallow trench 290 of the degree of depth of the degree of depth.Follow-up again by fill process, can form the dual shallow trench isolation that the degree of depth is different.
In order to make corresponding dual shallow trench isolation, existing another kind of method is as shown in Figure 10 to 12.
Please refer to Figure 10, substrate 300 is provided, substrate 300 comprises pixel region P and logic region L.In substrate 300, form silicon oxide layer 310, on silicon oxide layer 310, form silicon nitride layer 320.And on silicon nitride layer 320, form the first photoresist layer 330, the first photoresist layer 330 is exposed and the technique such as development forms the opening (mark) being positioned on pixel region P and logic region L, and to adopt first photoresist layer 330 with opening be mask, etching is positioned at silicon nitride layer 320 and the silicon oxide layer 310 on pixel region P and logic region L, thereby form, be positioned at the first shallow trench 340 on logic region L and be positioned at the second shallow trench 350 on pixel region P, and the first shallow trench 340 and second shallow trench 350 degree of depth all less.
Please refer to Figure 11; remove the first photoresist layer 330 shown in Figure 10; then on silicon nitride layer 320, form the second photoresist layer 360; the second photoresist layer 360 is exposed and the technique such as development; to remove the photoresist that is positioned at the first shallow trench 340 tops shown in Figure 10; now the second photoresist layer 360 is filled the second shallow trench 350 shown in full Figure 10, to protect the second shallow trench 350.Then second photoresist layer 360 of take is mask, continues etching substrate 300, thereby make the first shallow trench 340 convert the 3rd shallow trench 370 that the degree of depth is larger to along the first shallow trench 340 shown in Figure 10.
Please refer to Figure 12, remove the second photoresist layer 360 shown in Figure 11, thereby again expose the second shallow trench 350.Arrive this, form less the second shallow trench 350 and the 3rd larger shallow trench 370 of the degree of depth of the degree of depth.Follow-up again by fill process, can form the dual shallow trench isolation that the degree of depth is different.
Yet along with the development of IC manufacturing process, when critical size arrives 0.13 μ m when following, above-mentioned three kinds of methods are not all suitable for the formation of dual shallow trench isolation in imageing sensor.This be because: in order to guarantee the resolution in photoetching process, critical size is more and more less, photoetching process photoresist used just need to be thinner, therefore, when critical size arrives 0.13 μ m when following, corresponding photoresist (thickness) has been not enough to stop corrasion, if now still adopt above-mentioned three kinds of methods, all need directly to adopt photoresist to form corresponding shallow trench as mask etching, and now photoresist cannot stop corrasion, therefore, not only can cause formed shallow trench shape unstable, the size heterogeneity of each shallow trench, the pattern of each shallow trench is poor, but also can cause body structure surface (for example silicon nitride surface or the substrate surface) effect of being etched to destroy, and then cause element leakage serious.
For this reason, the invention provides a kind of formation method of new dual shallow trench isolation, described method forms oxide layer and hard mask layer at substrate surface, and described substrate has first area and second area; Described hard mask layer and oxide layer described in etching on first area and second area, until expose substrate surface, the surface that described first area is exposed forms first region, the surface that described second area is exposed forms second portion region; Different from existing method, described method be take described hard mask layer as mask, and first region forms the first shallow trench described in etching, and second portion region forms the second shallow trench described in etching; Protect the second shallow trench, and take described hard mask layer as the first shallow trench formation the 3rd shallow trench described in the further etching of mask.Owing to adopting described hard mask layer, it is mask, for etching the first shallow trench and the second shallow trench, therefore, can prevent from cannot stopping that because of photoresist the shallow trench shape that corrasion causes is unstable, and the dimensional homogeneity of each shallow trench is improved, and the pattern of each shallow trench is better.In addition, adopting described hard mask layer is mask, the defect that the byproduct of reaction producing in the time of can also eliminating photoresist as mask causes, and this defect also can not cause larger yield loss when the above technology of 0.13 μ m, but below 0.13 μ m, may cause larger yield loss.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The embodiment of the present invention provides a kind of formation method of dual shallow trench isolation, incorporated by reference to reference to figures 13 to Figure 17.
Please refer to Figure 13, on substrate 400 surfaces, form oxide layer 411 and hard mask layer 413, substrate 400 has first area A and second area B.
In the present embodiment, substrate 400 is semiconductor crystal wafer.
Semiconductor crystal wafer is for production of integrated circuits silicon wafer used.In the present embodiment, semiconductor crystal wafer is specifically for making image transducer.Described imageing sensor can, for front according to formula (front-side illuminated, FSI) transducer, can be also back-illuminated type (backside illuminated, BSI) transducer.In FSI transducer, light is sent by the front surface of silicon wafer, and in BSI transducer, light is sent by the back of the body surface of silicon wafer.
In the present embodiment, first area A is logic region, and second area B is pixel region.
Pixel region (also can be called pixel array region) generally includes the pixel (not shown) that is arranged in array.Wherein each pixel can comprise various semiconductor device (such as transistor etc.).Pixel region also can comprise various elements (element also for semiconductor device), such as photodetector (not shown) etc., and photodiode for example, photodiode can sensing leads to the light quantity of pixel and records the intensity of light or brightness etc.Pixel region can be for absorbing light and producing optical charge or photoelectron, and pixel region is collected and for example built up, in the photosensitive area of photodetector (photodiode), and can be used for reading produced photoelectron and changed into electronic signal.Transistor in pixel region generally includes dissimilar, and transistor, transmission (transfer) transistor etc. are followed in (reset) transistor of for example resetting, source.
Logic region generally includes logical circuit and input/output, in order to the operating environment of pixel to be provided and to provide pixel and the support of outside UNICOM.Circuit in logic region can comprise transistor, driving pixel, picked up signal electric charge circuit, analog/digital (A/D) transducer, form output signal processing circuit, electric connection line with miscellaneous part etc.
In the present embodiment, the material of oxide layer 411 can be silica.Oxide layer 411 can adopt thermal oxidation process or chemical oxidation method directly to form at crystal column surface.For example adopt dry method thermal oxidation process to form oxide layer 411.Oxide layer 411 has the effect of resilient coating, and oxide layer 411 can be used for reducing the stress of 413 pairs of wafers of hard mask layer of follow-up formation.
In the present embodiment, hard mask layer 413 is the combination of silicon nitride or silicon nitride and silicon oxynitride.Hard mask layer 413 can adopt low-pressure chemical vapour deposition technique (LPCVD) to form.
Please continue to refer to Figure 13, in hard mask layer 413 surfaces, form the first photoresist layer 415.And the present embodiment also comprises by exposing and the technique such as development, to form openings (mark) at the first photoresist layer 415.
In the present embodiment, the process that formation has the first photoresist layer 415 of described opening can be: wafer (being substrate 400) is cleaned, dewatered becomes counterdie processing with surface, can adopt afterwards spin coating method to form photoresist layer on hard mask layer 413, spin coating method adopts vacuum attraction method that wafer is inhaled on the sucker of photoresist spinner, the photoresist with certain viscosity is dropped in to the surface of substrate, the rotating speed resetting and time whirl coating; Due to the effect of centrifugal force, photoresist launches equably at crystal column surface, and unnecessary photoresist is got rid of, and obtains certain thickness photoresist layer; The thickness of photoresist layer is to be controlled by the viscosity of photoresist and the rotating speed of whirl coating; After spin coating, photoresist layer is carried out to soft baking; After soft baking, photoresist layer exposed and developed, thereby forming described opening; After developing, carry out post bake and cure, finally can also check operation.For adopting deep-UV lithography glue-line, in exposure with between developing, can also increase and cure together operation.By above-mentioned operation, form first photoresist layer 415 with described opening.
Please continue to refer to Figure 13, hard mask layer 413 on etching first area A and second area B and oxide layer 411, until expose substrate surface 400, the surface that first area A is exposed forms first region 417, and the surface that second area B is exposed forms second portion region 419.
In the present embodiment, can be along above-mentioned opening etching hard mask layer 413 and the oxide layer 411 of the first photoresist layer 415, thus form first region 417 and second portion region 419.
In the present embodiment, the material of hard mask layer 413 is the combination of silicon nitride or silicon nitride and silicon oxynitride, the material of oxide layer 411 is silica, so the gas that adopts of etching hard mask layer 413 and oxide layer 411 can be one or more in CF4, CHF3, SiF4 and NF3.
In the present embodiment, the thickness of the first photoresist layer 415 is:
the first photoresist layer 415 is used to form first region 417 and the second portion region 419 being positioned on the A of first area, and first region 417 and second portion region 419 follow-up for the higher shallow trench isolation of precision from, therefore, the thickness of the first photoresist layer 415 needs thinner, and thickness exists
below, thus guarantee enough photoetching resolutions.Simultaneously the thickness of the first photoresist layer 415 need to guarantee the formation in first region 417, and its thickness need to be
above.In addition, the thickness of the first photoresist layer 415 is also relevant with the minimum dimension of pixel region, and the minimum dimension of pixel region is less, requires the thickness of the first photoresist layer 415 less.For example, when the minimum dimension of pixel region is 80nm, the thickness of the first photoresist layer 415 need to be controlled at
thereby guarantee that photoetching resolution reaches necessary requirement.
Please refer to Figure 14, remove the first photoresist layer 415 shown in Figure 13.
In the present embodiment, can adopt wet type to divest or plasma ashing (ashing) removes photoresist.The present embodiment specifically can adopt the plasma etch process of oxygen to remove the first photoresist layer 415.
Please refer to Figure 15, take hard mask layer 413 as mask, etching first region 417 forms the first shallow trench 421, and etching second portion region 419 forms the second shallow trench 423.
In the present embodiment, the first shallow trench 421 that forms first region 417 with the step that forms second shallow trench 423 in second portion region 419 is: take hard mask layer 413 as mask, to first region 417 and the same degree of depth of second portion region 419 etching phases simultaneously.
In the present embodiment, first region 417 and second portion region 419 consist of monocrystalline silicon, so the gas that etching first region 417 and second portion region 419 adopt can be F2, bromine-based gas (such as Br2) or chlorine-based gas (such as Cl2) etc.
In fact, if directly adopting photoresist layer is that mask forms shallow trench, not only cause unstable and each shallow trench size heterogeneity problem of shallow trench shape, and photoresist can produce the accessory substance of fine granularity in etching process, these accessory substances can drop on formed shallow trench surface, cause shallow trench surface to have post.Along with shallow trench isolation is from the reducing of size, the adverse effect effect of these posts is amplified, and causes shallow trench isolation from hydraulic performance decline.And after the present embodiment is chosen in and removes the first photoresist layer 415, then adopt hard mask layer 413 for mask, etching forms the first shallow trench 421 and the second shallow trench 423, has the following advantages:
1. prevent from cannot playing because of photoresist layer shallow trench shape instability problem and each shallow trench size heterogeneity problem that etching protective effect causes, form dimensionally stable, pattern is good and the less shallow trench more accurately of size, thereby guarantee that the final dual shallow trench isolation forming is functional, and then guarantee to adopt in the imageing sensor of this dual shallow trench isolation, the photosensitive area of pixel region increases, and the dark current of pixel reduces;
2. avoid the existence because of photoresist in etching process to produce accessory substance, eliminate the impurity particle on shallow trench surface, prevent from being polluted in shallow trench forming process, improve shallow trench isolation from performance;
3. prevent that crystal column surface is damaged, thereby prevent that device from leaking electricity;
4. improve the yield of the semiconductor product that adopts the method formation.
Please refer to Figure 16, form the second photoresist layer 425 and fill the second shallow trench 423 shown in full Figure 15, thus protection the second shallow trench 423, and take hard mask layer 413 as further etching the first shallow trench 421 formation the 3rd shallow trenchs 427 of mask.
In the present embodiment, the second photoresist layer 425 exposes the first shallow trench 421, therefore the forming process of the second photoresist layer 425 can be: after the photoresist layer that adopts spin coating method to form, photoresist layer is exposed and the technique such as development, thereby remove the photoresist layer that is positioned at the first shallow trench 421 tops, form the second photoresist layer 425 as shown in figure 16.
In the present embodiment, the gas that further etching the first shallow trench 421 formation the 3rd shallow trenchs 427 adopt can be F2, bromine-based gas (such as Br2) or chlorine-based gas (such as Cl2) etc. equally.
In the present embodiment, the thickness of the second photoresist layer 425 is: be more than or equal to
the second photoresist layer 425, for form second portion region 419 on second area, in order to guarantee to form behind second portion region 419, still has part photoresist protection first area A, and the thickness that the second photoresist layer 425 is set is especially more than or equal to
thereby make first area A (being pixel region) obtain good protection.
Please refer to Figure 17, remove the second photoresist layer 425 shown in Figure 16, again to expose the second shallow trench 423.
In the present embodiment, the second photoresist layer 425 can adopt equally wet type to divest or plasma ashing removes.
Arrive this, the present embodiment has formed larger the 3rd shallow trench 427 and the second less shallow trench 423 of the degree of depth of the degree of depth.
In the present embodiment, the degree of depth of the 3rd shallow trench 427 is for being more than or equal to 200nm and being less than or equal to 400nm.The 3rd shallow trench 427 is positioned at logic region (being first area A), and its degree of depth need to guarantee the buffer action of the semiconductor device that operating voltage is larger conventionally, and therefore, its degree of depth need to guarantee more than 200nm; Meanwhile, if the 3rd shallow trench 427 is too dark, not only cause technology difficulty to increase, but also cause the degree of depth of the second shallow trench 423 also to increase thereupon, therefore, the present embodiment is controlled its degree of depth below 400nm.
In the present embodiment, the degree of depth of the second shallow trench 423 is for being more than or equal to 120nm and being less than or equal to 200nm.On the one hand, if the degree of depth of the second shallow trench 423 is greater than 200nm, can cause the processing procedure difficulty of each structure in pixel region (being second area B) to increase, and because the depth-to-width ratio of the second shallow trench 423 is generally 2:1 to 3:1, if the degree of depth of the second shallow trench 423 increases, the width of the second shallow trench 423 also increases thereupon, causes shallow trench isolation from the area that takies too many pixel region, effective area in pixel region reduces, and corresponding image sensor performance declines; And if the degree of depth of the second shallow trench 423 is less than 120nm, the final shallow trench isolation forming, from not having corresponding insulation buffer action, causes corresponding image sensor performance to decline equally.
Though in figure, do not show, after forming the 3rd shallow trench 427 and the second shallow trench 423, can be in the 3rd shallow trench 427 and the second shallow trench 423 deposition of dielectric materials, thereby form complete dual shallow trench isolation.Described dielectric material can be silica.Concrete, can be by adopting high density plasma CVD (high density plasma CVD, HDP-CVD) to come cvd silicon oxide material to fill the 3rd shallow trench 427 and the second shallow trench 423.And, after fill process, can also adopt flatening process to repair or remove unwanted rete.For example can utilize cmp (chemical mechanical polishing, CMP) to grind each shallow trench insulation surfaces, make each shallow trench isolation from flush.
In the formation method of the dual shallow trench isolation that the present embodiment provides, when forming the first shallow trench 421 and during the second shallow trench 423, after being chosen in removal photoresist layer, again substrate 400 is carried out to etching, thereby prevent that unsettled phenomenon from appearring in formed shallow trench shape, and prevent that the not good and inhomogenous problem of size of pattern from appearring in formed each shallow trench, and formed shallow trench dimensionally stable, each shallow trench pattern is good and size is less more accurate.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for dual shallow trench isolation, is characterized in that, comprising:
At substrate surface, form oxide layer and hard mask layer, described substrate has first area and second area;
Described hard mask layer and oxide layer described in etching on first area and second area, until expose substrate surface, the surface that described first area is exposed forms first region, the surface that described second area is exposed forms second portion region;
Take described hard mask layer as mask, and first region forms the first shallow trench described in etching, and second portion region forms the second shallow trench described in etching;
Protect the second shallow trench, and take described hard mask layer as the first shallow trench formation the 3rd shallow trench described in the further etching of mask.
2. the formation method of dual shallow trench isolation according to claim 1, it is characterized in that, in described hard mask layer surface, form the first photoresist layer, by exposure, development, etching with remove photoresist and expose described substrate surface, to form described first region and second portion region.
3. the formation method of dual shallow trench isolation according to claim 2, is characterized in that, the thickness of described the first photoresist layer is:
4. the formation method of dual shallow trench isolation according to claim 1, is characterized in that, described hard mask layer is: the combination of silicon nitride or silicon nitride and silicon oxynitride.
5. the formation method of dual shallow trench isolation according to claim 1, it is characterized in that, the degree of depth of described the 3rd shallow trench is less than or equal to 400nm for being more than or equal to 200nm, and the degree of depth of the first shallow trench, the second shallow trench is less than or equal to 200nm for being more than or equal to 120nm.
6. the formation method of dual shallow trench isolation according to claim 1, is characterized in that, forms the step of the first shallow trench of first area and the second shallow trench of second area for take hard mask layer as the identical degree of depth of mask etching simultaneously.
7. the formation method of dual shallow trench isolation according to claim 1, it is characterized in that, the step that forms described the 3rd shallow trench comprises, in described hard mask layer surface, forms the second photoresist layer, by exposure, development, etching and described the 3rd shallow trench of formation that removes photoresist; Described the second photoresist layer is protected described second area simultaneously.
8. the formation method of dual shallow trench isolation according to claim 7, is characterized in that, the thickness of described the second photoresist layer is: be more than or equal to
9. the formation method of dual shallow trench isolation according to claim 1, is characterized in that, described substrate is semiconductor crystal wafer.
10. the formation method of dual shallow trench isolation according to claim 1, is characterized in that, described first area is logic region, and described second area is pixel region.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304663A (en) * | 2015-10-27 | 2016-02-03 | 上海华力微电子有限公司 | Method for reducing metal pollution of working area of contact image sensor |
| CN105374840A (en) * | 2015-10-27 | 2016-03-02 | 上海华力微电子有限公司 | Method to reduce metal pollution in work area of contact-type image sensor |
| CN110148580A (en) * | 2019-05-15 | 2019-08-20 | 上海集成电路研发中心有限公司 | A kind of dual depth shallow trench isolation groove and preparation method thereof |
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2014
- 2014-09-10 CN CN201410459326.0A patent/CN104201147A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304663A (en) * | 2015-10-27 | 2016-02-03 | 上海华力微电子有限公司 | Method for reducing metal pollution of working area of contact image sensor |
| CN105374840A (en) * | 2015-10-27 | 2016-03-02 | 上海华力微电子有限公司 | Method to reduce metal pollution in work area of contact-type image sensor |
| CN105304663B (en) * | 2015-10-27 | 2018-08-24 | 上海华力微电子有限公司 | A method of reducing contact-type image sensor workspace metallic pollution |
| CN105374840B (en) * | 2015-10-27 | 2019-01-04 | 上海华力微电子有限公司 | A method of reducing contact-type image sensor workspace metallic pollution |
| CN110148580A (en) * | 2019-05-15 | 2019-08-20 | 上海集成电路研发中心有限公司 | A kind of dual depth shallow trench isolation groove and preparation method thereof |
| CN110148580B (en) * | 2019-05-15 | 2021-07-02 | 上海集成电路研发中心有限公司 | Double-depth shallow trench isolation groove and preparation method thereof |
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Application publication date: 20141210 |