CN104201114A - Packaging method and packaging structure of chip with sidewall in insulating protection - Google Patents
Packaging method and packaging structure of chip with sidewall in insulating protection Download PDFInfo
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- CN104201114A CN104201114A CN201410426690.7A CN201410426690A CN104201114A CN 104201114 A CN104201114 A CN 104201114A CN 201410426690 A CN201410426690 A CN 201410426690A CN 104201114 A CN104201114 A CN 104201114A
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 23
- 239000011241 protective layer Substances 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 86
- 230000004888 barrier function Effects 0.000 claims description 67
- 239000000377 silicon dioxide Substances 0.000 claims description 42
- 238000009413 insulation Methods 0.000 claims description 38
- 230000008878 coupling Effects 0.000 claims description 32
- 238000010168 coupling process Methods 0.000 claims description 32
- 238000005859 coupling reaction Methods 0.000 claims description 32
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000007888 film coating Substances 0.000 claims description 6
- 238000009501 film coating Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 29
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000003698 laser cutting Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010992 reflux Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241000931526 Acer campestre Species 0.000 description 1
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010020843 Hyperthermia Diseases 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000036031 hyperthermia Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Laser Beam Processing (AREA)
Abstract
The invention discloses a packaging method and a packaging structure of a chip with a sidewall in insulating protection, and belongs to the technical field of semiconductor packaging. A chip electrode (102) is embedded into an upper surface of a silicon-based body (101); a metal convex block (300) is located on the upper surface of the silicon-based body (101) and is connected with the chip electrode (102); an insulating layer I (202) is arranged on the sidewall of the silicon-based body (101) and is formed in the process of cutting a wafer (100) through laser and O2 or N2; an insulating layer II (210) is arranged on a portion of the upper surface of the silicon-based body (101), except for the metal convex block (300); a backside protective layer (400) is arranged on the lower surface of the silicon-based body (101). According to the invention, as the insulating layer I (202) is formed on the sidewall of the silicon-based body (101) through the laser, the wicking effect of the sidewall is effectively eliminated, electric leakage of chip scale package is avoided, the yield of chips is increased, the packaging method is easy and environment-friendly, and manufacturing cost is reduced.
Description
Technical field
The chip packaging method and the encapsulating structure thereof that the present invention relates to a kind of lateral wall insulation protection, belong to semiconductor packaging field.
Background technology
Existing wafer level CSP (Chip Scale Package) encapsulating structure, the silicon of its chip surrounding is exposed in assembling environment, mounting in reflux technique, solder ball or electrode zone easily, because solder(ing) paste number to be printed too much causes part scolding tin to climb above the exposed silicon of chip sidewall, cause chip electric leakage; Or because inter-chip pitch is closer, heating or reflux after, the sidewall contact that causes chip to other chips metal coupling and cause losing efficacy.
Simultaneously, for very small dimensions encapsulating products, as the encapsulating products of 0402,0210,01005 equidimension, as shown in figure as left in Fig. 1, himself very light in weight, if the solder(ing) paste number to be printed of two electrodes is variant in surface mount process, and backflow heating temperature inequality, electrode two ends imbalance caused, very easily cause the perk of chip one end, form " gravestone " phenomenon, as shown in figure as right in Fig. 1, cause chip attachment bad.
Summary of the invention
The object of the invention is to overcome the deficiency of above-mentioned encapsulating structure, provide a kind of chip attachment of improving bad and be difficult for causing chip packaging method and the encapsulating structure thereof of the lateral wall insulation protection of chip electric leakage.
the object of the present invention is achieved like this:
The chip packaging method of a kind of lateral wall insulation protection of the present invention, its technical process is as follows:
Step 1, provide the disk with chip electrode and scribing road;
Step 2, laser knife and disk are placed in enclosure space, start laser knife, advanced in its scribing road along disk, cut disk, form groove, O is provided simultaneously
2or N
2, in the insulating barrier I of the trench wall formation oxide of silicon or the nitride of silicon;
Step 3, adopt the method deposition SiO of PECVD in disk surfaces
2/ SiN, forms insulating barrier II, and forms insulating barrier II opening, the surface of insulating barrier II opening exposed chip electrode by the method for corrosion or etching above chip electrode;
Step 4, by chemical plating or electroplating technology, on the surface of chip electrode, form metal coupling;
Step 5, on disk overlay film, and spin upside down 180 °;
Step 6, by abrasive disc technique, attenuate is carried out in the back side of disk;
Step 7, by film coating process, paste back-protective layer at disk back;
Step 8, by sliver and striping, make single change of disk, form the chip-packaging structure of the lateral wall insulation protection of single.
Alternatively, described gash depth h is >=30 μ m.
Alternatively, the degree of depth h of described groove is 100～250 μ m.
The chip-packaging structure of the described lateral wall insulation protection that the chip packaging method of above-mentioned lateral wall insulation protection forms; it comprises silica-based body, chip electrode, insulating barrier I, insulating barrier II, metal coupling and back-protective layer; wherein; chip electrode embeds the upper surface of silica-based body; metal coupling is positioned at the upper surface of silica-based body and is connected with chip electrode; described insulating barrier I is arranged at the sidewall of silica-based body; described insulating barrier II is arranged at the part beyond the metal coupling on silica-based body, and back-protective layer is arranged at the lower surface of silica-based body.
Alternatively, the thickness of described insulating barrier I is 0.5～5 μ m.
The chip packaging method of another kind of lateral wall insulation protection of the present invention, its technical process is as follows:
Step 1, provide the disk with chip electrode and scribing road;
Step 2, adopt the method deposition SiO of PECVD in disk surfaces
2/ SiN or coating polyimide, form insulating barrier II, and form insulating barrier II opening, the surface of insulating barrier II opening exposed chip electrode by the method for corrosion or etching above chip electrode;
Step 3, by chemical plating or electroplating technology, on the surface of chip electrode, form metal coupling;
Step 4, on disk overlay film, and spin upside down 180 °;
Step 5, by abrasive disc technique, attenuate is carried out in the back side of disk;
Step 6, by film coating process, paste back-protective layer at disk back,
Step 7, laser knife and disk to be cut are placed in enclosure space, start laser knife, advanced in its scribing road along disk, cut disk, O is provided simultaneously
2or N
2, in the insulating barrier I of the trench wall formation oxide of silicon or the nitride of silicon;
Step 8, by sliver and striping, make single change of disk, form the chip-packaging structure of the lateral wall insulation protection of single.
Alternatively, described disk residual thickness h2 is >=30 μ m.
Alternatively, described disk residue degree of depth h2 is 100～250 μ m.
The chip-packaging structure of the described lateral wall insulation protection that the chip packaging method of above-mentioned lateral wall insulation protection forms; it comprises silica-based body, chip electrode, insulating barrier I, insulating barrier II, metal coupling and back-protective layer; wherein; chip electrode embeds the upper surface of silica-based body; metal coupling is positioned at the upper surface of silica-based body and is connected with chip electrode; described insulating barrier I is arranged at the sidewall of silica-based body; described insulating barrier II is arranged at the part beyond the metal coupling of silica-based body upper surface, and back-protective layer is arranged at the lower surface of silica-based body.
Alternatively, the thickness of described insulating barrier I is 0.5～5 μ m.
The invention has the beneficial effects as follows:
1, the chip-packaging structure of lateral wall insulation protection of the present invention, its sidewall at silica-based body arranges the insulating barrier I of the oxide of silicon and/or the nitride of silicon, that has eliminated silica-based body sidewall climbs tin phenomenon, has overcome the electric leakage problem of chip size packages, has promoted the yield that mounts of chip;
2, the insulating barrier I of the oxide of silicon of the present invention or the nitride of silicon forms in laser cutting disk process, and processing procedure is succinct, environmental protection, has reduced production cost.
brief description of the drawings
Fig. 1 is the schematic diagram of climbing tin phenomenon of existing chip-packaging structure;
Fig. 2 is the process chart of the chip packaging method of a kind of lateral wall insulation protection of the present invention;
Fig. 3 is the generalized section of the embodiment mono-of the chip-packaging structure of a kind of lateral wall insulation protection of the present invention;
The technical process schematic diagram of the method for packing of Fig. 4 to Figure 12 embodiment mono-;
Figure 13 is the generalized section of the distortion of the embodiment mono-of the chip-packaging structure of a kind of lateral wall insulation protection of the present invention;
Figure 14 is another process chart of the chip packaging method of a kind of lateral wall insulation protection of the present invention;
Figure 15 is the generalized section of the chip-packaging structure embodiment bis-of a kind of lateral wall insulation protection of the present invention;
Figure 16 to Figure 21 is the technical process schematic diagram of the method for packing of embodiment bis-;
Wherein, silica-based body 101
Chip electrode 102
Insulating barrier I 202
Insulating barrier II 210
Insulating barrier II opening 211
Metal coupling 300
Back-protective layer 400;
Disk 100
Chip 11
Scribing road 12
Groove 103
Film 500
Laser knife 600.
Embodiment
Now will with reference to accompanying drawing, the present invention be described more fully hereinafter, exemplary embodiment of the present invention shown in the drawings, thus scope of the present invention is conveyed to fully those skilled in the art by the disclosure.But the present invention can realize in many different forms, and should not be interpreted as being limited to the embodiment setting forth here.
Scheme one
Referring to Fig. 2, the chip packaging method of a kind of lateral wall insulation protection of the present invention, its technological process is as follows:
Execution step S101: the disk with chip electrode array is provided;
Execution step S102: groove is offered with laser in the scribing road along disk forms insulating barrier I in trench wall simultaneously;
Execution step S103: the surface at disk forms insulating barrier II and the metal coupling being connected with chip electrode;
Execution step S104: the back side of attenuate disk, and overlay film;
Execution step S105: sliver, forms the chip-packaging structure of the lateral wall insulation protection of single.
Adopt above-mentioned process, form the embodiment mono-of the chip-packaging structure of the lateral wall insulation protection of single of the present invention, as follows:
The chip-packaging structure of a kind of lateral wall insulation protection as shown in Figure 3, it comprises silica-based body 101, chip electrode 102, insulating barrier I 202, insulating barrier II 210, metal coupling 300 and back-protective layer 400.Wherein, chip electrode 102 embeds the upper surface of silica-based body 101, metal coupling 300 is positioned at the upper surface of silica-based body 101 and is connected with chip electrode 102, and conventionally metal coupling 300 is for having the multiple layer metal post such as copper post, pure tin post, sn-ag alloy post or Ni/Pd, Ni/Au, Ni/Pd/Au of superior electric conductivity, heat conductivility and reliability.It is block that metal coupling 300 is, and also can be column.Can also there is the metal antioxidation coating of scolding tin material on the top of metal coupling 300.Insulating barrier I 202 is arranged at the sidewall of silica-based body 101, material is the oxide of silicon or the nitride of silicon, general thickness is 0.5～5 μ m, it has avoided the exposed of silica-based body 101 sidewalls, can effectively eliminate and climb tin phenomenon, reduce the damage of chip in the time installing and use, improved the yield that mounts of chip.Insulating barrier II 210 is arranged at the part beyond the metal coupling 300 on silica-based body 101.Back-protective layer 400 is arranged at the lower surface of silica-based body 101, and its thickness is 5 ~ 40um.When use, metal coupling 300 upside-down mountings of the present invention, to substrate, are connected by reflux technique and substrate; Or by routing technique, chip is fixed on lead frame.
The technical process of above-described embodiment one is as follows:
Step 1, provide the disk 100 with chip electrode array, as shown in Figure 4 and Figure 5, it can form thousands of chips 11, and it is the scribing road 12 of 40 μ m～100 μ m that 11 of adjacent chips have spacing conventionally, and disk 100 forms silica-based body 101 after cutting into monomer.The front view that wherein Fig. 4 is disk, Fig. 5 is the cutaway view through wherein amplify the part of the disk of a row chip electrode.
Step 2, laser knife 600 and disk 100 to be cut are placed in enclosure space, as shown in Figure 6, start laser knife 600, advanced in its scribing road 12 along disk 100, cut disk 100, form the very high groove 103 of fineness, groove 103 degree of depth h are >=30 μ m, taking degree of depth h as 100～250 μ m are as good.Because laser knife 600 is not cut disk 100, for follow-up technique provides support power.
In the time of laser cutting disk 100, the laser equipment adopting can be the infrared laser of optical maser wavelength 1064nm, the laser beam that laser sends is through lens focus, be polymerized to a minimum hot spot at focus place, its spot size can be as small as 30～80 μ m, and the laser power density focusing at hot spot place is up to 10
9～10
12w/mm
2.The laser facula that is subject to high power density in the silicon matter at its focus place irradiates, and can produce 10000 ° of localized hyperthermias more than C, makes it instant vaporization, and is blown away by air-flow, forms groove 103, simultaneously the silicon matter at edge, focus place and its O around
2or N
2react, form the insulating barrier I 202 of the nitride that is attached to oxide groove 103 walls, that composition is silicon or silicon, the thickness of this insulating barrier I 202 is 0.5～5 μ m, has insulation protection effect.
Step 3, adopt the method deposition SiO of PECVD on disk 100 surface
2/ SiN, forms insulating barrier II 210, and forms insulating barrier II opening 211 by the method for corrosion or etching above chip electrode 102, the surface of insulating barrier II opening 211 exposed chip electrodes 102, as shown in Figure 7.
Step 4, by chemical plating or electroplating technology, on the surface of chip electrode 102, form metal coupling 300, as shown in Figure 8.
Step 5, on disk 100 overlay film 500, this overlay film 500 is generally UV film, and spins upside down 180 °, as shown in Figure 9.
Step 6, by abrasive disc technique, attenuate is carried out in the back side of disk 100, thickness thinning is determined according to actual needs.The bottom residual thickness h1 that can be thinned to groove 103, also can be thinned to the bottom of exposing groove 103, can also be thinned to insulating barrier I 202 and insulating barrier II 210 thickness in residual thickness and the groove 103 that removes groove 103, as shown in figure 10.
Step 7, by film coating process, paste back-protective layers 400 at disk 100 backs, to strengthen the intensity of encapsulating structure, as shown in figure 11.
Step 8, by sliver and striping 500, make 100 single changes of disk, form the chip-packaging structure of the lateral wall insulation protection of single, as shown in figure 12.
Due to the thickness difference of the thinning back side of disk 100; can form chip-packaging structure sizes thickness, the slightly differentiated lateral wall insulation protection of encapsulating structure; as shown in figure 13, the thickness of silica-based body 101 is thinner, and insulating barrier II 210 also can extend to the outside of insulating barrier I 202.
Scheme two
Referring to Figure 14, the chip packaging method of a kind of lateral wall insulation protection of the present invention, its technological process is as follows:
Execution step S101: the disk with chip electrode array is provided;
Execution step S102: the surface at disk forms insulating barrier II and the metal coupling being connected with chip electrode;
Execution step S103: the back side of attenuate disk, and overlay film;
Execution step S104: groove is offered with laser in the scribing road along disk forms insulating barrier I in trench wall simultaneously;
Execution step S105: sliver, forms the chip-packaging structure of the lateral wall insulation protection of single.
Adopt above-mentioned process, form the embodiment bis-of the chip-packaging structure of the lateral wall insulation protection of single of the present invention, as follows:
The chip-packaging structure of a kind of lateral wall insulation protection as shown in figure 15; it comprises silica-based body 101, chip electrode 102, insulating barrier I 202, insulating barrier II 210, metal coupling 300 and back-protective layer 400; wherein; chip electrode 102 embeds the upper surface of silica-based body 101, and metal coupling 300 is positioned at the upper surface of silica-based body 101 and is connected with chip electrode 102.Insulating barrier I 202 is arranged at the sidewall of silica-based body 101, the oxide that material is silicon or the nitride of silicon, and general thickness is 0.5～5 μ m, it can effectively be eliminated and climb tin phenomenon, has improved the yield that mounts of chip.Insulating barrier II 210 is arranged at the part beyond the metal coupling 300 of silica-based body 101 upper surfaces, and back-protective layer 400 is arranged at the lower surface of silica-based body 101.
The technical process of above-described embodiment two is as follows:
Step 1, provide the disk 100 with chip electrode array, as shown in figure 16.
Step 2, adopt the method deposition SiO of PECVD on disk 100 surface
2/ SiN or coating polyimide, form insulating barrier II 210, and form insulating barrier II opening 211 by the method for corrosion or etching above chip electrode 102, the surface of insulating barrier II opening 211 exposed chip electrodes 102, as shown in figure 17.
Step 3, by chemical plating or electroplating technology, on the surface of chip electrode 102, form metal coupling 300, as shown in figure 18.
Step 4, on disk 100 overlay film 500, this overlay film 500 is generally UV film, and spins upside down 180 °, as shown in figure 19.
Step 5, by abrasive disc technique, attenuate is carried out in the back side of disk 100, making disk 100 residual thickness h2 is >=30 μ m, taking degree of depth h2 as 100～250 μ m are as good, as shown in figure 19.
Step 6, by film coating process, paste back-protective layers 400 at disk 100 backs, as shown in figure 20.
Step 7, laser knife 600 and disk 100 to be cut are placed in enclosure space, start laser knife 600, advanced in its scribing road 12 along disk 100, cut disk 100, as shown in figure 20, provide O simultaneously
2or N
2, the insulating barrier I 202 of the oxide that forming thickness in groove 103 walls is 0.5～5 μ m, material is silicon or the nitride of silicon, plays insulation protection effect.
Step 8, by sliver and striping 500, make 100 single changes of disk, as shown in figure 21.
Chip packaging method and the encapsulating structure thereof of a kind of lateral wall insulation protection of the present invention are not limited to above preferred embodiment; during as laser cutting disk 100; also can in air, carry out; the mixture of the oxide that the material of the insulating barrier I 202 forming is silicon and the nitride of silicon, plays insulation protection effect equally.Or when laser cutting disk 100, provide other easily to react the gas or the liquid that generate insulating protective layer with silicon matter.
In addition, except laser, other high-speed cutting modes or chemical corrosion method also can form side insulation protective layer while processing disk.
Therefore any those skilled in the art without departing from the spirit and scope of the present invention, any amendment, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all fall in the protection range that the claims in the present invention define.
Claims (10)
1. a chip packaging method for lateral wall insulation protection, its technical process is as follows:
Step 1, provide the disk (100) with chip electrode (102) and scribing road (12);
Step 2, laser knife (600) and disk (100) are placed in enclosure space, start laser knife (600), advanced in its scribing road (12) along disk (100), cut disk (100), form groove (103), O is provided simultaneously
2or N
2, in the insulating barrier I (202) of groove (103) the wall formation oxide of silicon or the nitride of silicon;
Step 3, adopt the method deposition SiO of PECVD on disk (100) surface
2/ SiN, forms insulating barrier II (210), and forms insulating barrier II opening (211), the surface of insulating barrier II opening (211) exposed chip electrode (102) in the top of chip electrode (102) by the method for corrosion or etching;
Step 4, by chemical plating or electroplating technology, on the surface of chip electrode (102), form metal coupling (300);
Step 5, at the upper overlay film (500) of disk (100), and spin upside down 180 °;
Step 6, by abrasive disc technique, attenuate is carried out in the back side of disk (100);
Step 7, by film coating process, paste back-protective layer (400) at disk (100) back;
Step 8, by sliver and striping (500), make single change of disk (100), form the chip-packaging structure of the lateral wall insulation protection of single.
2. chip packaging method according to claim 1 and 2, is characterized in that: described groove (103) degree of depth h is >=30 μ m.
3. chip packaging method according to claim 2, is characterized in that: the degree of depth h of described groove (103) is 100～250 μ m.
4. chip packaging method according to claim 1, it is characterized in that: the chip-packaging structure of described lateral wall insulation protection, it comprises silica-based body (101), chip electrode (102), insulating barrier I (202), insulating barrier II (210), metal coupling (300) and back-protective layer (400), wherein, chip electrode (102) embeds the upper surface of silica-based body (101), metal coupling (300) is positioned at the upper surface of silica-based body (101) and is connected with chip electrode (102), described insulating barrier I (202) is arranged at the sidewall of silica-based body (101), described insulating barrier II (210) is arranged at metal coupling (300) on silica-based body (101) part in addition, back-protective layer (400) is arranged at the lower surface of silica-based body (101).
5. according to the chip packaging method described in claim 1 or 4, it is characterized in that: the thickness of described insulating barrier I (202) is 0.5～5 μ m.
6. a chip packaging method for lateral wall insulation protection, its technical process is as follows:
Step 1, provide the disk (100) with chip electrode (102) and scribing road (12);
Step 2, adopt the method deposition SiO of PECVD on disk (100) surface
2/ SiN or coating polyimide, form insulating barrier II (210), and form insulating barrier II opening (211), the surface of insulating barrier II opening (211) exposed chip electrode (102) in the top of chip electrode (102) by the method for corrosion or etching;
Step 3, by chemical plating or electroplating technology, on the surface of chip electrode (102), form metal coupling (300);
Step 4, at the upper overlay film (500) of disk (100), and spin upside down 180 °;
Step 5, by abrasive disc technique, attenuate is carried out in the back side of disk (100);
Step 6, by film coating process, paste back-protective layer (400) at disk (100) back,
Step 7, laser knife (600) and disk (100) to be cut are placed in enclosure space, start laser knife (600), advanced in its scribing road (12) along disk (100), cut disk (100), O is provided simultaneously
2or N
2, in the insulating barrier I (202) of groove (103) the wall formation oxide of silicon or the nitride of silicon;
Step 8, by sliver and striping (500), make single change of disk (100), form the chip-packaging structure of the lateral wall insulation protection of single.
7. chip packaging method according to claim 6, is characterized in that: described disk (100) residual thickness h2 is >=30 μ m.
8. chip packaging method according to claim 7, is characterized in that: described disk (100) residue degree of depth h2 is 100～250 μ m.
9. chip packaging method according to claim 6, it is characterized in that: the chip-packaging structure of described lateral wall insulation protection, it comprises silica-based body (101), chip electrode (102), insulating barrier I (202), insulating barrier II (210), metal coupling (300) and back-protective layer (400), wherein, chip electrode (102) embeds the upper surface of silica-based body (101), metal coupling (300) is positioned at the upper surface of silica-based body (101) and is connected with chip electrode (102), described insulating barrier I (202) is arranged at the sidewall of silica-based body (101), the metal coupling (300) that described insulating barrier II (210) is arranged at silica-based body (101) upper surface part in addition, back-protective layer (400) is arranged at the lower surface of silica-based body (101).
10. according to the chip packaging method described in claim 6 or 9, it is characterized in that: the thickness of described insulating barrier I (202) is 0.5～5 μ m.
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